changes to improve timing. note that the minimal pause between two pulses is three...

diff --git a/mupix/Mupix8/sources/SlowControl/TestpulseGenerator.vhd b/mupix/Mupix8/sources/SlowControl/TestpulseGenerator.vhd
index 82aaac7fd70991d3a722ecefc15b2e918897dbd4..c5bb1b35cf50c2347b1acee154052ab101dcab11 100644 (file)
--- a/mupix/Mupix8/sources/SlowControl/TestpulseGenerator.vhd
+++ b/mupix/Mupix8/sources/SlowControl/TestpulseGenerator.vhd
@@ -9,97 +9,100 @@ use ieee.numeric_std.all;
 
 entity injection_generator is
   port (
-    rst                  : in  std_logic;--! reset input
-    clk                  : in  std_logic;--! clock input
-    pulse_length         : in  std_logic_vector(31 downto 0); --! length of injection pulse
-    pulse_pause          : in  std_logic_vector(31 downto 0); --! pause between pulses
-    pulse_number         : in  std_logic_vector(31 downto 0); --! number of pulses to send (adds one additional pulse)
-    pulse_start          : in  std_logic;--! start generation of pulse
-    pulse_o              : out std_logic --! output signal to mupix board
+    rst          : in  std_logic;       --! reset input
+    clk          : in  std_logic;       --! clock input
+    pulse_length : in  std_logic_vector(31 downto 0);  --! length of injection pulse
+    pulse_pause  : in  std_logic_vector(31 downto 0);  --! pause between pulses
+    pulse_number : in  std_logic_vector(31 downto 0);  --! number of pulses to send (adds one additional pulse)
+    pulse_start  : in  std_logic;       --! start generation of pulse
+    pulse_o      : out std_logic        --! output signal to mupix board
     );
 end injection_generator;
 
 
 architecture rtl of injection_generator is
 
-       type injection_generator_type is (idle, gen, pause);
-       signal pulse_i                 : std_logic;
-       signal injection_generator_fsm : injection_generator_type := idle;
-       signal length_counter          : unsigned(31 downto 0)    := (others => '0');
-       signal pause_counter           : unsigned(31 downto 0)    := (others => '0');
-       signal pulse_counter           : unsigned(31 downto 0)    := (others => '0');
-       
+  type injection_generator_type is (idle, gen, pause);
+  signal pulse_i                            : std_logic;
+  signal injection_generator_fsm            : injection_generator_type := idle;
+  signal length_counter, length_counter_reg : unsigned(31 downto 0)    := (others => '0');
+  signal pause_counter, pause_counter_reg   : unsigned(31 downto 0)    := (others => '0');
+  signal pulse_counter                      : unsigned(31 downto 0)    := (others => '0');
+
 begin
 
-       injection_gen : process(clk) is
-       begin
-               if rising_edge(clk) then
-                       if rst = '1' then
-                               length_counter          <= (others => '0');
-                               pause_counter           <= (others => '0');
-                               injection_generator_fsm <= idle;
-                               pulse_i                 <= '0';
-                       else
-                               case injection_generator_fsm is
-                                       when idle =>
-                                               pulse_i        <= '0';
-                                               length_counter <= (others => '0');
-                                               pulse_counter  <= (others => '0');
-                                               if pulse_start = '1' and unsigned(pulse_length) > 0 then
-                                                       injection_generator_fsm <= gen;
-                                               else
-                                                       injection_generator_fsm <= idle;
-                                               end if;
-                                       when gen =>
-                                               pulse_i        <= '1';
-                                               pause_counter  <= (others => '0');
-                                               length_counter <= length_counter + 1;
-                                               if unsigned(pulse_length) > 0 then
-                            if length_counter < unsigned(pulse_length) - 1 then
-                                injection_generator_fsm <= gen;
-                            else
-                                injection_generator_fsm <= pause;
-                            end if;
-                        else
-                            injection_generator_fsm <= idle;
-                                               end if;
-                                       when pause =>
-                                               pulse_i        <= '0';
-                        length_counter <= (others => '0');
-                                               pause_counter  <= pause_counter + 1;
-                                               if unsigned(pulse_pause) > 0 then
-                                                       if pause_counter < unsigned(pulse_pause) - 1 then
-                                injection_generator_fsm <= pause;
-                                                       else
-                                                               if unsigned(pulse_number) > 0 then
-                                                                       if pulse_counter < unsigned(pulse_number) then
-                                                                               pulse_counter <= pulse_counter + 1;
-                                                                               injection_generator_fsm <= gen;
-                                                                       else
-                                                                               injection_generator_fsm <= idle;
-                                                                       end if;
-                                                               else
-                                                                       injection_generator_fsm <= gen;
-                                                               end if;
-                                                       end if;
-                                               else
-                                                       injection_generator_fsm <= idle;
-                                               end if;
-                               end case;
-                       end if;
-               end if;
-       end process injection_gen;
-       
-       output_pipe : process (clk) is
-       begin
-               if rising_edge(clk) then
-                       if rst = '1' then
-                               pulse_o <= '0';
-                       else
-                               pulse_o <= pulse_i;
-                       end if;
-               end if;
-       end process output_pipe;
-       
-  
+  injection_gen : process(clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        length_counter          <= (others => '0');
+        pause_counter           <= (others => '0');
+        injection_generator_fsm <= idle;
+        pulse_i                 <= '0';
+      else
+        pause_counter_reg  <= pause_counter;
+        length_counter_reg <= length_counter;
+        case injection_generator_fsm is
+          when idle =>
+            pulse_i        <= '0';
+            length_counter <= (others => '0');
+            pulse_counter  <= (others => '0');
+            if pulse_start = '1' and unsigned(pulse_length) > 0 then
+              injection_generator_fsm <= gen;
+            else
+              injection_generator_fsm <= idle;
+            end if;
+          when gen =>
+            pulse_i        <= '1';
+            pause_counter  <= (others => '0');
+            length_counter <= length_counter + 1;
+            if unsigned(pulse_length) > 1 then
+              if length_counter_reg < unsigned(pulse_length) - 1 then
+                injection_generator_fsm <= gen;
+              else
+                injection_generator_fsm <= pause;
+                pulse_i        <= '0';
+              end if;
+            else
+              injection_generator_fsm <= idle;
+            end if;
+          when pause =>
+            pulse_i        <= '0';
+            length_counter <= (others => '0');
+            pause_counter  <= pause_counter + 1;
+            if unsigned(pulse_pause) > 3 then
+              if pause_counter_reg < unsigned(pulse_pause) - 3 then
+                injection_generator_fsm <= pause;
+              else
+                if unsigned(pulse_number) > 1 then
+                  if pulse_counter < unsigned(pulse_number) - 1 then
+                    pulse_counter           <= pulse_counter + 1;
+                    injection_generator_fsm <= gen;
+                  else
+                    injection_generator_fsm <= idle;
+                  end if;
+                else
+                  injection_generator_fsm <= gen;
+                end if;
+              end if;
+            else
+              injection_generator_fsm <= idle;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process injection_gen;
+
+  output_pipe : process (clk) is
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        pulse_o <= '0';
+      else
+        pulse_o <= pulse_i;
+      end if;
+    end if;
+  end process output_pipe;
+
+
 end rtl;

diff --git a/mupix/Mupix8/tb/TestPulseGeneratorTest.vhd b/mupix/Mupix8/tb/TestPulseGeneratorTest.vhd
new file mode 100644 (file)
index 0000000..f4149fe
--- /dev/null
+++ b/mupix/Mupix8/tb/TestPulseGeneratorTest.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity TestPulseGeneratorTest is
+end entity TestPulseGeneratorTest;
+
+
+architecture sim of TestPulseGeneratorTest is
+
+  component injection_generator is
+    port (
+      rst          : in  std_logic;
+      clk          : in  std_logic;
+      pulse_length : in  std_logic_vector(31 downto 0);
+      pulse_pause  : in  std_logic_vector(31 downto 0);
+      pulse_number : in  std_logic_vector(31 downto 0);
+      pulse_start  : in  std_logic;
+      pulse_o      : out std_logic);
+  end component injection_generator;
+
+  constant clk_period  : time  := 10 ns;
+  signal rst          : std_logic := '0';
+  signal clk          : std_logic;
+  signal pulse_length : std_logic_vector(31 downto 0) := (others => '0');
+  signal pulse_pause  : std_logic_vector(31 downto 0) := (others => '0');
+  signal pulse_number : std_logic_vector(31 downto 0) := (others => '0');
+  signal pulse_start  : std_logic := '0';
+  signal pulse_o      : std_logic;
+  
+begin  -- architecture sim
+
+  injection_generator_1: entity work.injection_generator
+    port map (
+      rst          => rst,
+      clk          => clk,
+      pulse_length => pulse_length,
+      pulse_pause  => pulse_pause,
+      pulse_number => pulse_number,
+      pulse_start  => pulse_start,
+      pulse_o      => pulse_o);
+
+  
+  clk_gen: process is
+  begin  -- process
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process clk_gen;
+
+  stim: process is
+  begin  -- process stim
+    wait for 100 ns;
+    pulse_length <= std_logic_vector(to_unsigned(4, 32));
+    pulse_pause  <= std_logic_vector(to_unsigned(2, 32));
+    pulse_number <= std_logic_vector(to_unsigned(1, 32));
+    wait for 50 ns;
+    pulse_start <= '1';
+    wait for clk_period;
+    pulse_start <= '0';
+    wait;
+  end process stim;
+
+end architecture sim;