Dirich update: input clock 200 MHz, flash connected to clock signal

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index f2e50e9f47c20240c8006db1ad7de7c061065e1c..6893cc942b67fe669a9e88c39a6821ce57db737f 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -49,12 +49,12 @@ begin
 SYS_CLK_OUT <= sys_clk_i;
 GSR_OUT     <= not pll_lock or clear_n_i;
 
-THE_PLL : entity work.pll_240_100
+THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input!
   port map(
     CLKI   => CLOCK_IN,
     CLKOP  => clock_200,
     CLKOS  => clock_100,
-    CLKOS2 => clock_240,
+    CLKOS2 => open, --clock_240,
     CLKOS3 => clock_120,
     LOCK   => pll_lock
     );  

diff --git a/cores/pll_240_100/pll_240_100.lpc b/cores/pll_240_100/pll_240_100.lpc
index dafb638ff1ede4a6bcf748ed060b0956e4afa026..b64866997ce91b93fab00ede3f588479411e6235 100644 (file)
--- a/cores/pll_240_100/pll_240_100.lpc
+++ b/cores/pll_240_100/pll_240_100.lpc
@@ -16,8 +16,8 @@ CoreRevision=5.8
 ModuleName=pll_240_100
 SourceFormat=vhdl
 ParameterFileVersion=1.0
-Date=01/06/2016
-Time=14:19:48
+Date=03/18/2016
+Time=16:38:06
 
 [Parameters]
 Verilog=0
@@ -27,16 +27,16 @@ Destination=Synplicity
 Expression=BusA(0 to 7)
 Order=Big Endian [MSB:LSB]
 IO=0
-CLKI_FREQ=240
-CLKI_DIV=6
+CLKI_FREQ=200
+CLKI_DIV=2
 ENABLE_HBW=DISABLED
 REFERENCE=0
 IOBUF=LVDS
 CLKOP_FREQ=200
 CLKOP_TOL=0.0
-CLKOP_DIV=3
+CLKOP_DIV=1
 CLKOP_ACTUAL_FREQ=200.000000
-CLKOP_MUXA=DISABLED
+CLKOP_MUXA=ENABLED
 CLKOS_Enable=ENABLED
 CLKOS_FREQ=100.00
 CLKOS_TOL=0.0
@@ -44,23 +44,23 @@ CLKOS_DIV=6
 CLKOS_ACTUAL_FREQ=100.000000
 CLKOS_MUXB=DISABLED
 CLKOS2_Enable=ENABLED
-CLKOS2_FREQ=100.00
+CLKOS2_FREQ=200
 CLKOS2_TOL=0.0
-CLKOS2_DIV=1
-CLKOS2_ACTUAL_FREQ=240.000000
-CLKOS2_MUXC=ENABLED
+CLKOS2_DIV=3
+CLKOS2_ACTUAL_FREQ=200.000000
+CLKOS2_MUXC=DISABLED
 CLKOS3_Enable=ENABLED
 CLKOS3_FREQ=120.00
 CLKOS3_TOL=0.0
 CLKOS3_DIV=5
 CLKOS3_ACTUAL_FREQ=120.000000
 CLKOS3_MUXD=DISABLED
-FEEDBK_PATH=CLKOP
-CLKFB_DIV=5
+FEEDBK_PATH=CLKOS
+CLKFB_DIV=1
 FRACN_ENABLE=DISABLED
 FRACN_DIV=
 VCO_RATE=600.000
-PLL_BW=4.966
+PLL_BW=8.185
 CLKOP_DPHASE=0
 CLKOP_APHASE=0.00
 CLKOP_TRIM_POL=Rising
@@ -90,4 +90,4 @@ PLL_LOCK_STK=DISABLED
 PLL_USE_SMI=DISABLED
 
 [Command]
-cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1
+cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 2

diff --git a/cores/pll_240_100/pll_240_100.vhd b/cores/pll_240_100/pll_240_100.vhd
index dfc5aa113af05f4a5bd5d96b0bc3908e621232bd..22dc39654d173c875cac9016fb7f136a9bceca3b 100644 (file)
--- a/cores/pll_240_100/pll_240_100.vhd
+++ b/cores/pll_240_100/pll_240_100.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1
 -- Module  Version: 5.7
---/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 -fdc /d/jspc22/trb/git/dirich/cores/pll_240_100/pll_240_100.fdc 
+--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 2 
 
--- Wed Jan  6 14:19:54 2016
+-- Fri Mar 18 16:38:06 2016
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -25,8 +25,8 @@ architecture Structure of pll_240_100 is
     signal REFCLK: std_logic;
     signal CLKOS3_t: std_logic;
     signal CLKOS2_t: std_logic;
-    signal CLKOS_t: std_logic;
     signal CLKOP_t: std_logic;
+    signal CLKOS_t: std_logic;
     signal scuba_vhi: std_logic;
     signal scuba_vlo: std_logic;
 
@@ -38,12 +38,12 @@ architecture Structure of pll_240_100 is
     attribute ICP_CURRENT : string; 
     attribute LPF_RESISTOR : string; 
     attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "120.000000";
-    attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "240.000000";
+    attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "200.000000";
     attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "100.000000";
     attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000";
-    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000";
-    attribute ICP_CURRENT of PLLInst_0 : label is "12";
-    attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "9";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "72";
     attribute syn_keep : boolean;
     attribute NGD_DRC_MASK : integer;
     attribute NGD_DRC_MASK of Structure : architecture is 1;
@@ -60,17 +60,17 @@ begin
         generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
         STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
         CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  4, CLKOS2_FPHASE=>  0, 
-        CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  5, 
-        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  2, PLL_LOCK_MODE=>  0, 
+        CLKOS2_CPHASE=>  2, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  5, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  0, PLL_LOCK_MODE=>  0, 
         CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
         CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
         OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED", 
         OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", 
         OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 
-        OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  5, 
-        CLKOS2_DIV=>  1, CLKOS_DIV=>  6, CLKOP_DIV=>  3, CLKFB_DIV=>  5, 
-        CLKI_DIV=>  6, FEEDBK_PATH=> "CLKOP")
-        port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 
+        OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  5, 
+        CLKOS2_DIV=>  3, CLKOS_DIV=>  6, CLKOP_DIV=>  1, CLKFB_DIV=>  1, 
+        CLKI_DIV=>  2, FEEDBK_PATH=> "CLKOS")
+        port map (CLKI=>CLKI, CLKFB=>CLKOS_t, PHASESEL1=>scuba_vlo, 
             PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
             PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
             STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 

diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf
index 53655150eb6f65c47d47560a5cc8b7fd184d097a..a725c59e49d3d9c480718a1aea1f2eae902c7ab6 100644 (file)
--- a/dirich/dirich.lpf
+++ b/dirich/dirich.lpf
@@ -12,8 +12,8 @@ FREQUENCY PORT CLOCK_CAL       33 MHz;
 
 BLOCK PATH TO   PORT "LED*";
 BLOCK PATH TO   PORT "PROGRAMN";
-BLOCK PATH TO   PORT "TEMPSENS";
-BLOCK PATH FROM PORT "TEMPSENS";
+BLOCK PATH TO   PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
 BLOCK PATH TO   PORT "TEST_LINE*";
 
 MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index 3893f643f41a69231a64a08274cc523cec24f71d..1573031eff3461df0b65fa9c85f7f1f3664e7d74 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -84,6 +84,7 @@ architecture dirich_arch of dirich is
   signal sed_error_i       : std_logic;
   signal clock_select      : std_logic;
   signal bus_master_active : std_logic;
+  signal flash_clk_i       : std_logic;
   
   signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
 
@@ -96,6 +97,15 @@ architecture dirich_arch of dirich is
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
 
+
+  component usrmclk
+    port(
+      USRMCLKI : in std_ulogic;
+      USRMCLKTS : in std_ulogic
+      );
+  end component;
+  
+  
 begin
 
 ---------------------------------------------------------------------------
@@ -251,7 +261,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       
       --Flash & Reload
       FLASH_CS    => FLASH_CS,
-      FLASH_CLK   => FLASH_CLK,
+      FLASH_CLK   => flash_clk_i,
       FLASH_IN    => FLASH_OUT,
       FLASH_OUT   => FLASH_IN,
       PROGRAMN    => PROGRAMN,
@@ -287,6 +297,13 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       DEBUG_OUT  => debug_tools
       );
 
+      
+THE_FLASH_CLOCK : usrmclk
+  port map(
+    USRMCLKI  => flash_clk_i,
+    USRMCLKTS => '0'
+    );
+      
 ---------------------------------------------------------------------------
 -- PWM / Thresh
 ---------------------------------------------------------------------------