]> jspc29.x-matter.uni-frankfurt.de Git - jtag_mvd.git/commitdiff
lastest MVD JTAG vhdl code, JM
authorHadaq in Frankfurt <hadaq@frankfurt>
Fri, 15 Mar 2013 17:23:10 +0000 (18:23 +0100)
committerHadaq in Frankfurt <hadaq@frankfurt>
Fri, 15 Mar 2013 17:23:10 +0000 (18:23 +0100)
vhdl/code/jtag_mvd.vhd

index ef0e5102491cc6fd667fe615385669c4ae132bd6..516ac6b1be0485ceabdd17a491a50ec85bf90d82 100644 (file)
@@ -161,6 +161,7 @@ architecture jtag_mvd_arch of jtag_mvd is
   signal waitbeforestart_counter                    : cnt_t;
   signal waitbeforestart                            : unsigned(27 downto 0);
   signal waitbeforestart_counter_allchains          : unsigned(27 downto 0);
+  signal waitbeforestart_mclk                       : unsigned(27 downto 0);
   
 begin
 
@@ -357,7 +358,7 @@ end generate;
                              
   idle_out_mclk              <= idle_out when rising_edge(clk_maps);
   prog_jtag_finished_mclk    <= prog_jtag_finished  when rising_edge(clk_maps);
-  
+  waitbeforestart_mclk       <= waitbeforestart when rising_edge(clk_maps);
   
 ---------------------------------------------------------------------------
 -- Generate control signals for MAPS
@@ -432,14 +433,14 @@ end generate;
                 init_seq_mclk(i) <= isRUN_JTAG;
               when isRUN_JTAG =>
                 if(resetafterfirstwrite(i) = '1') then
-                  if(request_reset(i) = '1') then
+                  if(request_reset_mclk(i) = '1') then
                     trigger_reset_pulse_mclk(i) <= '1';
                   end if;
                 end if;
                 -- wait for completion of potential copy ram request and then finishing of run
                 if(idle_out_mclk(i) = '1') then
                   init_seq_mclk(i) <= isWAITBEFORESTART;
-                  waitbeforestart_counter(i) <= waitbeforestart;
+                  waitbeforestart_counter(i) <= waitbeforestart_mclk;
                 end if;
               when isWAITBEFORESTART =>
                 waitbeforestart_counter(i) <= waitbeforestart_counter(i) -1;
@@ -491,7 +492,7 @@ end generate;
 
             if(and_all(idle_out_mclk) = '1') then
               init_seq_allchains_mclk <= isWAITBEFORESTART;
-              waitbeforestart_counter_allchains <= waitbeforestart;
+              waitbeforestart_counter_allchains <= waitbeforestart_mclk;
             end if;
           when isWAITBEFORESTART =>
             waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1;