signal waitbeforestart_counter : cnt_t;
signal waitbeforestart : unsigned(27 downto 0);
signal waitbeforestart_counter_allchains : unsigned(27 downto 0);
+ signal waitbeforestart_mclk : unsigned(27 downto 0);
begin
idle_out_mclk <= idle_out when rising_edge(clk_maps);
prog_jtag_finished_mclk <= prog_jtag_finished when rising_edge(clk_maps);
-
+ waitbeforestart_mclk <= waitbeforestart when rising_edge(clk_maps);
---------------------------------------------------------------------------
-- Generate control signals for MAPS
init_seq_mclk(i) <= isRUN_JTAG;
when isRUN_JTAG =>
if(resetafterfirstwrite(i) = '1') then
- if(request_reset(i) = '1') then
+ if(request_reset_mclk(i) = '1') then
trigger_reset_pulse_mclk(i) <= '1';
end if;
end if;
-- wait for completion of potential copy ram request and then finishing of run
if(idle_out_mclk(i) = '1') then
init_seq_mclk(i) <= isWAITBEFORESTART;
- waitbeforestart_counter(i) <= waitbeforestart;
+ waitbeforestart_counter(i) <= waitbeforestart_mclk;
end if;
when isWAITBEFORESTART =>
waitbeforestart_counter(i) <= waitbeforestart_counter(i) -1;
if(and_all(idle_out_mclk) = '1') then
init_seq_allchains_mclk <= isWAITBEFORESTART;
- waitbeforestart_counter_allchains <= waitbeforestart;
+ waitbeforestart_counter_allchains <= waitbeforestart_mclk;
end if;
when isWAITBEFORESTART =>
waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1;