gen_link_reset : if IS_SYNC_SLAVE = 1 generate
- link_reset_pulse : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
- D_IN(0) => make_link_reset_i,
- D_OUT(0) => make_link_reset_sys_i);
+ link_reset_pulse : pulse_sync port map( CLK_A_IN => CLK_RXI, CLK_B_IN => CLK_SYS,
+ PULSE_A_IN => make_link_reset_i,
+ PULSE_B_OUT => make_link_reset_sys_i);
link_reset_send : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
D_IN(0) => send_link_reset_i,
D_OUT(0) => send_link_reset_real_i);
signal reg_rx_data_in : std_logic_vector(7 downto 0);
signal reg_rx_k_in : std_logic;
-signal reset_cnt : unsigned(7 downto 0);
+signal reset_cnt : unsigned(11 downto 0);
begin
rx_state <= GET_IDLE;
when K_RST =>
rx_state <= MAKE_RESET;
- reset_cnt <= x"00";
+ reset_cnt <= x"000";
when K_DLM =>
rx_state <= GET_DLM;
when K_REQ =>
send_link_reset_i <= '1';
make_reset_i <= '0';
got_link_ready_i <= '0';
- if reset_cnt < x"c0" then
+ if reset_cnt < x"1ff" then
reset_cnt <= reset_cnt + 1;
- else
- make_reset_i <= '1';
+-- else
+-- make_reset_i <= '1';
end if;
- elsif reset_cnt >= x"c0" or reset_cnt < x"80" then
+ elsif reset_cnt >= x"1ff" or reset_cnt < x"40" then
send_link_reset_i <= '0';
make_reset_i <= '1';
rx_state <= SLEEP;
else
- reset_cnt <= reset_cnt + 1;
+ if reset_cnt < x"1ff" then
+ reset_cnt <= reset_cnt + 1;
+ end if;
send_link_reset_i <= '1';
end if;
if RESET_IN = '1' or RX_RESET_FINISHED = '0' then
rx_state <= SLEEP;
- make_reset_i <= '0';
+ if rx_state = MAKE_RESET then
+ make_reset_i <= '1';
+ else
+ make_reset_i <= '0';
+ end if;
send_link_reset_i <= '0';
end if;
end process;
architecture trb_net16_api_base_arch of trb_net16_api_base is
-- Placer Directives
- attribute HGROUP : string;
+-- attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of trb_net16_api_base_arch : architecture is "API_group";
+-- attribute HGROUP of trb_net16_api_base_arch : architecture is "API_group";
-- signals for the APL to INT fifo:
signal med_data_in : std_logic_vector (mii*c_DATA_WIDTH-1 downto 0);
signal med_packet_num_in : std_logic_vector (mii*c_NUM_WIDTH-1 downto 0);
signal med_read_out : std_logic_vector (mii-1 downto 0);
-signal med_stat_op : std_logic_vector (mii*16+15 downto 0);
+signal med_stat_op : std_logic_vector (mii*16-1 downto 0);
signal med_ctrl_op : std_logic_vector (mii*16-1 downto 0);
signal rdack, wrack : std_logic;
begin
if rising_edge(CLK) then
reset_i <= RESET;
- reset_i_mux_io <= MED_STAT_OP(mii*16+14) or reset_i;
+ reset_i_mux_io <= MEDIA_MED2INT(mii).stat_op(14) or reset_i;
end if;
end process;
end generate;
- hub_make_network_reset <= external_send_reset_long or med_stat_op((MII_NUMBER-1)*16+15);
+ hub_make_network_reset <= external_send_reset_long;
make_gbe_reset : process begin
- wait until rising_edge(CLK);
- if EXTERNAL_SEND_RESET = '1' or med_stat_op((MII_NUMBER-1)*16+15) = '1' then
+ wait until rising_edge(CLK); --REMOVED AUTO RESET FROM highest port!
+ if EXTERNAL_SEND_RESET = '1' then
external_send_reset_long <= '1';
external_send_reset_timer <= '1';
end if;
- if timer_ticks(1) = '1' then
+ if timer_ticks(0) = '1' then
external_send_reset_timer <= '0';
external_send_reset_long <= external_send_reset_timer;
end if;
STAT => open
);
io_error_in <= MEDIA_MED2INT(mii).stat_op(2 downto 0);
- med_stat_op(mii*16+15 downto mii*16) <= MEDIA_MED2INT(mii).stat_op;
+-- med_stat_op(mii*16+15 downto mii*16) <= MEDIA_MED2INT(mii).stat_op;
---------------------------------------------------------------------
-- IPU Channel
---------------------------------------------------------------------