Priority switch to: soda source with soda on 40MHz repetition rate.
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.0" title="CU_trb3_soda_client" device="LFE3-150EA-8FN672C" default_implementation="CU_trb3_soda_client">
+ <Options>
+ <Option name="HDL type" value="VHDL"/>
+ </Options>
+ <Implementation title="CU_trb3_soda_client" dir="CU_trb3_soda_client" description="CU_trb3_soda_client" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="Cu_trb3_periph_sodaclient" top="Cu_trb3_periph_sodaclient"/>
+ <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_only_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
+ <Options/>
+ </Source>
+ <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
+ <Options/>
+ </Source>
+ <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/Cu_trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="Cu_trb3_periph_sodaclient"/>
+ </Source>
+ <Source name="Cu_trb3_soda_client.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ <Source name="Cu_trb3_soda_client.rvl" type="Reveal" type_short="Reveal">
+ <Options/>
+ </Source>
+ <Source name="Cu_trb3_soda_dual_client.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE">
+ <Options/>
+ </Source>
+ <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="soda_client1.sty"/>
+</BaliProject>
--- /dev/null
+rvl_alias "reveal_ist_125" "the_sync_link/rx_full_clk";
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+# SYSCONFIG MCCLK_FREQ = 2.5;
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+#################################################################
+# Clock I/O
+#################################################################
+#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+#LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
+#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
+#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
+#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
+#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
+#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
+#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
+#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
+#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
+#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
+#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
+#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
+#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
+#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
+#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
+#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
+#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
+#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
+#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
+#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
+#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
+#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
+#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
+#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
+#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+#GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+BLOCK JTAGPATHS ;
+## IOBUF ALLPORTS ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="2.1.0">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>1</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
+ <FileTime>09/24/13 10:52:51</FileTime>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>2</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/CU_trb3_periph_soda_client_20141112.bit</File>
+ <FileTime>11/12/14 10:02:17</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>3</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
+ <FileTime>09/03/13 16:32:30</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>4</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>5</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP3</Family>
+ <Name>LFE3-150EA</Name>
+ <IDCode>0x01015043</IDCode>
+ <Package>All</Package>
+ <PON>LFE3-150EA</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140915.bit</File>
+ <FileTime>09/11/14 08:56:37</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="TRUE"/>
+ <Pos>6</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
+ <FileTime>04/10/13 09:35:41</FileTime>
+ <JedecChecksum>0x1C57</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0xFFFFFFFF</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <SelectedProg value="FALSE"/>
+ <Pos>7</Pos>
+ <Vendor>Lattice</Vendor>
+ <Family>ispCLOCK</Family>
+ <Name>ispPAC-CLK5410D</Name>
+ <IDCode>0x00190043</IDCode>
+ <Package>64-pin QFNS</Package>
+ <PON>ispPAC-CLK5410D-XXSN64C</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>32</PreloadLength>
+ <IOVectorData>0x00000000</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>ispVM</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <VerifyUsercode value="FALSE"/>
+ </ProjectOptions>
+ <CableOptions>
+ <CableName>USB</CableName>
+ <PortAdd>EzUSB-0</PortAdd>
+ </CableOptions>
+</ispXCF>
--- /dev/null
+---------------
+-- TOP LEVEL --
+---------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.med_sync_define.all;
+use work.version.all;
+
+entity Cu_trb3_periph_sodaclient is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+ USE_125_MHZ : integer := c_NO;
+ CLOCK_FREQUENCY : integer := 100;
+ NUM_INTERFACES : integer := 1
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --Trigger
+ --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+ --Serdes Clocks - do not use
+ --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+
+ --serdes I/O - connect as you like, no real use
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+ --SFP_MOD1 : inout std_logic_vector(6 downto 1);
+ --SFP_MOD2 : inout std_logic_vector(6 downto 1);
+ --SFP_RATESEL : out std_logic_vector(6 downto 1);
+ --SFP_TXFAULT : in std_logic_vector(6 downto 1);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+ attribute syn_useioff of TEST_LINE : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+
+
+end entity;
+
+architecture Cu_trb3_periph_sodaclient_arch of Cu_trb3_periph_sodaclient is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
+
+ --Clock / Reset
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+
+ signal clk_100_osc : std_logic;
+ signal clk_200_osc : std_logic;
+ signal rx_full_clk : std_logic;
+ signal rx_half_clk : std_logic;
+ signal tx_full_clk : std_logic;
+ signal tx_half_clk : std_logic;
+-- signal clk_tdc : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ --Cu media interface
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+ signal sci1_nack : std_logic;
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
+
+-- SiO media interface
+-- signal sci2_ack : std_logic;
+-- signal sci2_write : std_logic;
+-- signal sci2_read : std_logic;
+-- signal sci2_data_in : std_logic_vector(7 downto 0);
+-- signal sci2_data_out : std_logic_vector(7 downto 0);
+-- signal sci2_addr : std_logic_vector(8 downto 0);
+-- signal sci2_nack : std_logic;
+
+ --SODA
+ signal tx_dlm_i : std_logic;
+ signal rx_dlm_i : std_logic;
+ signal tx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal make_reset : std_logic;
+ signal tx_dlm_preview_S : std_logic; --PL!
+ signal link_phase_S : std_logic; --PL!
+ signal rx_cdr_lol_S : std_logic;
+ signal link_locked_S : std_logic; --PL!
+
+ -- SODA slow controll
+ signal soda_ack : std_logic;
+-- signal soda_nack : std_logic;
+ signal soda_write : std_logic;
+ signal soda_read : std_logic;
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_leds : std_logic_vector(3 downto 0);
+
+ signal link_debug_in_S : std_logic_vector(31 downto 0);
+ signal general_reset_i : std_logic := '1';
+
+ signal soda_counter_i : unsigned(3 downto 0);
+ attribute syn_keep of soda_counter_i : signal is true;
+
+ -- fix signal names for constraining
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_preserve of rx_full_clk : signal is true;
+ attribute syn_keep of rx_full_clk : signal is true;
+ attribute syn_preserve of rx_half_clk : signal is true;
+ attribute syn_keep of rx_half_clk : signal is true;
+ attribute syn_preserve of tx_full_clk : signal is true;
+ attribute syn_keep of tx_full_clk : signal is true;
+ attribute syn_preserve of tx_half_clk : signal is true;
+ attribute syn_keep of tx_half_clk : signal is true;
+ attribute syn_preserve of clk_100_osc : signal is true;
+ attribute syn_keep of clk_100_osc : signal is true;
+ attribute syn_preserve of clk_200_osc : signal is true;
+ attribute syn_keep of clk_200_osc : signal is true;
+ attribute syn_preserve of tx_dlm_i : signal is true;
+ attribute syn_keep of tx_dlm_i : signal is true;
+ attribute syn_preserve of rx_dlm_i : signal is true;
+ attribute syn_keep of rx_dlm_i : signal is true;
+
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+
+ LED_RX <= (others => '0'); -- otherwise it is floating
+ LED_TX <= (others => '0'); -- otherwise it is floating
+ LED_LINKOK <= (others => '0'); -- otherwise it is floating
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_osc, --rx_half_clk, PL 111114, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+--gen_200_PLL : if USE_125_MHZ = c_NO generate
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_osc,
+ CLKOK => clk_200_osc,
+ LOCK => pll_lock
+ );
+--end generate;
+
+--gen_125 : if USE_125_MHZ = c_YES generate
+-- clk_100_osc <= CLK_GPLL_LEFT;
+-- clk_200_osc <= CLK_GPLL_LEFT;
+--end generate;
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
+ USE_125_MHZ => USE_125_MHZ,
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
+ )
+ port map(
+ CLK => clk_200_osc,
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => open,
+ CLK_RX_FULL_OUT => open,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(4),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100b000",
+ REGIO_INIT_ADDRESS => x"f35a",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 9, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 256,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 256
+ )
+ port map(
+ CLK => clk_100_osc, --rx_half_clk, PL 111114
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out(0),
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in(0),
+ MED_DATAREADY_IN => med_dataready_in(0),
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out(0),
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => '0',
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => open,
+ LVL1_VALID_TIMING_TRG_OUT => open,
+ LVL1_VALID_NOTIMING_TRG_OUT => open,
+ LVL1_INVALID_TRG_OUT => open,
+
+ LVL1_TRG_TYPE_OUT => open,
+ LVL1_TRG_NUMBER_OUT => open,
+ LVL1_TRG_CODE_OUT => open,
+ LVL1_TRG_INFORMATION_OUT => open,
+ LVL1_INT_TRG_NUMBER_OUT => open,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => open,
+ TRG_TIMEOUT_DETECTED_OUT => open,
+ TRG_SPURIOUS_TRG_OUT => open,
+ TRG_MISSING_TMG_TRG_OUT => open,
+ TRG_SPIKE_DETECTED_OUT => open,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => '1',
+ FEE_TRG_STATUSBITS_IN => (others => '0'),
+ FEE_DATA_IN => (others => '0'),
+ FEE_DATA_WRITE_IN(0) => '0',
+ FEE_DATA_FINISHED_IN(0) => '1',
+ FEE_DATA_ALMOST_FULL_OUT(0) => open,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
+ )
+ port map(
+ CLK => clk_100_osc, --rx_half_clk, PL 111114
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(1) => sci1_read,
+ BUS_READ_ENABLE_OUT(2) => soda_read,
+
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,
+ BUS_WRITE_ENABLE_OUT(2) => soda_write,
+
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in,
+
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
+ BUS_ADDR_OUT(2*16+3 downto 2*16) => soda_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
+
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_IN(2*32+31 downto 2*32) => soda_data_out,
+
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_DATAREADY_IN(1) => sci1_ack,
+ BUS_DATAREADY_IN(2) => soda_ack,
+
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => sci1_ack,
+ BUS_WRITE_ACK_IN(2) => soda_ack,
+
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
+ port map(
+ CLK_IN => clk_100_osc, --rx_half_clk, PL 111114
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+
+---------------------------------------------------------------------------
+-- The synchronous interface for Soda tests
+---------------------------------------------------------------------------
+
+THE_SYNC_LINK : soda_only_ecp3_sfp_sync_up
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ OSCCLK => clk_200_osc, --clk_raw_internal,
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ RX_HALF_CLK_OUT => rx_half_clk, --soda_rx_clock_half,
+ RX_FULL_CLK_OUT => rx_full_clk, --soda_rx_clock_full,
+ TX_HALF_CLK_OUT => tx_half_clk,
+ TX_FULL_CLK_OUT => tx_full_clk,
+ RX_CDR_LOL_OUT => rx_cdr_lol_S,
+
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => rx_dlm_word,
+ TX_DLM => tx_dlm_i,
+ TX_DLM_WORD => tx_dlm_word,
+ TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
+ LINK_PHASE_OUT => link_phase_S, --PL!
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(3), --(1),
+ SD_LOS_IN => SFP_LOS(3), --(1),
+ SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1),
+
+ SCI_DATA_IN => (others => '0'), --sci2_data_in,
+ SCI_DATA_OUT => open, --sci2_data_out,
+ SCI_ADDR => (others => '0'), --sci2_addr,
+ SCI_READ => '0', --sci2_read,
+ SCI_WRITE => '0', --sci2_write,
+ SCI_ACK => open, --sci2_ack,
+ SCI_NACK => open --sci2_nack
+ );
+
+
+-- SFP_TXDIS(1) <= sfp_txdis_S(1);
+ SFP_TXDIS <= sfp_txdis_S;
+
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
+
+ A_SODA_CLIENT : soda_client
+ port map(
+ SYSCLK => rx_half_clk, --clk_100_osc,
+ SODACLK => rx_full_clk,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ RX_DLM_WORD_IN => rx_dlm_word,
+ RX_DLM_IN => rx_dlm_i,
+ TX_DLM_OUT => tx_dlm_i,
+ TX_DLM_WORD_OUT => tx_dlm_word,
+ TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
+ LINK_PHASE_IN => link_phase_S,
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read,
+ SODA_WRITE_IN => soda_write,
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => soda_leds,
+ LINK_DEBUG_IN => link_debug_in_S
+ );
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
+ LED_GREEN <= time_counter(25); --med_stat_op(12); --tx_pll_lol
+ LED_RED <= med_stat_op(11); --rx_cdr_lol
+-- LED_ORANGE <= not reset_i when rising_edge(clk_100_osc);
+-- LED_YELLOW <= soda_leds(0); --'1';
+-- LED_GREEN <= not med_stat_op(9);
+-- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+-- LED_ORANGE <= soda_leds(0);
+-- LED_YELLOW <= soda_leds(1);
+-- LED_GREEN <= soda_leds(2);
+-- LED_RED <= soda_leds(3);
+
+---------------------------------------------------------------------------
+-- DEBUG
+---------------------------------------------------------------------------
+ link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
+ link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ clock_counter_proc : process(clk_100_osc)
+ begin
+ if rising_edge(clk_100_osc) then
+ time_counter <= time_counter + 1;
+ end if;
+ end process;
+
+ process(rx_full_clk) --soda_rx_clock_full) --clk_soda_i)
+ begin
+ if rising_edge(rx_full_clk) then
+ soda_counter_i <= soda_counter_i+1;
+ end if;
+ end process;
+
+ TEST_LINE(0) <= time_counter(1);
+ TEST_LINE(1) <= '0';
+ TEST_LINE(2) <= '0';
+ TEST_LINE(3) <= soda_counter_i(2);
+ TEST_LINE(4) <= '0';
+ TEST_LINE(5) <= '0';
+ TEST_LINE(6) <= rx_half_clk;
+ TEST_LINE(7) <= '0';
+ TEST_LINE(8) <= '0';
+
+ TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating
+
+
+end Cu_trb3_periph_sodaclient_arch;
\ No newline at end of file
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "serdes_sync_upstream.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_EXT";
+-- CH2_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_upstream is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_upstream.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+-- CH2 --
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end serdes_sync_upstream;
+
+
+architecture serdes_sync_upstream_arch of serdes_sync_upstream is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal tx_full_clk_ch3_sig : std_logic;
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => open,
+ FF_RX_H_CLK_1 => open,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpsc_vlo,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => open,
+ FF_RX_D_1_1 => open,
+ FF_RX_D_1_2 => open,
+ FF_RX_D_1_3 => open,
+ FF_RX_D_1_4 => open,
+ FF_RX_D_1_5 => open,
+ FF_RX_D_1_6 => open,
+ FF_RX_D_1_7 => open,
+ FF_RX_D_1_8 => open,
+ FF_RX_D_1_9 => open,
+ FF_RX_D_1_10 => open,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => fpsc_vlo,
+ FFC_RXPWDNB_1 => fpsc_vlo,
+ FFS_RLOS_LO_1 => open,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => open,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => fpsc_vlo,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => fpsc_vlo,
+ HDINN2 => fpsc_vlo,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => open,
+ FF_RX_H_CLK_2 => open,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpsc_vlo,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => open,
+ FF_RX_D_2_1 => open,
+ FF_RX_D_2_2 => open,
+ FF_RX_D_2_3 => open,
+ FF_RX_D_2_4 => open,
+ FF_RX_D_2_5 => open,
+ FF_RX_D_2_6 => open,
+ FF_RX_D_2_7 => open,
+ FF_RX_D_2_8 => open,
+ FF_RX_D_2_9 => open,
+ FF_RX_D_2_10 => open,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => fpsc_vlo,
+ FFC_RXPWDNB_2 => fpsc_vlo,
+ FFS_RLOS_LO_2 => open,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => sci_wrdata(7),
+ SCIWDATA6 => sci_wrdata(6),
+ SCIWDATA5 => sci_wrdata(5),
+ SCIWDATA4 => sci_wrdata(4),
+ SCIWDATA3 => sci_wrdata(3),
+ SCIWDATA2 => sci_wrdata(2),
+ SCIWDATA1 => sci_wrdata(1),
+ SCIWDATA0 => sci_wrdata(0),
+ SCIADDR5 => sci_addr(5),
+ SCIADDR4 => sci_addr(4),
+ SCIADDR3 => sci_addr(3),
+ SCIADDR2 => sci_addr(2),
+ SCIADDR1 => sci_addr(1),
+ SCIADDR0 => sci_addr(0),
+ SCIRDATA7 => sci_rddata(7),
+ SCIRDATA6 => sci_rddata(6),
+ SCIRDATA5 => sci_rddata(5),
+ SCIRDATA4 => sci_rddata(4),
+ SCIRDATA3 => sci_rddata(3),
+ SCIRDATA2 => sci_rddata(2),
+ SCIRDATA1 => sci_rddata(1),
+ SCIRDATA0 => sci_rddata(0),
+ SCIENAUX => fpsc_vhi,
+ SCISELAUX => sci_sel_quad,
+ SCIRD => sci_rd,
+ SCIWSTN => sci_wrn,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => rst_qd_c,
+ FFC_TRST => tx_serdes_rst_c,
+ FFS_PLOL => tx_pll_lol_qd_sig,
+ FFC_SYNC_TOGGLE => fpsc_vlo,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_upstream_arch ;
SCI_ACK : out std_logic := '0';
SCI_NACK : out std_logic := '0';
-- Status and control port
- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
+-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
+-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
end generate;
-end med_ecp3_sfp_4_sync_down_arch;
\ No newline at end of file
+end med_ecp3_sfp_4_sync_down_arch;
--- /dev/null
+--4 channel Media interface for Lattice ECP3 using PCS at 2GHz
+
+LIBRARY IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_unsigned.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+use work.soda_components.all;
+
+entity med_ecp3_sfp_4_sync_down_EP is
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
+ port(
+ OSC_CLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+
+ --Sync operation
+ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
+ SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
+ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
+ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
+-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+end entity;
+
+
+architecture med_ecp3_sfp_4_sync_down_EP_arch of med_ecp3_sfp_4_sync_down_EP is
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of med_ecp3_sfp_4_sync_down_EP_arch : architecture is "media_downlink_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of med_ecp3_sfp_4_sync_down_EP_arch : architecture is "off";
+
+
+
+signal clk_200_osc : std_logic;
+signal clk_200_txdata : std_logic;
+--signal clk_200_rxdn : std_logic_vector(3 downto 0);
+--signal clk_200_i : std_logic_vector(3 downto 0);
+signal rx_full_clk : std_logic_vector(3 downto 0);
+signal rx_half_clk : std_logic_vector(3 downto 0);
+signal tx_full_clk : std_logic_vector(3 downto 0);
+signal tx_half_clk : std_logic_vector(3 downto 0);
+
+signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
+signal tx_k : std_logic_vector(3 downto 0);
+signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
+signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
+
+signal rst_n : t_HUB_BIT;
+signal rst : t_HUB_BIT; -- PL!
+signal rx_serdes_rst : t_HUB_BIT;
+signal tx_serdes_rst : std_logic := '0';
+signal tx_pcs_rst : t_HUB_BIT;
+signal rx_pcs_rst : t_HUB_BIT;
+signal rst_qd : t_HUB_BIT;
+signal rst_down_quad : std_logic;
+--signal serdes_rst_qd : t_HUB_BIT;
+signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad
+signal sd_los_i : t_HUB_BIT; --PL!
+
+signal rx_los_low : t_HUB_BIT;
+signal lsm_status : t_HUB_BIT;
+signal rx_cdr_lol : t_HUB_BIT;
+signal tx_pll_lol : t_HUB_BIT;
+signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
+
+signal sci_ch_i : std_logic_vector(3 downto 0);
+signal sci_qd_i : std_logic;
+signal sci_reg_i : std_logic;
+signal sci_addr_i : std_logic_vector(8 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+--signal sci_write_shift_i : std_logic_vector(2 downto 0);
+--signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
+signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
+signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
+signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL!
+signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
+signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
+signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
+signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0);
+
+signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0');
+
+signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
+signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
+
+signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
+signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
+signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
+signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
+signal debug_reg : std_logic_vector(63 downto 0);
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state : sci_ctrl;
+signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0');
+
+begin
+
+
+--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+
+clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!!
+clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
+
+
+gen_clocks : for i in 0 to 3 generate
+
+ rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
+ rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
+
+ RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
+ RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
+ TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
+ TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
+
+-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
+-- clk_200_i(i) <= rx_full_clk(i);
+-- end generate;
+
+-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+-- clk_200_i(i) <= clk_200_txdata;
+-- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
+-- end generate;
+end generate;
+
+-------------------------------------------------
+-- Serdes
+-------------------------------------------------
+THE_SERDES : entity work.serdes_4_sync_downstream
+ port map(
+ -- CHANNEL0 --
+ hdinp_ch0 => SD_RXD_P_IN(0),
+ hdinn_ch0 => SD_RXD_N_IN(0),
+ hdoutp_ch0 => SD_TXD_P_OUT(0),
+ hdoutn_ch0 => SD_TXD_N_OUT(0),
+ rxiclk_ch0 => clk_200_txdata, --clk_200_i(0),
+ sci_sel_ch0 => sci_ch_i(0),
+ txiclk_ch0 => clk_200_txdata,
+ rx_full_clk_ch0 => rx_full_clk(0),
+ rx_half_clk_ch0 => rx_half_clk(0),
+ tx_full_clk_ch0 => tx_full_clk(0),
+ tx_half_clk_ch0 => tx_half_clk(0),
+ fpga_rxrefclk_ch0 => clk_200_osc,
+ txdata_ch0 => tx_data(0),
+ tx_k_ch0 => tx_k(0),
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data(0),
+ rx_k_ch0 => rx_k(0),
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error(0),
+ rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst(0),
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst(0),
+ rx_pwrup_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low(0),
+ lsm_status_ch0_s => lsm_status(0),
+ rx_cdr_lol_ch0_s => rx_cdr_lol(0),
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
+ -- CHANNEL1 --
+ hdinp_ch1 => SD_RXD_P_IN(1),
+ hdinn_ch1 => SD_RXD_N_IN(1),
+ hdoutp_ch1 => SD_TXD_P_OUT(1),
+ hdoutn_ch1 => SD_TXD_N_OUT(1),
+ rxiclk_ch1 => clk_200_txdata, --clk_200_i(1),
+ sci_sel_ch1 => sci_ch_i(1),
+ txiclk_ch1 => clk_200_txdata,
+ rx_full_clk_ch1 => rx_full_clk(1),
+ rx_half_clk_ch1 => rx_half_clk(1),
+ tx_full_clk_ch1 => tx_full_clk(1),
+ tx_half_clk_ch1 => tx_half_clk(1),
+ fpga_rxrefclk_ch1 => clk_200_osc,
+ txdata_ch1 => tx_data(1),
+ tx_k_ch1 => tx_k(1),
+ tx_force_disp_ch1 => '0',
+ tx_disp_sel_ch1 => '0',
+ rxdata_ch1 => rx_data(1),
+ rx_k_ch1 => rx_k(1),
+ rx_disp_err_ch1 => open,
+ rx_cv_err_ch1 => rx_error(1),
+ rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+ sb_felb_ch1_c => '0',
+ sb_felb_rst_ch1_c => '0',
+ tx_pcs_rst_ch1_c => tx_pcs_rst(1),
+ tx_pwrup_ch1_c => '1',
+ rx_pcs_rst_ch1_c => rx_pcs_rst(1),
+ rx_pwrup_ch1_c => '1',
+ rx_los_low_ch1_s => rx_los_low(1),
+ lsm_status_ch1_s => lsm_status(1),
+ rx_cdr_lol_ch1_s => rx_cdr_lol(1),
+ tx_div2_mode_ch1_c => '0',
+ rx_div2_mode_ch1_c => '0',
+ -- CHANNEL2 --
+ hdinp_ch2 => SD_RXD_P_IN(2),
+ hdinn_ch2 => SD_RXD_N_IN(2),
+ hdoutp_ch2 => SD_TXD_P_OUT(2),
+ hdoutn_ch2 => SD_TXD_N_OUT(2),
+ rxiclk_ch2 => clk_200_txdata, --clk_200_i(2),
+ sci_sel_ch2 => sci_ch_i(2),
+ txiclk_ch2 => clk_200_txdata,
+ rx_full_clk_ch2 => rx_full_clk(2),
+ rx_half_clk_ch2 => rx_half_clk(2),
+ tx_full_clk_ch2 => tx_full_clk(2),
+ tx_half_clk_ch2 => tx_half_clk(2),
+ fpga_rxrefclk_ch2 => clk_200_osc,
+ txdata_ch2 => tx_data(2),
+ tx_k_ch2 => tx_k(2),
+ tx_force_disp_ch2 => '0',
+ tx_disp_sel_ch2 => '0',
+ rxdata_ch2 => rx_data(2),
+ rx_k_ch2 => rx_k(2),
+ rx_disp_err_ch2 => open,
+ rx_cv_err_ch2 => rx_error(2),
+ rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+ sb_felb_ch2_c => '0',
+ sb_felb_rst_ch2_c => '0',
+ tx_pcs_rst_ch2_c => tx_pcs_rst(2),
+ tx_pwrup_ch2_c => '1',
+ rx_pcs_rst_ch2_c => rx_pcs_rst(2),
+ rx_pwrup_ch2_c => '1',
+ rx_los_low_ch2_s => rx_los_low(2),
+ lsm_status_ch2_s => lsm_status(2),
+ rx_cdr_lol_ch2_s => rx_cdr_lol(2),
+ tx_div2_mode_ch2_c => '0',
+ rx_div2_mode_ch2_c => '0',
+ -- CHANNEL3 --
+ hdinp_ch3 => SD_RXD_P_IN(3),
+ hdinn_ch3 => SD_RXD_N_IN(3),
+ hdoutp_ch3 => SD_TXD_P_OUT(3),
+ hdoutn_ch3 => SD_TXD_N_OUT(3),
+ rxiclk_ch3 => clk_200_txdata, --clk_200_i(3),
+ sci_sel_ch3 => sci_ch_i(3),
+ txiclk_ch3 => clk_200_txdata,
+ rx_full_clk_ch3 => rx_full_clk(3),
+ rx_half_clk_ch3 => rx_half_clk(3),
+ tx_full_clk_ch3 => tx_full_clk(3),
+ tx_half_clk_ch3 => tx_half_clk(3),
+ fpga_rxrefclk_ch3 => clk_200_osc,
+ txdata_ch3 => tx_data(3),
+ tx_k_ch3 => tx_k(3),
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data(3),
+ rx_k_ch3 => rx_k(3),
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error(3),
+ rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst(3),
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst(3),
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low(3),
+ lsm_status_ch3_s => lsm_status(3),
+ rx_cdr_lol_ch3_s => rx_cdr_lol(3),
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
+ -- COMMON --
+ sci_wrdata => sci_data_in_i,
+ sci_rddata => sci_data_out_i,
+ sci_addr => sci_addr_i(5 downto 0),
+ sci_sel_quad => sci_qd_i,
+ sci_rd => sci_read_i,
+ sci_wrn => sci_write_i,
+
+ fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0),
+ tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
+ tx_pll_lol_qd_s => tx_pll_lol_quad,
+ tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
+ rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk
+ serdes_rst_qd_c => serdes_rst_down_quad
+ );
+
+-------------------------
+-- combined quad reset --
+-------------------------
+--rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
+rst_down_quad <= RESET; -- PL: 18/06/14
+--serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
+serdes_rst_down_quad <= '0'; -- PL: 23/06/14
+
+generated_logic : for i in 0 to 3 generate
+
+ SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
+
+ tx_pll_lol(i) <= tx_pll_lol_quad;
+
+ -------------------------------------------------
+ -- Reset FSM & Link states
+ -------------------------------------------------
+ THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => rst_n(i),
+ RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
+ TX_PLL_LOL_QD_S => tx_pll_lol(i),
+ RX_SERDES_RST_CH_C => rx_serdes_rst(i),
+ RX_CDR_LOL_CH_S => rx_cdr_lol(i),
+ RX_LOS_LOW_CH_S => rx_los_low(i),
+ RX_PCS_RST_CH_C => rx_pcs_rst(i),
+ WA_POSITION => wa_position_rx(i),
+ STATE_OUT => rx_fsm_state(i)
+ );
+
+ THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => rst_n(i),
+ TX_REFCLK => clk_200_txdata, --clk_200_osc,
+ TX_PLL_LOL_QD_S => tx_pll_lol(i),
+ RST_QD_C => rst_qd(i),
+ TX_PCS_RST_CH_C => tx_pcs_rst(i),
+ STATE_OUT => tx_fsm_state(i)
+ );
+
+
+ -- Master does not do bit-locking
+ wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
+
+
+ PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
+ begin
+ if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
+ if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
+ rx_allow(i) <= '1';
+ tx_allow(i) <= '1';
+ else
+ rx_allow(i) <= '0';
+ tx_allow(i) <= '1';
+ end if;
+ end if;
+ end process;
+
+ rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
+ tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
+
+
+ PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
+ begin
+ if rising_edge(clk_200_txdata) then
+ if got_link_ready_i(i) = '1' then
+ watchdog_timer(i) <= (others => '0');
+ if start_timer(i)(start_timer'left) = '0' then
+ start_timer(i) <= start_timer(i) + 1;
+-- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1;
+ end if;
+ else
+ start_timer(i) <= (others => '0');
+ if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then
+ watchdog_trigger(i) <= '1';
+ else
+ watchdog_trigger(i) <= '0';
+ end if;
+ if watchdog_trigger(i) = '0' then
+ watchdog_timer(i) <= watchdog_timer(i) + 1;
+ else
+ watchdog_timer(i) <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process;
+ -------------------------------------------------
+ -- TX Data
+ -------------------------------------------------
+ THE_TX : soda_tx_control
+ port map(
+ CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
+ CLK_100 => SYSCLK,
+ RESET_IN => rst(i), --CLEAR, PL!
+
+ TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i),
+ TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i),
+ TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i),
+ TX_READ_OUT => open, -- MED_READ_OUT(i),
+
+ TX_DATA_OUT => tx_data(i),
+ TX_K_OUT => tx_k(i),
+
+ REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
+ REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
+
+ START_RETRANSMIT_IN => start_retr_i(i), --TODO
+ START_POSITION_IN => request_retr_position_i(i), --TODO
+
+ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
+ SEND_DLM => TX_DLM(i),
+ SEND_DLM_WORD => TX_DLM_WORD(i),
+
+ SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15),
+ TX_ALLOW_IN => tx_allow(i),
+ RX_ALLOW_IN => rx_allow(i),
+ LINK_PHASE_OUT => link_phase_S(i), --PL!
+
+ DEBUG_OUT => debug_tx_control_i(i),
+ STAT_REG_OUT => stat_tx_control_i(i)
+ );
+
+ LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!
+ -------------------------------------------------
+ -- RX Data
+ -------------------------------------------------
+ THE_RX_CONTROL : rx_control
+ port map(
+ CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
+ CLK_100 => SYSCLK,
+ RESET_IN => rst(i), --CLEAR, PL!
+
+ RX_DATA_OUT => open, -- MED_DATA_OUT(i),
+ RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i),
+ RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i),
+ RX_READ_IN => '0', -- MED_READ_IN(i),
+
+ RX_DATA_IN => rx_data(i),
+ RX_K_IN => rx_k(i),
+
+ REQUEST_RETRANSMIT_OUT => request_retr_i(i),
+ REQUEST_POSITION_OUT => request_retr_position_i(i),
+
+ START_RETRANSMIT_OUT => start_retr_i(i),
+ START_POSITION_OUT => start_retr_position_i(i),
+
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+ RX_DLM => RX_DLM(i),
+ RX_DLM_WORD => RX_DLM_WORD(i),
+
+ SEND_LINK_RESET_OUT => send_link_reset_i(i),
+ MAKE_RESET_OUT => make_link_reset_i(i),
+ RX_ALLOW_IN => rx_allow(i),
+ GOT_LINK_READY => got_link_ready_i(i),
+
+ DEBUG_OUT => debug_rx_control_i(i),
+ STAT_REG_OUT => stat_rx_control_i(i)
+ );
+
+ internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
+ sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
+
+end generate;
+
+-------------------------------------------------
+-- SCI
+-------------------------------------------------
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process
+variable cnt : integer range 0 to 4 := 0;
+begin
+wait until rising_edge(SYSCLK);
+ SCI_ACK <= '0';
+ case sci_state is
+ when IDLE =>
+ sci_ch_i <= x"0";
+ sci_qd_i <= '0';
+ sci_reg_i <= '0';
+ sci_read_i <= '0';
+ sci_write_i <= '0';
+ sci_timer(0) <= sci_timer(0) + 1;
+ sci_timer(1) <= sci_timer(1) + 1;
+ sci_timer(2) <= sci_timer(2) + 1;
+ sci_timer(3) <= sci_timer(3) + 1;
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_state <= SCTRL;
+ else
+ if sci_timer(0)(sci_timer'left) = '1' then
+ sci_timer(0) <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ if sci_timer(1)(sci_timer'left) = '1' then
+ sci_timer(1) <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ if sci_timer(2)(sci_timer'left) = '1' then
+ sci_timer(2) <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ if sci_timer(3)(sci_timer'left) = '1' then
+ sci_timer(3) <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ end if;
+when SCTRL =>
+ if sci_reg_i = '1' then
+ SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+ else
+ sci_state <= SCTRL_WAIT;
+ end if;
+when SCTRL_WAIT =>
+ sci_state <= SCTRL_WAIT2;
+when SCTRL_WAIT2 =>
+ sci_state <= SCTRL_FINISH;
+when SCTRL_FINISH =>
+ SCI_DATA_OUT <= sci_data_out_i;
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+
+when GET_WA =>
+ if cnt = 4 then
+ cnt := 0;
+ sci_state <= IDLE;
+ else
+ sci_state <= GET_WA_WAIT;
+ sci_addr_i <= '0' & x"22";
+ sci_ch_i <= x"0";
+ sci_ch_i(cnt) <= '1';
+ sci_read_i <= '1';
+ end if;
+when GET_WA_WAIT =>
+ sci_state <= GET_WA_WAIT2;
+when GET_WA_WAIT2 =>
+ sci_state <= GET_WA_FINISH;
+when GET_WA_FINISH =>
+-- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+ wa_position(cnt) <= sci_data_out_i(3 downto 0);
+ sci_state <= GET_WA;
+ cnt := cnt + 1;
+end case;
+
+if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+ SCI_NACK <= '1';
+else
+ SCI_NACK <= '0';
+end if;
+
+end process;
+
+
+-- -------------------------------------------------
+-- -- Debug Registers
+-- -------------------------------------------------
+-- debug_reg(3 downto 0) <= rx_fsm_state;
+-- debug_reg(4) <= rx_k;
+-- debug_reg(5) <= rx_error;
+-- debug_reg(6) <= rx_los_low;
+-- debug_reg(7) <= rx_cdr_lol;
+--
+-- debug_reg(8) <= tx_k;
+-- debug_reg(9) <= tx_pll_lol;
+-- debug_reg(10) <= lsm_status;
+-- debug_reg(11) <= make_link_reset_i;
+-- debug_reg(15 downto 12) <= tx_fsm_state;
+-- -- debug_reg(31 downto 24) <= tx_data;
+--
+-- debug_reg(16) <= '0';
+-- debug_reg(17) <= tx_allow;
+-- debug_reg(18) <= RESET;
+-- debug_reg(19) <= CLEAR;
+-- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
+--
+-- debug_reg(35 downto 32) <= wa_position(3 downto 0);
+-- debug_reg(36) <= debug_tx_control_i(6);
+-- debug_reg(39 downto 37) <= "000";
+-- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
+
+
+ STAT_DEBUG <= (others => '0'); --debug_reg;
+
+-- generated_status : for i in 0 to 3 generate
+ -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
+ -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
+
+-- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK);
+-- STAT_OP(i)(14) <= '0';
+-- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
+-- STAT_OP(i)(12) <= '0';
+-- STAT_OP(i)(11) <= '0';
+-- STAT_OP(i)(10) <= rx_allow(i);
+-- STAT_OP(i)(9) <= tx_allow(i);
+-- STAT_OP(i)(8) <= got_link_ready_i(i);
+-- STAT_OP(i)(7) <= send_link_reset_i(i);
+-- STAT_OP(i)(6) <= make_link_reset_i(i);
+-- STAT_OP(i)(5) <= request_retr_i(i);
+-- STAT_OP(i)(4) <= start_retr_i(i);
+-- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
+-- end generate;
+
+end med_ecp3_sfp_4_sync_down_EP_arch;
\ No newline at end of file
CLK_100 => rx_half_clk, --SYSCLK,
RESET_IN => rst, --CLEAR, PL!
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
+ TX_DATA_IN => (others => '0'), --MED_DATA_IN,
+ TX_PACKET_NUMBER_IN => (others => '0'), --MED_PACKET_NUM_IN,
+ TX_WRITE_IN => '0', --MED_DATAREADY_IN,
+ TX_READ_OUT => open, --MED_READ_OUT,
TX_DATA_OUT => tx_data,
TX_K_OUT => tx_k,
CLK_100 => rx_half_clk, --SYSCLK,
RESET_IN => rst, --CLEAR, PL!
- RX_DATA_OUT => MED_DATA_OUT,
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
- RX_WRITE_OUT => MED_DATAREADY_OUT,
- RX_READ_IN => MED_READ_IN,
+ RX_DATA_OUT => open, --MED_DATA_OUT,
+ RX_PACKET_NUMBER_OUT => open, --MED_PACKET_NUM_OUT,
+ RX_WRITE_OUT => open, --MED_DATAREADY_OUT,
+ RX_READ_IN => '0', --MED_READ_IN,
RX_DATA_IN => rx_data,
RX_K_IN => rx_k,
signal CURRENT_STATE, NEXT_STATE: STATES;
signal last_packet_sent_S : t_PACKET_TYPE_SENT;
- signal expected_reply_S : t_HUB_BYTE_ARRAY; --std_logic_vector(7 downto 0);
- signal reply_data_valid_S : t_HUB_BIT_ARRAY;
- signal reply_OK_S : t_HUB_BIT_ARRAY;
--- signal recv_start_calibration_S : std_logic := '0';
- signal send_start_calibration_S : t_HUB_BIT_ARRAY;
- signal start_calibration_S : t_HUB_BIT_ARRAY;
- signal calib_data_valid_S : t_HUB_BIT_ARRAY;
- signal calibration_time_S : t_HUB_WORD_ARRAY;
- signal calib_register_s : t_HUB_LWORD_ARRAY;
- signal reply_timeout_error_S : t_HUB_BIT_ARRAY;
- signal channel_timeout_status_S : t_HUB_BIT_ARRAY;
- signal downstream_error_S : t_HUB_BIT_ARRAY;
+ signal expected_reply_S : t_HUB_BYTE_ARRAY;
+ signal reply_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal reply_OK_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal send_start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal calib_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal calibration_time_S : t_HUB_WORD_ARRAY := (others => (others => '0'));
+ signal calib_register_s : t_HUB_LWORD_ARRAY := (others => (others => '0'));
+ signal reply_timeout_error_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal channel_timeout_status_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal downstream_error_S : t_HUB_BIT_ARRAY := (others => '0');
- signal dead_channel_S : t_HUB_BIT_ARRAY;
+ signal dead_channel_S : t_HUB_BIT_ARRAY := (others => '0');
- signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY;\r
+ signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY := (others => (others => '0'));\r
\r
- signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY;
+ signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY := (others => '0');
signal TXsuper_burst_nr_S : t_HUB_LWORD_ARRAY; -- from super-burst-nr-generator
signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY;
signal TXsoda_cmd_word_S : t_HUB_LWORD_ARRAY;
CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit
CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit
CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit
+ elsif (start_calibration_S(i) = '1') then -- reset registers at start of new calibration
+ calib_register_S(i) <= (others => '0');
+ channel_timeout_status_S(i) <= '0';
+ downstream_error_S(i) <= '0';
+ CTRL_STATUS_register_S(i)(16) <= '0'; -- reset DOWNSTREAM_ERROR status-bit
+ CTRL_STATUS_register_S(i)(17) <= '0'; -- reset DOWNSTREAM_ERROR status-bit
+ CTRL_STATUS_register_S(i)(31) <= '0'; -- reset REPORT_ERROR status-bit
elsif (calib_data_valid_S(i) = '1') then -- calibration finished in time
calib_register_S(i) <= x"0000" & calibration_time_S(i);
channel_timeout_status_S(i) <= '0';
if (START_CALIBRATION='1') then
calibration_running_S <= '1';
calibration_timer_S <= (others => '0');
- VALID_OUT <= '0';
+ VALID_OUT <= '0';
CALIB_TIME_OUT <= (others => '0');
TIMEOUT_ERROR <= '0'; -- reset timeout error at start of new calibration
elsif (END_CALIBRATION='1') then
calibration_running_S <= '0';
- VALID_OUT <= '1';
+ VALID_OUT <= '1';
CALIB_TIME_OUT <= calibration_timer_S;
TIMEOUT_ERROR <= '0'; -- reset timeout error because a correct reply was received
elsif (calibration_timer_S = cCALIBRATION_TIMEOUT) then
calibration_running_S <= '0';
- VALID_OUT <= '1';
+ VALID_OUT <= '1';
CALIB_TIME_OUT <= calibration_timer_S;
TIMEOUT_ERROR <= '1'; -- set timeout error because NO correct reply was received
elsif (calibration_running_S='1') then
);
end component;
-
component med_ecp3_sfp_4_sync_down is
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); --select slave mode
);
end component;
+ component med_ecp3_sfp_4_sync_down_EP is
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ port(
+ OSC_CLK : in std_logic; -- 200 MHz reference clock
+ TX_DATACLK : in std_logic; -- 200 MHz data clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+ TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+ TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+
+ --Sync operation
+ RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
+ TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
+ TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+ LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in t_HUB_BIT; --std_logic;
+ SD_RXD_N_IN : in t_HUB_BIT; --std_logic;
+ SD_TXD_P_OUT : out t_HUB_BIT; --std_logic;
+ SD_TXD_N_OUT : out t_HUB_BIT; --std_logic;
+ SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
+ SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
+-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
+ end component;
component med_ecp3_sfp_sync_up is
generic(
);
end component;
+ component soda_only_ecp3_sfp_sync_up
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode
+ port(
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!
+ LINK_READY_OUT : out std_logic := '0'; --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0'
+ );
+ end component;
+\r
component med_ecp3_sfp_4_soda is
generic( SERDES_NUM : integer range 0 to 3 := 0;
IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
signal CURRENT_STATE, NEXT_STATE: STATES;
signal last_packet_sent_S : t_PACKET_TYPE_SENT;
- signal expected_reply_S : t_HUB_BYTE_ARRAY; --std_logic_vector(7 downto 0);
- signal reply_data_valid_S : t_HUB_BIT_ARRAY;
- signal reply_OK_S : t_HUB_BIT_ARRAY;
+ signal expected_reply_S : t_HUB_BYTE_ARRAY := (others => (others => '0'));
+ signal reply_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal reply_OK_S : t_HUB_BIT_ARRAY := (others => '0');
signal recv_start_calibration_S : std_logic := '0';
- signal send_start_calibration_S : t_HUB_BIT_ARRAY;
- signal start_calibration_S : t_HUB_BIT_ARRAY;
- signal calib_data_valid_S : t_HUB_BIT_ARRAY;
- signal calibration_time_S : t_HUB_WORD_ARRAY;
- signal calib_register_s : t_HUB_LWORD_ARRAY;
- signal reply_timeout_error_S : t_HUB_BIT_ARRAY;
- signal channel_timeout_status_S : t_HUB_BIT_ARRAY;
- signal downstream_error_S : t_HUB_BIT_ARRAY;
+ signal send_start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal calib_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal calibration_time_S : t_HUB_WORD_ARRAY := (others => (others => '0'));
+ signal calib_register_s : t_HUB_LWORD_ARRAY := (others => (others => '0'));
+ signal reply_timeout_error_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal channel_timeout_status_S : t_HUB_BIT_ARRAY := (others => '0');
+ signal downstream_error_S : t_HUB_BIT_ARRAY := (others => '0');
- signal dead_channel_S : t_HUB_BIT_ARRAY;
+ signal dead_channel_S : t_HUB_BIT_ARRAY := (others => '0');
- signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY;\r
- \r
+ signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY := (others => (others => '0'));
+
signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY;
signal TXsuper_burst_nr_S : t_HUB_LWORD_ARRAY; -- from super-burst-nr-generator
signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY;
TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT,
TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT,
TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT
- );\r
- \r
+ );
+
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
--end if;
--end if;
--end process;
- \r
- \r
- \r
+
+
+
start_calibration_S(i) <= send_start_calibration_S(i);
packet_builder : soda_packet_builder
SODACLK => SODACLK,
RESET => RESET,
--Internal Connection
- LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ?
+ LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ?
SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
START_OF_SUPERBURST => TXstart_of_superburst_S(i),
SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0),
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
-end architecture;
+end architecture;
\ No newline at end of file
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+use work.soda_components.all;
+
+entity soda_only_ecp3_sfp_sync_up is
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode
+ port(
+ OSCCLK : in std_logic; -- 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
+ RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!
+ LINK_READY_OUT : out std_logic := '0'; --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0'
+ );
+end entity;
+
+
+architecture soda_only_ecp3_sfp_sync_up_arch of soda_only_ecp3_sfp_sync_up is
+
+-- Placer Directives
+attribute HGROUP : string;
+-- for whole architecture
+attribute HGROUP of soda_only_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group";
+attribute syn_sharing : string;
+attribute syn_sharing of soda_only_ecp3_sfp_sync_up_arch : architecture is "off";
+
+
+component DCS
+-- synthesis translate_off
+generic
+ (
+DCSMODE : string :=“POS”
+);
+-- synthesis translate_on
+port (
+CLK0 :in std_logic ;
+CLK1 :in std_logic ;
+SEL :in std_logic ;
+DCSOUT :out std_logic) ;
+end component;
+
+
+--signal clk_200_i : std_logic;
+--signal clk_200_internal : std_logic;
+signal clk_200_osc : std_logic;
+signal rx_full_clk : std_logic;
+signal rx_half_clk : std_logic;
+signal tx_full_clk : std_logic;
+signal tx_half_clk : std_logic;
+
+signal tx_data : std_logic_vector(7 downto 0);
+signal tx_k : std_logic;
+signal rx_data : std_logic_vector(7 downto 0);
+signal rx_k : std_logic;
+signal rx_error : std_logic;
+
+signal rst_n : std_logic;
+signal rst : std_logic; -- PL!
+signal rx_serdes_rst : std_logic;
+signal tx_serdes_rst : std_logic;
+signal tx_pcs_rst : std_logic;
+signal rx_pcs_rst : std_logic;
+signal rst_qd : std_logic;
+signal serdes_rst_qd : std_logic;
+signal sd_los_i : std_logic; --PL!
+
+signal rx_los_low : std_logic;
+signal lsm_status : std_logic;
+signal rx_cdr_lol : std_logic;
+signal tx_pll_lol : std_logic;
+
+signal sci_ch_i : std_logic_vector(3 downto 0);
+signal sci_qd_i : std_logic;
+signal sci_reg_i : std_logic;
+signal sci_addr_i : std_logic_vector(8 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+signal sci_write_shift_i : std_logic_vector(2 downto 0);
+signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
+-- fix signal names for constraining
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_preserve of sci_ch_i : signal is true;
+attribute syn_keep of sci_ch_i : signal is true;
+attribute syn_preserve of sci_qd_i : signal is true;
+attribute syn_keep of sci_qd_i : signal is true;
+attribute syn_preserve of sci_reg_i : signal is true;
+attribute syn_keep of sci_reg_i : signal is true;
+attribute syn_preserve of sci_addr_i : signal is true;
+attribute syn_keep of sci_addr_i : signal is true;
+attribute syn_preserve of sci_data_in_i : signal is true;
+attribute syn_keep of sci_data_in_i : signal is true;
+attribute syn_preserve of sci_data_out_i : signal is true;
+attribute syn_keep of sci_data_out_i : signal is true;
+attribute syn_preserve of sci_read_i : signal is true;
+attribute syn_keep of sci_read_i : signal is true;
+attribute syn_preserve of sci_write_i : signal is true;
+attribute syn_keep of sci_write_i : signal is true;
+attribute syn_preserve of sci_write_shift_i : signal is true;
+attribute syn_keep of sci_write_shift_i : signal is true;
+attribute syn_preserve of sci_read_shift_i : signal is true;
+attribute syn_keep of sci_read_shift_i : signal is true;
+
+signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
+signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
+signal tx_allow : std_logic;
+signal rx_allow : std_logic;
+signal tx_allow_q : std_logic;
+signal rx_allow_q : std_logic;
+signal link_phase_S : std_logic; --PL!
+signal request_retr_i : std_logic;
+signal start_retr_i : std_logic;
+signal request_retr_position_i : std_logic_vector(7 downto 0);
+signal start_retr_position_i : std_logic_vector(7 downto 0);
+signal send_link_reset_i : std_logic;
+signal make_link_reset_i : std_logic;
+signal got_link_ready_i : std_logic;
+signal internal_make_link_reset_out : std_logic;
+
+attribute syn_preserve of wa_position : signal is true;
+attribute syn_keep of wa_position : signal is true;
+attribute syn_preserve of wa_position_rx : signal is true;
+attribute syn_keep of wa_position_rx : signal is true;
+
+signal stat_rx_control_i : std_logic_vector(31 downto 0);
+signal stat_tx_control_i : std_logic_vector(31 downto 0);
+signal debug_rx_control_i : std_logic_vector(31 downto 0);
+signal debug_tx_control_i : std_logic_vector(31 downto 0);
+signal rx_fsm_state : std_logic_vector(3 downto 0);
+signal tx_fsm_state : std_logic_vector(3 downto 0);
+signal debug_reg : std_logic_vector(63 downto 0);
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state : sci_ctrl;
+signal sci_timer : unsigned(12 downto 0) := (others => '0');
+signal start_timer : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger : std_logic :='0';
+
+begin
+
+clk_200_osc <= OSCCLK;
+
+RX_HALF_CLK_OUT <= rx_half_clk;
+RX_FULL_CLK_OUT <= rx_full_clk;
+TX_HALF_CLK_OUT <= tx_half_clk;
+TX_FULL_CLK_OUT <= tx_full_clk;
+RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014
+
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+
+LINK_READY_OUT <= got_link_ready_i;
+
+
+--rst_n <= not CLEAR; PL!
+rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+
+
+--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
+-- clk_200_i <= rx_full_clk;
+--end generate;
+
+--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
+-- clk_200_i <= clk_200_internal;
+--end generate;
+
+
+-------------------------------------------------
+-- Serdes
+-------------------------------------------------
+THE_SERDES : entity work.serdes_sync_upstream
+ port map(
+ hdinp_ch3 => SD_RXD_P_IN,
+ hdinn_ch3 => SD_RXD_N_IN,
+ hdoutp_ch3 => SD_TXD_P_OUT,
+ hdoutn_ch3 => SD_TXD_N_OUT,
+ txiclk_ch3 => rx_full_clk,
+ rx_full_clk_ch3 => rx_full_clk,
+ rx_half_clk_ch3 => rx_half_clk,
+ tx_full_clk_ch3 => tx_full_clk,
+ tx_half_clk_ch3 => tx_half_clk,
+ fpga_rxrefclk_ch3 => clk_200_osc,
+ txdata_ch3 => tx_data,
+ tx_k_ch3 => tx_k,
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data,
+ rx_k_ch3 => rx_k,
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error,
+ rx_serdes_rst_ch3_c => rx_serdes_rst,
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst,
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low,
+ lsm_status_ch3_s => lsm_status,
+ rx_cdr_lol_ch3_s => rx_cdr_lol,
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_qd_i,
+ SCI_SEL_ch3 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => rx_full_clk,
+ tx_serdes_rst_c => tx_serdes_rst,
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => serdes_rst_qd
+
+ );
+
+-------------------------------------------------
+-- Reset FSM & Link states
+-------------------------------------------------
+THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => rst_n,
+ RX_REFCLK => clk_200_osc, -- allways running PL!
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ RX_SERDES_RST_CH_C => rx_serdes_rst,
+ RX_CDR_LOL_CH_S => rx_cdr_lol,
+ RX_LOS_LOW_CH_S => rx_los_low,
+ RX_PCS_RST_CH_C => rx_pcs_rst,
+ WA_POSITION => wa_position_rx(3 downto 0),
+ STATE_OUT => rx_fsm_state
+ );
+
+THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => rst_n,
+ TX_REFCLK => clk_200_osc, -- allways running PL! 18-06 was clk_200_i
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ RST_QD_C => rst_qd,
+ TX_PCS_RST_CH_C => tx_pcs_rst,
+ STATE_OUT => tx_fsm_state
+ );
+
+-- Master does not do bit-locking
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
+
+
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
+PROC_ALLOW : process begin
+ wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
+ rx_allow <= '1';
+ else
+ rx_allow <= '0';
+ end if;
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
+ tx_allow <= '1';
+ else
+ tx_allow <= '0';
+ end if;
+end process;
+
+rx_allow_q <= rx_allow when rising_edge(rx_half_clk); --SYSCLK);
+tx_allow_q <= tx_allow when rising_edge(rx_half_clk); --SYSCLK);
+
+
+PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i)
+begin
+ if rising_edge(rx_full_clk) then --clk_200_osc) then
+ if got_link_ready_i = '1' then
+ watchdog_timer <= (others => '0');
+ if start_timer(start_timer'left) = '0' then
+ start_timer <= start_timer + 1;
+ end if;
+ else
+ start_timer <= (others => '0');
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
+ watchdog_trigger <= '1';
+ else
+ watchdog_trigger <= '0';
+ end if;
+ if watchdog_trigger = '0' then
+ watchdog_timer <= watchdog_timer + 1;
+ else
+ watchdog_timer <= (others => '0');
+ end if;
+ end if;
+ end if;
+end process;
+-------------------------------------------------
+-- TX Data
+-------------------------------------------------
+THE_TX : soda_tx_control
+ port map(
+ CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i,
+ CLK_100 => rx_half_clk, --SYSCLK,
+ RESET_IN => rst, --CLEAR, PL!
+
+ TX_DATA_IN => (others => '0'), --MED_DATA_IN,
+ TX_PACKET_NUMBER_IN => (others => '0'), --MED_PACKET_NUM_IN,
+ TX_WRITE_IN => '0', --MED_DATAREADY_IN,
+ TX_READ_OUT => open, --MED_READ_OUT,
+
+ TX_DATA_OUT => tx_data,
+ TX_K_OUT => tx_k,
+
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO
+
+ START_RETRANSMIT_IN => start_retr_i, --TODO
+ START_POSITION_IN => request_retr_position_i, --TODO
+
+ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,
+ SEND_DLM => TX_DLM,
+ SEND_DLM_WORD => TX_DLM_WORD,
+
+ SEND_LINK_RESET_IN => '0', --CTRL_OP(15),
+ TX_ALLOW_IN => tx_allow,
+ RX_ALLOW_IN => rx_allow,
+ LINK_PHASE_OUT => link_phase_S, --PL!
+
+ DEBUG_OUT => debug_tx_control_i,
+ STAT_REG_OUT => stat_tx_control_i
+);
+
+LINK_PHASE_OUT <= link_phase_S; --PL!
+-------------------------------------------------
+-- RX Data
+-------------------------------------------------
+THE_RX_CONTROL : rx_control
+ port map(
+ CLK_200 => rx_full_clk, --clk_200_i, PL!
+ CLK_100 => rx_half_clk, --SYSCLK,
+ RESET_IN => rst, --CLEAR, PL!
+
+ RX_DATA_OUT => open, --MED_DATA_OUT,
+ RX_PACKET_NUMBER_OUT => open, --MED_PACKET_NUM_OUT,
+ RX_WRITE_OUT => open, --MED_DATAREADY_OUT,
+ RX_READ_IN => '0', --MED_READ_IN,
+
+ RX_DATA_IN => rx_data,
+ RX_K_IN => rx_k,
+
+ REQUEST_RETRANSMIT_OUT => request_retr_i,
+ REQUEST_POSITION_OUT => request_retr_position_i,
+
+ START_RETRANSMIT_OUT => start_retr_i,
+ START_POSITION_OUT => start_retr_position_i,
+
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+ RX_DLM => RX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+
+ SEND_LINK_RESET_OUT => send_link_reset_i,
+ MAKE_RESET_OUT => make_link_reset_i,
+ RX_ALLOW_IN => rx_allow,
+ GOT_LINK_READY => got_link_ready_i,
+
+ DEBUG_OUT => debug_rx_control_i,
+ STAT_REG_OUT => stat_rx_control_i
+ );
+
+
+
+-------------------------------------------------
+-- SCI
+-------------------------------------------------
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process
+ variable cnt : integer range 0 to 4 := 0;
+begin
+ wait until rising_edge(rx_half_clk); --SYSCLK);
+ SCI_ACK <= '0';
+ case sci_state is
+ when IDLE =>
+ sci_ch_i <= x"0";
+ sci_qd_i <= '0';
+ sci_reg_i <= '0';
+ sci_read_i <= '0';
+ sci_write_i <= '0';
+ sci_timer <= sci_timer + 1;
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_state <= SCTRL;
+ elsif sci_timer(sci_timer'left) = '1' then
+ sci_timer <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ when SCTRL =>
+ if sci_reg_i = '1' then
+ SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+ else
+ sci_state <= SCTRL_WAIT;
+ end if;
+ when SCTRL_WAIT =>
+ sci_state <= SCTRL_WAIT2;
+ when SCTRL_WAIT2 =>
+ sci_state <= SCTRL_FINISH;
+ when SCTRL_FINISH =>
+ SCI_DATA_OUT <= sci_data_out_i;
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+
+ when GET_WA =>
+ if cnt = 4 then
+ cnt := 0;
+ sci_state <= IDLE;
+ else
+ sci_state <= GET_WA_WAIT;
+ sci_addr_i <= '0' & x"22";
+ sci_ch_i <= x"0";
+ sci_ch_i(cnt) <= '1';
+ sci_read_i <= '1';
+ end if;
+ when GET_WA_WAIT =>
+ sci_state <= GET_WA_WAIT2;
+ when GET_WA_WAIT2 =>
+ sci_state <= GET_WA_FINISH;
+ when GET_WA_FINISH =>
+ wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+ sci_state <= GET_WA;
+ cnt := cnt + 1;
+ end case;
+
+ if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+ SCI_NACK <= '1';
+ else
+ SCI_NACK <= '0';
+ end if;
+
+end process;
+
+
+-------------------------------------------------
+-- Debug Registers
+-------------------------------------------------
+debug_reg(3 downto 0) <= rx_fsm_state;
+debug_reg(4) <= rx_k;
+debug_reg(5) <= rx_error;
+debug_reg(6) <= rx_los_low;
+debug_reg(7) <= rx_cdr_lol;
+
+debug_reg(8) <= tx_k;
+debug_reg(9) <= tx_pll_lol;
+debug_reg(10) <= lsm_status;
+debug_reg(11) <= make_link_reset_i;
+debug_reg(15 downto 12) <= tx_fsm_state;
+-- debug_reg(31 downto 24) <= tx_data;
+
+debug_reg(16) <= '0';
+debug_reg(17) <= tx_allow;
+debug_reg(18) <= RESET;
+debug_reg(19) <= CLEAR;
+debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
+
+debug_reg(35 downto 32) <= wa_position(3 downto 0);
+debug_reg(36) <= debug_tx_control_i(6);
+debug_reg(39 downto 37) <= "000";
+debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
+
+
+--STAT_DEBUG <= debug_reg;
+
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
+
+ --STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
+ --STAT_OP(14) <= '0';
+ --STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
+ --STAT_OP(12) <= tx_pll_lol; --'0';
+ --STAT_OP(11) <= rx_cdr_lol; --'0';
+ --STAT_OP(10) <= rx_allow;
+ --STAT_OP(9) <= tx_allow;
+ --STAT_OP(8 downto 4) <= (others => '0');
+ --STAT_OP(8) <= got_link_ready_i;
+ --STAT_OP(7) <= send_link_reset_i;
+ --STAT_OP(6) <= make_link_reset_i;
+ --STAT_OP(5) <= request_retr_i;
+ --STAT_OP(4) <= start_retr_i;
+ --STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
+end soda_only_ecp3_sfp_sync_up_arch;
\ No newline at end of file
);\r
end soda_reply_pkt_builder;\r
\r
-architecture Behavioral of soda_reply_pkt_builder is\r
+architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is\r
type packet_state_type is ( c_IDLE, c_ERROR,
c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
\r
\r
\r
-end architecture;
\ No newline at end of file
+end soda_reply_pkt_builder_arch;
\ No newline at end of file
signal clear_i : std_logic;
signal reset_i : std_logic;
signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
+
signal clk_100_osc : std_logic;
signal clk_200_osc : std_logic;
signal time_counter : unsigned(31 downto 0);
--SODA
signal SOB_S : std_logic := '0';
-- fix signal names for constraining
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
attribute syn_preserve of rx_full_clk : signal is true;
attribute syn_keep of rx_full_clk : signal is true;
attribute syn_preserve of rx_half_clk : signal is true;
DEBUG_OUT => open
);
-
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
DEBUG_LVL1_HANDLER_OUT => open
);
-
-
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
port map(
- CLK_IN => clk_100_osc,
+ CLK_IN => clk_100_osc,
RESET_IN => reset_i,
BUS_ADDR_IN => spimem_addr,
---------------------------------------------------------------------------------------------------------------------------------------------------------
-- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
---------------------------------------------------------------------------------------------------------------------------------------------------------
--- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16),
RX_HALF_CLK_OUT(0) => rx_half_clk(0),
RX_HALF_CLK_OUT(1) => rx_half_clk(1),
RX_HALF_CLK_OUT(2) => rx_half_clk(2),
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.med_sync_define.all;
+use work.version.all;
+
+entity trb3_periph_EP_hub is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+ USE_125_MHZ : integer := c_NO;
+ CLOCK_FREQUENCY : integer := 100;
+ NUM_TRB_INTERFACES : integer := 1
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --serdes I/O - connect as you like, no real use
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+ --SFP_MOD1 : inout std_logic_vector(6 downto 1);
+ --SFP_MOD2 : inout std_logic_vector(6 downto 1);
+ --SFP_RATESEL : out std_logic_vector(6 downto 1);
+ --SFP_TXFAULT : in std_logic_vector(6 downto 1);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+ attribute syn_useioff of TEST_LINE : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_EP_hub_arch of trb3_periph_EP_hub is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
+
+ --Clock / Reset
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal downlink_clear : std_logic;
+ signal downlink_reset : std_logic;
+ signal GSR_N : std_logic;
+ signal clk_100_osc : std_logic;
+ signal clk_200_osc : std_logic;
+ signal time_counter : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
+-- signal med_ctrl_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
+
+ --Slow Control channel
+-- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+-- signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+-- SCI for the uplink
+ signal sci1_ack : std_logic;
+ signal sci1_nack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+-- SCI for the downlink
+ signal sci2_ack : std_logic;
+ signal sci2_nack : std_logic;
+ signal sci2_write : std_logic;
+ signal sci2_read : std_logic;
+ signal sci2_data_in : std_logic_vector(7 downto 0);
+ signal sci2_data_out : std_logic_vector(7 downto 0);
+ signal sci2_addr : std_logic_vector(8 downto 0);
+
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
+
+ --SODA
+ signal soda_ack : std_logic;
+ signal soda_nack : std_logic;
+ signal soda_write : std_logic;
+ signal soda_read : std_logic;
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_leds : std_logic_vector(3 downto 0);
+
+ --SODA uplink
+ signal rxup_half_clk : std_logic;
+ signal rxup_full_clk : std_logic;
+ signal txup_half_clk : std_logic;
+ signal txup_full_clk : std_logic;
+
+ signal rx_cdr_lol_S : std_logic;
+ signal txup_dlm_i : std_logic;
+ signal rxup_dlm_i : std_logic;
+ signal txup_dlm_word : std_logic_vector(7 downto 0);
+ signal rxup_dlm_word : std_logic_vector(7 downto 0);
+ signal txup_dlm_preview_S : std_logic; --PL!
+ signal uplink_phase_S : std_logic; --PL!
+ signal uplink_ready_S : std_logic; --PL!
+
+ --SODA downlink
+ signal rxdn_half_clk : t_HUB_BIT;
+ signal rxdn_full_clk : t_HUB_BIT;
+ signal txdn_half_clk : t_HUB_BIT;
+ signal txdn_full_clk : t_HUB_BIT;
+
+ signal txdn_dlm_i : t_HUB_BIT;
+ signal rxdn_dlm_i : t_HUB_BIT;
+ signal txdn_dlm_word : t_HUB_BYTE;
+ signal rxdn_dlm_word : t_HUB_BYTE;
+ signal txdn_dlm_preview_S : t_HUB_BIT; --PL!
+ signal dnlink_phase_S : t_HUB_BIT; --PL!
+
+ signal link_debug_in_S : std_logic_vector(31 downto 0);
+
+ --SODA
+ signal SOB_S : std_logic := '0';
+ -- fix signal names for constraining
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_preserve of clk_100_osc : signal is true;
+ attribute syn_keep of clk_100_osc : signal is true;
+ attribute syn_preserve of clk_200_osc : signal is true;
+ attribute syn_keep of clk_200_osc : signal is true;
+
+ attribute syn_preserve of rxup_full_clk : signal is true;
+ attribute syn_keep of rxup_full_clk : signal is true;
+ attribute syn_preserve of rxup_half_clk : signal is true;
+ attribute syn_keep of rxup_half_clk : signal is true;
+ attribute syn_preserve of txup_full_clk : signal is true;
+ attribute syn_keep of txup_full_clk : signal is true;
+ attribute syn_preserve of txup_half_clk : signal is true;
+ attribute syn_keep of txup_half_clk : signal is true;
+ attribute syn_preserve of txup_dlm_i : signal is true;
+ attribute syn_keep of txup_dlm_i : signal is true;
+ attribute syn_preserve of rxup_dlm_i : signal is true;
+ attribute syn_keep of rxup_dlm_i : signal is true;
+
+ attribute syn_preserve of rxdn_full_clk : signal is true;
+ attribute syn_keep of rxdn_full_clk : signal is true;
+ attribute syn_preserve of rxdn_half_clk : signal is true;
+ attribute syn_keep of rxdn_half_clk : signal is true;
+ attribute syn_preserve of txdn_full_clk : signal is true;
+ attribute syn_keep of txdn_full_clk : signal is true;
+ attribute syn_preserve of txdn_half_clk : signal is true;
+ attribute syn_keep of txdn_half_clk : signal is true;
+ attribute syn_preserve of txdn_dlm_i : signal is true;
+ attribute syn_keep of txdn_dlm_i : signal is true;
+ attribute syn_preserve of rxdn_dlm_i : signal is true;
+ attribute syn_keep of rxdn_dlm_i : signal is true;
+
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+--gen_200_PLL : if USE_125_MHZ = c_NO generate
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_osc,
+ CLKOK => clk_200_osc,
+ LOCK => pll_lock
+ );
+--end generate;
+
+--gen_125 : if USE_125_MHZ = c_YES generate
+-- clk_100_osc <= CLK_GPLL_LEFT;
+-- clk_200_osc <= CLK_GPLL_LEFT;
+--end generate;
+
+
+
+---------------------------------------------------------------------------
+-- The synchronous interface for Soda and trb_endpoint
+---------------------------------------------------------------------------
+
+THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ OSCCLK => clk_200_osc,
+ SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection for TrbNet data -> not used a.t.m.
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ RX_HALF_CLK_OUT => rxup_half_clk,
+ RX_FULL_CLK_OUT => rxup_full_clk,
+ TX_HALF_CLK_OUT => txup_half_clk,
+ TX_FULL_CLK_OUT => txup_full_clk,
+ RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014
+
+ RX_DLM => rxup_dlm_i,
+ RX_DLM_WORD => rxup_dlm_word,
+ TX_DLM => txup_dlm_i,
+ TX_DLM_WORD => txup_dlm_word,
+ TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!
+ LINK_PHASE_OUT => uplink_phase_S, --PL!
+ LINK_READY_OUT => uplink_ready_S, --PL!
+ --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
+ SD_RXD_P_IN => SERDES_ADDON_RX(4),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0
+ SD_LOS_IN => SFP_LOS(3),
+ SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ SCI_NACK => sci1_nack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+\r
+
+ SFP_TXDIS <= sfp_txdis_S;
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"9100b000",
+ REGIO_INIT_ADDRESS => x"f359",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 9, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 256,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 256
+ )
+ port map(
+ CLK => clk_100_osc,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out(0),
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
+ MED_READ_IN => med_read_in(0),
+ MED_DATAREADY_IN => med_dataready_in(0),
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out(0),
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => '0',
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => open,
+ LVL1_VALID_TIMING_TRG_OUT => open,
+ LVL1_VALID_NOTIMING_TRG_OUT => open,
+ LVL1_INVALID_TRG_OUT => open,
+
+ LVL1_TRG_TYPE_OUT => open,
+ LVL1_TRG_NUMBER_OUT => open,
+ LVL1_TRG_CODE_OUT => open,
+ LVL1_TRG_INFORMATION_OUT => open,
+ LVL1_INT_TRG_NUMBER_OUT => open,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => open,
+ TRG_TIMEOUT_DETECTED_OUT => open,
+ TRG_SPURIOUS_TRG_OUT => open,
+ TRG_MISSING_TMG_TRG_OUT => open,
+ TRG_SPIKE_DETECTED_OUT => open,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => '1',
+ FEE_TRG_STATUSBITS_IN => (others => '0'),
+ FEE_DATA_IN => (others => '0'),
+ FEE_DATA_WRITE_IN(0) => '0',
+ FEE_DATA_FINISHED_IN(0) => '1',
+ FEE_DATA_ALMOST_FULL_OUT(0) => open,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
+ )
+ port map(
+ CLK => clk_100_osc,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(1) => sci1_read,
+ BUS_READ_ENABLE_OUT(2) => sci2_read,
+ BUS_READ_ENABLE_OUT(3) => soda_read,
+
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,
+ BUS_WRITE_ENABLE_OUT(2) => sci2_write,
+ BUS_WRITE_ENABLE_OUT(3) => soda_write,
+
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
+
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
+ BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
+
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
+
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_DATAREADY_IN(1) => sci1_ack,
+ BUS_DATAREADY_IN(2) => sci2_ack,
+ BUS_DATAREADY_IN(3) => soda_ack,
+
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => sci1_ack,
+ BUS_WRITE_ACK_IN(2) => sci2_ack,
+ BUS_WRITE_ACK_IN(3) => soda_ack,
+
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
+ port map(
+ CLK_IN => clk_100_osc,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+
+---------------------------------------------------------------------------
+-- The synchronous quad-downlink interface for Soda
+---------------------------------------------------------------------------
+
+ THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down_EP
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ IS_SYNC_SLAVE => c_NO
+ )
+ port map(
+ OSC_CLK => clk_200_osc,
+ TX_DATACLK => rxup_full_clk,
+ SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
+ RESET => downlink_reset,
+ CLEAR => downlink_clear,
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------
+ RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),
+ RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),
+ RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),
+ RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),
+
+ RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration
+ RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration
+
+ TX_HALF_CLK_OUT(0) => txdn_half_clk(0),
+ TX_HALF_CLK_OUT(1) => txdn_half_clk(1),
+ TX_HALF_CLK_OUT(2) => txdn_half_clk(2),
+ TX_HALF_CLK_OUT(3) => txdn_half_clk(3),
+
+ TX_FULL_CLK_OUT(0) => txdn_full_clk(0),
+ TX_FULL_CLK_OUT(1) => txdn_full_clk(1),
+ TX_FULL_CLK_OUT(2) => txdn_full_clk(2),
+ TX_FULL_CLK_OUT(3) => txdn_full_clk(3),
+
+ RX_DLM(0) => rxdn_dlm_i(0),
+ RX_DLM(1) => rxdn_dlm_i(1),
+ RX_DLM(2) => rxdn_dlm_i(2),
+ RX_DLM(3) => rxdn_dlm_i(3),
+
+ RX_DLM_WORD(0) => rxdn_dlm_word(0),
+ RX_DLM_WORD(1) => rxdn_dlm_word(1),
+ RX_DLM_WORD(2) => rxdn_dlm_word(2),
+ RX_DLM_WORD(3) => rxdn_dlm_word(3),
+
+ TX_DLM(0) => txdn_dlm_i(0),
+ TX_DLM(1) => txdn_dlm_i(1),
+ TX_DLM(2) => txdn_dlm_i(2),
+ TX_DLM(3) => txdn_dlm_i(3),
+
+ TX_DLM_WORD(0) => txdn_dlm_word(0),
+ TX_DLM_WORD(1) => txdn_dlm_word(1),
+ TX_DLM_WORD(2) => txdn_dlm_word(2),
+ TX_DLM_WORD(3) => txdn_dlm_word(3),
+
+ TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL!
+ TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL!
+ TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL!
+ TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL!
+
+ LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL!
+ LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL!
+ LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL!
+ LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
+ SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
+ SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
+ SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
+ SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
+ SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
+ SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
+ SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
+ SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
+ SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
+ SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
+ SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
+ SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
+ SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
+ SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
+ SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
+ SD_REFCLK_P_IN => (others => '0'),
+ SD_REFCLK_N_IN => ('0','0','0','0'),
+ SD_PRSNT_N_IN(0) => SFP_MOD0(1),
+ SD_PRSNT_N_IN(1) => SFP_MOD0(6),
+ SD_PRSNT_N_IN(2) => SFP_MOD0(2),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(4),
+ SD_LOS_IN(0) => SFP_LOS(1),
+ SD_LOS_IN(1) => SFP_LOS(6),
+ SD_LOS_IN(2) => SFP_LOS(2),
+ SD_LOS_IN(3) => SFP_LOS(4),
+ SD_TXDIS_OUT(0) => sfp_txdis_S(1),
+ SD_TXDIS_OUT(1) => sfp_txdis_S(6),
+ SD_TXDIS_OUT(2) => sfp_txdis_S(2),
+ SD_TXDIS_OUT(3) => sfp_txdis_S(4),
+
+ SCI_DATA_IN => sci2_data_in,
+ SCI_DATA_OUT => sci2_data_out,
+ SCI_ADDR => sci2_addr,
+ SCI_READ => sci2_read,
+ SCI_WRITE => sci2_write,
+ SCI_ACK => sci2_ack,
+ SCI_NACK => sci2_nack,
+
+ --Status and control port
+-- STAT_OP(0) => med_stat_op(15 downto 0), --med_stat_op(1*16+15 downto 1*16),
+-- CTRL_OP(0) => med_ctrl_op(15 downto 0), --med_ctrl_op(0*16+15 downto 0*16),
+
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+
+ SFP_TXDIS <= sfp_txdis_S;
+-- SFP_TXDIS(1) <= sfp_txdis_S(1);
+
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
+
+THE_SOB_SOURCE : soda_start_of_burst_faker
+ generic map(
+ CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
+ BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
+ )
+ port map(
+ SYSCLK => clk_100_osc,
+ RESET => reset_i,
+ SODA_BURST_PULSE_OUT => SOB_S
+ );
+
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
+
+ A_SODA_HUB : soda_hub
+ port map(
+ SYSCLK => rxup_half_clk,
+ SODACLK => rxup_full_clk,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+
+ -- SINGLE DUBPLEX UP-LINK TO THE TOP
+ RXUP_DLM_WORD_IN => rxup_dlm_word,
+ RXUP_DLM_IN => rxup_dlm_i,
+ TXUP_DLM_OUT => txup_dlm_i,
+ TXUP_DLM_WORD_OUT => txup_dlm_word,
+ TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S,
+ UPLINK_PHASE_IN => uplink_phase_S,
+ -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
+ RXDN_DLM_WORD_IN => rxdn_dlm_word,
+ RXDN_DLM_IN => rxdn_dlm_i,
+ TXDN_DLM_OUT => txdn_dlm_i,
+ TXDN_DLM_WORD_OUT => txdn_dlm_word,
+ TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S,
+ DNLINK_PHASE_IN => dnlink_phase_S,
+
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read,
+ SODA_WRITE_IN => soda_write,
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => soda_leds,
+ LINK_DEBUG_IN => link_debug_in_S
+ );
+
+
+ downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';
+ downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
+ LED_GREEN <= med_stat_op(12); --tx_pll_lol
+ LED_RED <= med_stat_op(11); --rx_cdr_lol
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+-- TEST_LINE(15 downto 0) <= (others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_100_osc);
+ time_counter <= time_counter + 1;
+ end process;
+
+
+end trb3_periph_EP_hub_arch;
\ No newline at end of file
constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
--Clock / Reset
--- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_sys_internal : std_logic;
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
-- signal clk_raw_internal : std_logic;
signal clk_200_osc : std_logic;
+ signal clk_100_osc : std_logic;
signal rx_full_clk : std_logic;
signal rx_half_clk : std_logic;
signal tx_full_clk : std_logic;
signal soda_counter_i : unsigned(3 downto 0);
attribute syn_keep of soda_counter_i : signal is true;
-- fix signal names for constraining
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
attribute syn_preserve of rx_full_clk : signal is true;
attribute syn_keep of rx_full_clk : signal is true;
attribute syn_preserve of rx_half_clk : signal is true;
attribute syn_keep of rx_half_clk : signal is true;
- attribute syn_preserve of clk_sys_internal : signal is true;
- attribute syn_keep of clk_sys_internal : signal is true;
+ attribute syn_preserve of clk_100_osc : signal is true;
+ attribute syn_keep of clk_100_osc : signal is true;
attribute syn_preserve of clk_200_osc : signal is true;
attribute syn_keep of clk_200_osc : signal is true;
attribute syn_preserve of tx_dlm_i : signal is true;
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => rx_half_clk, --clk_sys_internal, -- PLL/DLL remastered clock
+ SYSCLK_IN => rx_half_clk, --clk_100_osc, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
DEBUG_OUT => open
);
--- process(clk_sys_internal)
+-- process(clk_100_osc)
-- begin
--- if rising_edge(clk_sys_internal) then
+-- if rising_edge(clk_100_osc) then
-- general_reset_i <= not SFP_LOS(1);
-- end if;
-- end process;
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_sys_internal,
+ CLKOP => clk_100_osc,
CLKOK => clk_200_osc, --clk_raw_internal,
LOCK => pll_lock
);
end generate;
--gen_125 : if USE_125_MHZ = c_YES generate
--- clk_sys_internal <= CLK_GPLL_LEFT;
+-- clk_100_osc <= CLK_GPLL_LEFT;
-- clk_raw_internal <= CLK_GPLL_LEFT;
--end generate;
--gen_sync_clocks : if SYNC_MODE = c_YES generate
--- clk_sys_i <= clk_sys_internal;
+-- clk_sys_i <= clk_100_osc;
-- clk_soda_i <= soda_rx_clock_full;
-- clk_200_i <= soda_rx_clock_full;
--end generate;
--gen_local_clocks : if SYNC_MODE = c_NO generate
--- clk_sys_i <= clk_sys_internal;
+-- clk_sys_i <= clk_100_osc;
-- clk_soda_i <= clk_raw_internal;
-- clk_200_i <= clk_raw_internal;
--end generate;
HEADER_BUFFER_FULL_THRESH => 256
)
port map(
- CLK => rx_half_clk, --clk_sys_internal,
+ CLK => rx_half_clk, --clk_100_osc,
RESET => reset_i,
CLK_EN => '1',
MED_DATAREADY_OUT => med_dataready_out(0),
PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
)
port map(
- CLK => rx_half_clk, --clk_sys_internal,
+ CLK => rx_half_clk, --clk_100_osc,
RESET => reset_i,
DAT_ADDR_IN => regio_addr_out,
THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
port map(
- CLK_IN => rx_half_clk, --clk_sys_internal,
+ CLK_IN => rx_half_clk, --clk_100_osc,
RESET_IN => reset_i,
BUS_ADDR_IN => spimem_addr,
)
port map(
OSCCLK => clk_200_osc, --clk_raw_internal,
- SYSCLK => clk_sys_internal,
+ SYSCLK => clk_100_osc,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection for TrbNet data -> not used a.t.m.
A_SODA_CLIENT : soda_client
port map(
- SYSCLK => rx_half_clk, --clk_sys_internal,
+ SYSCLK => rx_half_clk, --clk_100_osc,
SODACLK => rx_full_clk,
RESET => reset_i,
CLEAR => clear_i,
LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
LED_GREEN <= med_stat_op(12); --tx_pll_lol
LED_RED <= med_stat_op(11); --rx_cdr_lol
--- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+-- LED_ORANGE <= not reset_i when rising_edge(clk_100_osc);
-- LED_YELLOW <= soda_leds(0); --'1';
-- LED_GREEN <= not med_stat_op(9);
-- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
- clock_counter_proc : process(clk_sys_internal)
+ clock_counter_proc : process(clk_100_osc)
begin
- if rising_edge(clk_sys_internal) then
+ if rising_edge(clk_100_osc) then
time_counter <= time_counter + 1;
end if;
end process;
<Option name="HDL type" value="VHDL"/>
</Options>
<Implementation title="soda_client" dir="soda_client" description="soda_client" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+ <Options top="trb3_periph_sodaclient"/>
<Source name="code/version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Options/>
</Source>
<Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodaclient"/>
+ <Options/>
</Source>
<Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
<Options/>
rvl_alias "clk_raw_internal" "clk_raw_internal";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140915.bit</File>
- <FileTime>09/15/14 16:30:11</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141015.bit</File>
+ <FileTime>10/15/14 15:08:51</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140915.bit</File>
- <FileTime>09/15/14 16:30:11</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141015.bit</File>
+ <FileTime>10/15/14 15:08:51</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
jspc29 / soda.git / commitdiff