add new MDC addresses

diff --git a/networkaddresses.tex b/networkaddresses.tex
index cddf905c30d5202b1ce49cee8c0788cd36441976..b956843ca2351cccac5774357b0c67edef749748 100755 (executable)
--- a/networkaddresses.tex
+++ b/networkaddresses.tex
@@ -2,43 +2,44 @@
 %\url{http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NetworkAddresses}
 
 \subsection{Addressing scheme}
-On boards with two or more FPGAs each FPGA gets its own address. The FPGA providing the uplink gets the lowest address (usually with 0 as 4th digit), the other FPGAs are numbered in the order they are placed on the board.
-
-
 
 \begin{table}[hb]
 \begin{center}
 \begin{tabularx}{\textwidth}{l|l|X}
 \textbf{Address(es)} & \textbf{Board(s)} & \textbf{Description} \\
-0000 - 00FF & CTS & \\
-1000 - 17FF & MDC Concentrator & 2nd digit: inner(0) / outer(1) MDC; 3rd digit: sector (0-5), 4th
-digit FPGA (0-4) \\
+0000 - 00FF & CTS & CTS, Triggerbox\\
+1000 - 17FF & MDC Conc. & 2nd digit: inner(0) / outer(1) MDC; 3rd digit: sector (0-5); 4th digit FPGA (0-4) \\
 2000 - 2FFF & MDC OEP & 2nd digit: MDC layer (0-3); 3rd digit: sector (0-5); 4th digit MBO (0-F) \\
-5000 - 50FF & StartTRB3 & Start/Veto/iTOF. 3rd digit: 0: Start, 1: Veto, 4th digit: FPGA (0-5)\\ 
-5555        & SEB & Dummy Address used in headers generated by SubEventBuilders \\
+2000 - 2FFF & MDC TDC & 2nd digit: sector (0-5 inner, a-f outer); 3rd digit: MBO (0-f); 4th digit: TDC (0-2 MDC 1/3, a-c MDC 2/4)\\
+5000 - 500F & Start & 4th digit: FPGA (0-7)\\ 
+5010 - 501F & Hodo & 4th digit: FPGA (0-2)\\ 
+5555        & SEB & Dummy Address used in SubEvents \\
 5800 - 58FF & RPC & 3rd digit sector (0..5), 4th digit TDC (0..8) \\
 5C00 - 5CFF & TOF & 3rd digit sector (0..6), 4th digit TDC (0..3) \\ 
 5D00 - 5D0F & iTOF & 4th digit TDC (0..5) \\
-6000 - 60FF & Ecal & Ecal read-out. 3rd digit: Sector, 4th digit: Readout Board (0-6)\\
-6400 - 64FF & STT &  3rd digit detector part (0-7), 4th digit FPGA (0-6) \\
+6000 - 60FF & Ecal & 3rd digit: Sector, 4th digit: TDC (0-6)\\
+6400 - 64FF & STT &  3rd digit detector part (0-7); 4th digit TDC (0-6) \\
 6700 - 67FF & Wall & 3rd digit board (0..2), 4th digit TDC (0..3) \\
-6800 - 68FF & f-RPC &  3rd digit board number (0-1), 4th digit FPGA (0-3)\\
+6800 - 68FF & f-RPC &  3rd digit board (0-1), 4th digit TDC (0-3)\\
 7000 - 7FFF & RICH & DiRich modules. 2nd/3rd digit backplane number, 4th digit: DiRich (0-11)\\
 8000 - 80FF & Central Hub & central hub\\
-8100 - 81FF & MDC Hub & Hub for inner MDC (3rd digit 0) or outer MDC (1)\\
-83C0 - 83DF & RICH Hubs & Hubs for old RICH, 4th digit: hub number (0..13)\\
-84C0 - 84CF & RPC Hubs & Hubs for RPC, 4th digit: sector (0..5) \\
-86C0 - 86CF & TOF Hub & Hubs (central FPGA TRB3), 4th digit: sector(0..6)\\
+8100 - 81FF & MDC Hub & 3rd digit inner (0) or outer MDC (1)\\
+83C0 - 83DF & RICH Hubs & 4th digit: hub number (0..13)\\
+84C0 - 84CF & RPC Hubs & 4th digit: sector (0..5) \\
+8500 - 85FF & MDC Hubs & 3rd digit: sector (0..5 MDC1/2, 6..b 3/4); 4th digit: board\\
+86C0 - 86CF & TOF Hub & 4th digit: sector(0..6)\\
 8700 - 870F & Wall Hub & 4th digit: board(0..2)\\
 8800 - 88FF & Central Hub & Central Hubs with GbE  \\
-8880 - 88BF & Start Hub & Hubs for timing detectors, 8880: Start, 8890 Veto\\
-8900 - 89FF & Pion Tracker Hub & 3rd digit: station\\
+8880 - 888F & Start Hub & \\
+8890 - 889F & Hodo Hub & \\
+8900 - 89FF & Pion Hub & 3rd digit: station\\
 8A00 - 8AFF & Ecal Hubs& 4th digit: pseudo-sector\\
-8B00 - 8BFF & STT Hubs & 3rd digit board number (0-9)\\
+8B00 - 8BFF & STT Hubs & 3rd digit: board number (0-9)\\
 8C00 - 8CFF & f-RPC Hubs & 3rd digit board number (0-1)\\
-8D00 - 8D00 & iTOF & innerTOF \\
-F000 - FDFF & Test Setups & \\
-FE00 - FFFF & Broadcasts & Broadcast addresses
+8D00 - 8D00 & iTOF & \\
+8E00 - 8FFF & MDC OEP & (upgrade) 2nd digit: inner (e)/outer (f); 3rd digit: chamber (0..5 MDC1/3, 6..b MDC2/4); 4th digit: MBO\\
+F000 - FCFF & Test Setups & \\
+FD00 - FFFF & Broadcasts & Broadcast addresses
 \end{tabularx}
 \caption{Network Addresses}
 \label{networkaddresses}