preparation and inclusion for calibration on data path to CRI

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index 8c18a31b82d78b84ccc0796c0ff2cc88afcad58b..1c3f82a657aceadcf54e6f8286f205bf825e9222 100644 (file)
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -225,6 +225,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
 add_file -vhdl -lib work "../../cri/src/cri_data_sender.vhd"
 add_file -vhdl -lib work "../../cri/src/mbs_generator_cbmrich.vhd"
+add_file -vhdl -lib work "../../cri/src/cri_cbm_rich_calib.vhd"
 
 add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd"
 add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd"

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index 3710d98425fd9b6fb73f1c00310b6db38756b64a..0c2cea069bb769c9eaebae940c85bde3d383fd12 100644 (file)
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -116,8 +116,8 @@ architecture arch of combiner is
   signal int2med           : int2med_array_t(0 to INTERFACE_NUM); -- 1 more due to uplink
   signal med_stat_debug    : std_logic_vector (1*64-1  downto 0);
   
-  signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx,  bustdc_rx ,bustdccal_rx, bus_mbs_rx, bus_mbs_gen_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx                    : CTRLBUS_RX;
-  signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx  , bustdc_tx, bustdccal_tx, bus_mbs_tx, bus_mbs_gen_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx      : CTRLBUS_TX;
+  signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx,  bustdc_rx ,bustdccal_rx, bus_mbs_rx, bus_mbs_gen_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX;
+  signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx  , bustdc_tx, bustdccal_tx, bus_mbs_tx, bus_mbs_gen_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX;
   
   signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
   signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
@@ -195,7 +195,6 @@ architecture arch of combiner is
   
   signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1);
   signal cts_rdo_rx                : READOUT_RX;
-  signal cts_rdo_additional_TDCcal : READOUT_TX;
 
   signal cts_addon_triggers_in       : std_logic_vector(ADDON_LINE_COUNT-1 downto 0);
 --   signal cts_addon_activity_i,
@@ -758,6 +757,9 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
     BUS_DBG_RX               => busCriDatadbgReg_rx,
     BUS_DBG_TX               => busCriDatadbgReg_tx,    
     
+    BUS_CALIBRATON_RX        => bustdccal_rx,
+    BUS_CALIBRATON_TX        => bustdccal_tx, 
+    
     TIMER_TICKS_IN(0)        => timer.tick_us,
     TIMER_TICKS_IN(1)        => timer.tick_ms
   );
@@ -942,10 +944,10 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
       PORT_NUMBER      => 14,
-      PORT_ADDRESSES   => (0 => x"d000", 1 => x"d300", 2 => x"b000",  3 => x"b200",  4 => x"b400",  5 => x"b600", 6 => x"c000",
-                           7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e100", 12 => x"e400", 13 => x"e410", others => x"0000"),
-      PORT_ADDR_MASK   => (0 => 12,      1 => 1,       2 => 9,        3 => 9,        4 => 9,        5 => 9,       6  => 12,
-                           7 =>  4,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 4,       13 => 2,  others => 0),
+      PORT_ADDRESSES   => ( 0 => x"d000", 1 => x"d300", 2 => x"b000",  3 => x"b200",  4 => x"b400",  5 => x"b600", 6 => x"c000",
+                            7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e500", 12 => x"e400", 13 => x"e410", others => x"0000"),
+      PORT_ADDR_MASK   => ( 0 => 12,      1 => 1,       2 => 9,        3 => 9,        4 => 9,        5 => 9,       6  => 12,
+                            7 =>  9,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 4,       13 =>  2, others => 0),
       PORT_MASK_ENABLE => 1
       )
     port map(
@@ -1134,7 +1136,7 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 --         HIT_CAL_IN         => clk_full_osc,--clk_cal,    -- Hits for calibrating the TDC  --FIXME: here we need a good cal clock!
 --         -- Trigger signals from handler
 --         BUSRDO_RX          => cts_rdo_rx,
---         BUSRDO_TX          => cts_rdo_additional_TDCcal,--_TDCcal
+--         BUSRDO_TX          => cts_rdo_additional(INCLUDE_ETM),--_TDCcal
 --         -- Slow control bus
 --         BUS_RX             => bustdc_rx,
 --         BUS_TX             => bustdc_tx,
@@ -1143,57 +1145,6 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 --         LOGIC_ANALYSER_OUT => open
 --         );
 -- 
---   
-  gen_TDC_onlineCal: if (INCLUDE_TDC = c_YES) generate
-    gen_onlineCal: if (INCLUDE_CALIBRATION = c_YES) generate     
-        THE_TDC_CAL : entity work.TDC_Calibration
-        generic map(
-          IS_COMBINER       => c_NO,
-          USE_STAT_BITS     => c_YES,
-          USE_DATA_WRITE    => c_YES,
-          USE_DATA_FINISHED => c_YES,
-          USE_BUSY_RELEASE  => c_YES
-        )
-        port map ( 
-            CLK         => clk_sys,
-            RESET       => reset_i,
-            DIN         => cts_rdo_additional_TDCcal.data,
-            DIN_TYPE    => x"4",
-            DIN_info(31 downto 0)  => cts_rdo_additional_TDCcal.statusbits,
-            DIN_info(32)  => cts_rdo_additional_TDCcal.busy_release,
-            DIN_info(33)  => cts_rdo_additional_TDCcal.data_write,
-            DIN_info(34)  => cts_rdo_additional_TDCcal.data_finished,
-            DIN_READY   => '1',
-            DIN_STAT    => (others=>'0'),
-            FPGA_in     => timer.network_address,
-            TRIGG_TYPE  => cts_rdo_rx.trg_type,
-            DOUT        => cts_rdo_additional(INCLUDE_ETM).data,
-            DOUT_info(31 downto 0)  => cts_rdo_additional(INCLUDE_ETM).statusbits,
-            DOUT_info(32)  => cts_rdo_additional(INCLUDE_ETM).busy_release,
-            DOUT_info(33)  => cts_rdo_additional(INCLUDE_ETM).data_write,
-            DOUT_info(34)  => cts_rdo_additional(INCLUDE_ETM).data_finished,
-            DOUT_TYPE   => open,
-            DOUT_READY  => open,
-            DOUT_STAT   => open,
-            BUS_RX      => bustdccal_rx,
-            BUS_TX      => bustdccal_tx
-          );
-      end generate;  
-  
-    gen_no_onlineCal: if (INCLUDE_CALIBRATION = c_NO) generate     
-    
-          cts_rdo_additional(INCLUDE_ETM).data          <= cts_rdo_additional_TDCcal.data;
-          cts_rdo_additional(INCLUDE_ETM).statusbits    <= cts_rdo_additional_TDCcal.statusbits;
-          cts_rdo_additional(INCLUDE_ETM).busy_release  <= cts_rdo_additional_TDCcal.busy_release;
-          cts_rdo_additional(INCLUDE_ETM).data_write    <= cts_rdo_additional_TDCcal.data_write;
-          cts_rdo_additional(INCLUDE_ETM).data_finished <= cts_rdo_additional_TDCcal.data_finished;
-
-          bustdccal_tx.ack     <= '0';
-          bustdccal_tx.nack    <= '1';
-          bustdccal_tx.unknown <= '1';
-          
-    end generate; --Calib   
-  end generate; -- TDC Calib
 
     -- For single edge measurements
     gen_single : if (DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 ) and (INCLUDE_ETM = c_NO) generate