\section{TRB3 \& AddOn}
-I/O from the TRB is provided via an Ada-AddOn with two connectors and 40 wire pairs each.
-Alternatively, the 4conn-AddOn provides four connectors with 20 wire pairs each. Appendix
+I/O from the TRB is provided via an 4conn-AddOn with four connectors and 20 wire pairs each.
+Alternatively, the ADA-AddOn provides two connectors with 40 wire pairs each. Appendix
\ref{ADApinout} shows, that the pin-out of the 4conn-AddOn fits better with respect to the
possibility to connect two identical CB to one FPGA.
-
Using the standard AddOns from GSI with their standard connector (KEL 8925E series) saves us from
building new boards.
\item Improve signal quality with LVDS drivers
\item Improve robustness by using different cables
\item Additional optical link for higher data bandwidth
- \item Not required for first iteration, can easily be added later
\end{itemize*}
}
+\clearpage
\section{Cable TRB to CB}
The 40-pair twisted pair flat cable used for TDC applications at GSI provides all connectivity for
one converter board. The cables can be made in any length, so we can do studies about the maximum
Table \ref{iocount} gives a rough count of necessary I/O. The final number of connections required
will strongly depend on the realization of the converter board, mainly with respect to the data
-buses for switches and ADCs. A.t.m. there are 14 I/O per converter board plus 14 I/O per sensor.
+buses for switches and ADCs. A.t.m. there are 14 I/O per converter board plus 15 I/O per sensor.
Note that this setup is for M26 sensors only where we will not have any ladders larger than 2
sensors. The number of I/O for the final sensor will be different.
-The available AddOns for TRB3 have 12 or 13 differential outputs for each CB available.
+The available AddOns for TRB3 have up to 15 differential outputs for each CB available. If we
+connect the power supply and switch IC via single ended connections, the number of required
+differential ports fits this number.
-\begin{table}[htp]
+\begin{table}[hbtp]
\centering
\begin{tabularx}{\textwidth}{X|c|c|c|c}
& \multicolumn{2}{c|}{\textbf{per Ladder}} & \multicolumn{2}{c}{\textbf{per
JTAG: TDI,TMS,TCK, TDO & 1 & 3 & 0 & 0\\
Sensor Data: Clock, Marker, 2x Data per sensor & 0 & 0 & 8 & 0\\
Sensor Control: Clock, Start, Reset. & 0 & 3 (2) & 0 & 0\\
-ADC for voltages and currents (SPI) & 0 & 3 & 2 & 1 (1)\\
-Voltage and JTAG switch (Bus) & 0 & 4 (4) & 0 & 1 (1) \\
+ADC for voltages and currents (SPI) & 0 & 2 & 2 & 2 \\
+Voltage and JTAG switch (Bus) & 0 & 3 (3) & 0 & 1 (1) \\
+DAC & 0 & 3 (3) & 0 & 0 \\
Fast Overcurrent Sense & 0 & 0 & 2 (2) & 0 \\
\hline
-Total & 1 & 13 (6) & 12 (2) & 2 (2)\\
-Proposal for ADA-AddOn & 1 & 10 + 3 & 12 & 1 + 1 \\
+Total & 1 & 14 (8) & 12 (2) & 3 (1)\\
+Proposal for 4conn-AddOn & 1 & 11 + 3 & 12 & 2 + 1 \\
\end{tabularx}
\caption{Inputs/Outputs from the FPGA to the converter board. The number in
parentheses shows the number of I/O that could be replaced by a non-differential connection.}
\subsection{Voltage and Current Monitoring}
All voltages and currents should be monitored. These are three supply voltages and currents per
sensor (i.e. analog and digital VDD as well as the clamping voltage), the 8 internally generated
-bias voltages and the temperature.
+bias voltages, the temperature and ground sense.
The temperature measurement needs an external differential amplification. The signal of the
temperature diode can only be measured using a sense line for the actual ground level on the sensor
wire and the output of the temperature diode. This could also be implemented using a differential
ADC channel.
-The 8 VDiscr signals must be monitored both single ended and differential\footnote{The voltages
+The 8 VDiscr signals must be analyzed both single ended and differential\footnote{The voltages
are labeled 1A-1D and 2A-2D. We need both the absolute value of the voltages ($\approx$2V) as well
-as the differences between 1A-2A, 1B-2B etc. These are in the order of $\pm$ 32 mV.}. I.e. must use
-a ADC that can switch input pairs from single ended to differential and provides a selectable input
-amplification of 20 - 50.
-
-In total, 7 single ended plus 4 differential ADC channels are needed per sensor. If two 8-channel
-ADC are used, the remaining channel can be connected to the ground sense wire.
+as the differences between 1A-2A, 1B-2B etc. These are in the order of $\pm$ 32 mV.}. I.e. we should
+use a ADC that can switch input pairs from single ended to differential.
-The on-board ADC should provide about 1 MSPS and a SPI (or similar) interface. AD7928 is a
-possible candidate for single ended measurement.
-(I do not have a differential ADC in mind yet, but the ADC implemented in ATtiny micro-controllers
-does fit the requirements despite conversion speed.)
+In total, 16 ADC channels are needed per sensor. The on-board ADC should provide about 200 kSPS,
+14-16 Bit resolution and a SPI (or similar) interface. A candidate is LTC1863L.
If necessary, an external monitoring board or oscilloscope can be connected for testing purposes.
Such a TRB3-AddOn is currently in preparation at GSI (52 channels, 12 Bit, 40 MSPS).
Current sensing can be implemented with dedicated current monitors, e.g. TSC101 to reduce count of
-components.
+components. ZXCT1022 would be available from GSI for free.
For latch-up protection, fast discriminators with settable threshold (via DAC) provide a logical
signal to the FPGA about the current status of the current levels. Necessary action is taken by the
\subsection{Board Control}
All voltages are switchable from FPGA. The JTAG chain needs the option to disable individual
-sensors. Both features can make use of a 74HC259 IC to reduce number of lines. This chip also
-provides the CE signals for ADCs if needed.
+sensors. Both features can make use of a 74HC259 IC to reduce number of lines.
For clamping voltages and current monitoring thresholds 4 configurable voltages are necessary per
sensor. The clamping can be provided by the previous method where it can be changed with a
potentiometer only. The threshold voltages for current monitoring must be configurable at run-time
-with a slow but precise DAC.
+with a slow but precise DAC. LTC2600 has already been used in many of our designs, is easy to
+control and chainable.
-\subsection{Components}
+\subsection{Other Remarks}
\begin{itemize*}
\item Inductivities on power rails can be replaced by ferrite beads (less DC resistance, higher
current, smaller form factor), e.g. BLM41 and similar.
+ \item All non-differential outputs should foresee to use ferrite beads / resistors and capacitors
+to reduce the slew rate
\end{itemize*}
\clearpage
FPGA. Unfortunately, pin-out at the FPGA of the two connectors of the AddOn is slightly different.
Hence, there are 12 differential outputs available on both connectors only.
-We could also use the 4-conn AddOn with four 40-pin connectors and slightly shuffled connections on
-the FPGA if pin-out fits better.
+The better choice is to use the 4-conn AddOn with four 40-pin connectors and slightly shuffled
+connections on the FPGA if pin-out fits better. One CB can be connected to ports 1 and 3, the other
+to 2 and 4. In total, this yields 15 differential outputs.
+An additional ground cable is required between the power supplies for the CB and the stack of TRBs.
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