#################################################################
#MuPix 8
#################################################################
-LOCATE COMP "MupixBoard8_0/mupix_data_link/gen_serdes_sim.mupix_serdes_sim/PCSD_INST" SITE "PCSB";
-#LOCATE COMP "MupixBoard8_0/mupix_data_link/mupix_serdes_new/PCSD_INST" SITE "PCSB";
+LOCATE COMP "MupixBoard8_0/mupix_data_link/gen_serdes_400.mupix_serdes/PCSD_INST" SITE "PCSB";
+#LOCATE COMP "MupixBoard8_0/mupix_data_link/gen_serdes_600.mupix_serdes/PCSD_INST" SITE "PCSB";
+#LOCATE COMP "MupixBoard8_0/mupix_data_link/gen_serdes_800.mupix_serdes/PCSD_INST" SITE "PCSB";
+#LOCATE COMP "MupixBoard8_0/mupix_data_link/gen_serdes_1250.mupix_serdes/PCSD_INST" SITE "PCSB";
LOCATE COMP "led_addon_0" SITE "P1";
LOCATE COMP "led_addon_1" SITE "P2";
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="FIFO_32_512" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 07 19 14:17:31.148" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="FIFO_32_512.lpc" type="lpc" modified="2018 07 19 14:17:28.000"/>
+ <File name="FIFO_32_512.vhd" type="top_level_vhdl" modified="2018 07 19 14:17:28.000"/>
+ <File name="FIFO_32_512_tmpl.vhd" type="template_vhdl" modified="2018 07 19 14:17:28.000"/>
+ <File name="tb_FIFO_32_512_tmpl.vhd" type="testbench_vhdl" modified="2018 07 19 14:17:28.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=FIFO_32_512
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/19/2018
+Time=14:17:28
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=32
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n FIFO_32_512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 9 -data_width 32 -num_words 512 -no_enable -pe -1 -pf -1
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.1
+--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n FIFO_32_512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -no_enable -pe -1 -pf -1
+
+-- Thu Jul 19 14:17:28 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity FIFO_32_512 is
+ port (
+ Data: in std_logic_vector(31 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end FIFO_32_512;
+
+architecture Structure of FIFO_32_512 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal cnt_con: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32_512.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1),
+ DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6),
+ DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ FF_31: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_30: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_29: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_28: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_27: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_26: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_25: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_24: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_23: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_22: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_21: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_20: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_19: FD1P3DX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_18: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_17: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_16: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_15: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_14: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_13: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_12: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_11: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_10: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_9: FD1P3DX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_8: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_7: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_6: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_5: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_4: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_3: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_2: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_1: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_0: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co3_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of FIFO_32_512 is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:CB2 use entity ecp3.CB2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="FIFO_40_512" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 07 22 16:37:51.091" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="FIFO_40_512.lpc" type="lpc" modified="2018 07 22 16:37:48.000"/>
+ <File name="FIFO_40_512.vhd" type="top_level_vhdl" modified="2018 07 22 16:37:48.000"/>
+ <File name="FIFO_40_512_tmpl.vhd" type="template_vhdl" modified="2018 07 22 16:37:48.000"/>
+ <File name="tb_FIFO_40_512_tmpl.vhd" type="testbench_vhdl" modified="2018 07 22 16:37:48.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=FIFO_40_512
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/22/2018
+Time=16:37:48
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=40
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n FIFO_40_512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 9 -data_width 40 -num_words 512 -no_enable -pe -1 -pf -1 -fill
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.1
+--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n FIFO_40_512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 40 -depth 512 -no_enable -pe -1 -pf -1 -fill
+
+-- Sun Jul 22 16:37:48 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity FIFO_40_512 is
+ port (
+ Data: in std_logic_vector(39 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(39 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end FIFO_40_512;
+
+architecture Structure of FIFO_40_512 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal cnt_con: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "FIFO_40_512.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "FIFO_40_512.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_1: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ pdp_ram_0_1_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>scuba_vlo, DI5=>scuba_vlo,
+ DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
+ DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo,
+ DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
+ DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
+ DO20=>Q(38), DO21=>Q(39), DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ FF_31: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_30: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_29: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_28: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_27: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_26: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_25: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_24: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_23: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_22: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_21: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_20: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_19: FD1P3DX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_18: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_17: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_16: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_15: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_14: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_13: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_12: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_11: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_10: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_9: FD1P3DX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_8: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_7: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_6: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_5: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_4: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_3: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_2: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_1: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_0: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co3_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of FIFO_40_512 is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:CB2 use entity ecp3.CB2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package Mupix_PLL is
+
+ component mupix_pll_main_40 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_main_40;
+
+ component mupix_pll_main_60 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_main_60;
+
+ component mupix_pll_main_80 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_main_80;
+
+ component mupix_pll_main_125 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_main_125;
+
+ component mupix_pll_sim_40 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ CLKOS : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_sim_40;
+
+ component mupix_pll_sim_80 is
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ CLKOS : out std_logic;
+ LOCK : out std_logic);
+ end component mupix_pll_sim_80;
+
+end package Mupix_PLL;
+
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_main_125" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 14:50:38.570" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_main_125.lpc" type="lpc" modified="2018 08 02 14:50:36.000"/>
+ <File name="mupix_pll_main_125.vhd" type="top_level_vhdl" modified="2018 08 02 14:50:36.000"/>
+ <File name="mupix_pll_main_125_tmpl.vhd" type="template_vhdl" modified="2018 08 02 14:50:36.000"/>
+ </Package>
+</DiamondModule>
[Device]
Family=latticeecp3
PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
Package=FPBGA672
OperatingCondition=COM
Status=P
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
-ModuleName=pll_mupix_main
+ModuleName=mupix_pll_main_125
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=12/22/2017
-Time=11:58:04
+Date=08/02/2018
+Time=14:50:36
[Parameters]
Verilog=0
enClkOK2=0
[Command]
-cmd_line= -w -n pll_mupix_main -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+cmd_line= -w -n mupix_pll_main_125 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
-- Module Version: 5.7
---/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n pll_mupix_main -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_main_125 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- Fri Dec 22 11:58:04 2017
+-- Thu Aug 2 14:50:36 2018
library IEEE;
use IEEE.std_logic_1164.all;
use ecp3.components.all;
-- synopsys translate_on
-entity pll_mupix_main is
+entity mupix_pll_main_125 is
port (
CLK: in std_logic;
CLKOP: out std_logic;
LOCK: out std_logic);
-end pll_mupix_main;
+end mupix_pll_main_125;
-architecture Structure of pll_mupix_main is
+architecture Structure of mupix_pll_main_125 is
-- internal signal declarations
signal CLKOP_t: std_logic;
-- synopsys translate_off
library ecp3;
-configuration Structure_CON of pll_mupix_main is
+configuration Structure_CON of mupix_pll_main_125 is
for Structure
for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
for all:VLO use entity ecp3.VLO(V); end for;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_main_40" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 14:49:15.145" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_main_40.lpc" type="lpc" modified="2018 08 02 14:49:00.000"/>
+ <File name="mupix_pll_main_40.vhd" type="top_level_vhdl" modified="2018 08 02 14:49:00.000"/>
+ <File name="mupix_pll_main_40_tmpl.vhd" type="template_vhdl" modified="2018 08 02 14:49:00.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=mupix_pll_main_40
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=14:49:00
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=16
+U_OFrq=40
+OP_Tol=0.0
+OFrq=40.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n mupix_pll_main_40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_main_40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Thu Aug 2 14:49:00 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mupix_pll_main_40 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end mupix_pll_main_40;
+
+architecture Structure of mupix_pll_main_40 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "40.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 1, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mupix_pll_main_40 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_main_60" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:39:29.112" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_main_60.lpc" type="lpc" modified="2018 08 02 15:39:27.000"/>
+ <File name="mupix_pll_main_60.vhd" type="top_level_vhdl" modified="2018 08 02 15:39:27.000"/>
+ <File name="mupix_pll_main_60_tmpl.vhd" type="template_vhdl" modified="2018 08 02 15:39:27.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=mupix_pll_main_60
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=15:39:27
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=10
+ClkOPBp=0
+Post=16
+U_OFrq=60
+OP_Tol=0.0
+OFrq=60.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=3
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.282879
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n mupix_pll_main_60 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 60 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_main_60 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 60 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Thu Aug 2 15:39:27 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mupix_pll_main_60 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end mupix_pll_main_60;
+
+architecture Structure of mupix_pll_main_60 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 3, CLKI_DIV=> 10,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mupix_pll_main_60 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_main_80" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 14:49:59.493" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_main_80.lpc" type="lpc" modified="2018 08 02 14:49:57.000"/>
+ <File name="mupix_pll_main_80.vhd" type="top_level_vhdl" modified="2018 08 02 14:49:57.000"/>
+ <File name="mupix_pll_main_80_tmpl.vhd" type="template_vhdl" modified="2018 08 02 14:49:57.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=mupix_pll_main_80
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=14:49:57
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=8
+U_OFrq=80
+OP_Tol=0.0
+OFrq=80.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=2
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n mupix_pll_main_80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_main_80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Thu Aug 2 14:49:57 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mupix_pll_main_80 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end mupix_pll_main_80;
+
+architecture Structure of mupix_pll_main_80 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "80.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 2, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mupix_pll_main_80 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_sim_40" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:28:37.078" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_sim_40.lpc" type="lpc" modified="2018 08 02 15:28:34.000"/>
+ <File name="mupix_pll_sim_40.vhd" type="top_level_vhdl" modified="2018 08 02 15:28:35.000"/>
+ <File name="mupix_pll_sim_40_tmpl.vhd" type="template_vhdl" modified="2018 08 02 15:28:35.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=mupix_pll_sim_40
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=15:28:34
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=16
+U_OFrq=40
+OP_Tol=0.0
+OFrq=40.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n mupix_pll_sim_40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_sim_40 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
+
+-- Thu Aug 2 15:28:35 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mupix_pll_sim_40 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ LOCK: out std_logic);
+end mupix_pll_sim_40;
+
+architecture Structure of mupix_pll_sim_40 is
+
+ -- internal signal declarations
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "40.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP",
+ DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0,
+ CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 1, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mupix_pll_sim_40 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_pll_sim_80" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:31:34.001" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_pll_sim_80.lpc" type="lpc" modified="2018 08 02 15:31:32.000"/>
+ <File name="mupix_pll_sim_80.vhd" type="top_level_vhdl" modified="2018 08 02 15:31:32.000"/>
+ <File name="mupix_pll_sim_80_tmpl.vhd" type="template_vhdl" modified="2018 08 02 15:31:32.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=mupix_pll_sim_80
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=15:31:32
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=8
+U_OFrq=80
+OP_Tol=0.0
+OFrq=80.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=2
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n mupix_pll_sim_80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 5.7
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n mupix_pll_sim_80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
+
+-- Thu Aug 2 15:31:32 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity mupix_pll_sim_80 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ LOCK: out std_logic);
+end mupix_pll_sim_80;
+
+architecture Structure of mupix_pll_sim_80 is
+
+ -- internal signal declarations
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "80.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP",
+ DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0,
+ CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 2, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of mupix_pll_sim_80 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="RAM_DP_4096_32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 07 19 14:16:16.570" version="6.5" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2018 07 19 14:16:16.000"/>
+ <File name="RAM_DP_4096_32.lpc" type="lpc" modified="2018 07 19 14:16:11.000"/>
+ <File name="RAM_DP_4096_32.vhd" type="top_level_vhdl" modified="2018 07 19 14:16:11.000"/>
+ <File name="RAM_DP_4096_32_tmpl.vhd" type="template_vhdl" modified="2018 07 19 14:16:11.000"/>
+ <File name="tb_RAM_DP_4096_32_tmpl.vhd" type="testbench_vhdl" modified="2018 07 19 14:16:11.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.5
+ModuleName=RAM_DP_4096_32
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/19/2018
+Time=14:16:11
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=4096
+RData=32
+WAddress=4096
+WData=32
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=0
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
+
+[Command]
+cmd_line= -w -n RAM_DP_4096_32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 12 -rwidth 32 -waddr_width 12 -wwidth 32 -rnum_words 4096 -wnum_words 4096 -cascade -1
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module Version: 6.5
+--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n RAM_DP_4096_32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 4096 -cascade -1
+
+-- Thu Jul 19 14:16:11 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity RAM_DP_4096_32 is
+ port (
+ WrAddress: in std_logic_vector(11 downto 0);
+ RdAddress: in std_logic_vector(11 downto 0);
+ Data: in std_logic_vector(31 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(31 downto 0));
+end RAM_DP_4096_32;
+
+architecture Structure of RAM_DP_4096_32 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_0_7 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_0_7 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_0_7 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_1_6 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_1_6 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_1_6 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_2_5 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_2_5 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_2_5 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_3_4 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_3_4 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_3_4 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_4_3 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_4_3 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_4_3 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_5_2 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_5_2 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_5_2 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_6_1 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_6_1 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_6_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of RAM_DP_4096_32_0_7_0 : label is "RAM_DP_4096_32.lpc";
+ attribute MEM_INIT_FILE of RAM_DP_4096_32_0_7_0 : label is "";
+ attribute RESETMODE of RAM_DP_4096_32_0_7_0 : label is "SYNC";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ RAM_DP_4096_32_0_0_7: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
+ DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ RAM_DP_4096_32_0_1_6: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
+ DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7),
+ DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ RAM_DP_4096_32_0_2_5: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10),
+ DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>Q(10),
+ DOB3=>Q(11), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ RAM_DP_4096_32_0_3_4: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14),
+ DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>Q(14),
+ DOB3=>Q(15), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ RAM_DP_4096_32_0_4_3: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18),
+ DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18),
+ DOB3=>Q(19), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ RAM_DP_4096_32_0_5_2: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22),
+ DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>Q(22),
+ DOB3=>Q(23), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ RAM_DP_4096_32_0_6_1: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26),
+ DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>Q(26),
+ DOB3=>Q(27), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ RAM_DP_4096_32_0_7_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30),
+ DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>WrAddress(0),
+ ADA3=>WrAddress(1), ADA4=>WrAddress(2), ADA5=>WrAddress(3),
+ ADA6=>WrAddress(4), ADA7=>WrAddress(5), ADA8=>WrAddress(6),
+ ADA9=>WrAddress(7), ADA10=>WrAddress(8), ADA11=>WrAddress(9),
+ ADA12=>WrAddress(10), ADA13=>WrAddress(11), CEA=>WrClockEn,
+ CLKA=>WrClock, OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>RdAddress(0),
+ ADB3=>RdAddress(1), ADB4=>RdAddress(2), ADB5=>RdAddress(3),
+ ADB6=>RdAddress(4), ADB7=>RdAddress(5), ADB8=>RdAddress(6),
+ ADB9=>RdAddress(7), ADB10=>RdAddress(8), ADB11=>RdAddress(9),
+ ADB12=>RdAddress(10), ADB13=>RdAddress(11), CEB=>RdClockEn,
+ CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>Q(30),
+ DOB3=>Q(31), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of RAM_DP_4096_32 is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package Mupix_Serdes is
+
+ component mupix_serdes_400 is
+ generic (
+ USER_CONFIG_FILE : String);
+ port (
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+ end component mupix_serdes_400;
+
+ component mupix_serdes_600 is
+ generic (
+ USER_CONFIG_FILE : String);
+ port (
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+ end component mupix_serdes_600;
+
+ component mupix_serdes_800 is
+ generic (
+ USER_CONFIG_FILE : String);
+ port (
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+ end component mupix_serdes_800;
+
+ component mupix_serdes_1250 is
+ generic (
+ USER_CONFIG_FILE : String);
+ port (
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+ end component mupix_serdes_1250;
+
+end package Mupix_Serdes;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_serdes_1250" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:16:36.883" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_serdes_1250.lpc" type="lpc" modified="2018 08 02 15:16:33.000"/>
+ <File name="mupix_serdes_1250.pp" type="pp" modified="2018 08 02 15:16:33.000"/>
+ <File name="mupix_serdes_1250.sym" type="sym" modified="2018 08 02 15:16:34.000"/>
+ <File name="mupix_serdes_1250.tft" type="tft" modified="2018 08 02 15:16:33.000"/>
+ <File name="mupix_serdes_1250.txt" type="pcs_module" modified="2018 08 02 15:16:33.000"/>
+ <File name="mupix_serdes_1250.vhd" type="top_level_vhdl" modified="2018 08 02 15:16:33.000"/>
+ </Package>
+</DiamondModule>
[Device]
Family=latticeecp3
PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
Package=FPBGA672
OperatingCondition=COM
Status=P
CoreStatus=Demo
CoreName=PCS
CoreRevision=8.2
-ModuleName=mupix_serdes_new
+ModuleName=mupix_serdes_1250
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=05/25/2018
-Time=10:05:57
+Date=08/02/2018
+Time=15:16:33
[Parameters]
Verilog=0
PARTrace3=0
[FilesGenerated]
-mupix_serdes_new.pp=pp
-mupix_serdes_new.tft=tft
-mupix_serdes_new.txt=pcs_module
-mupix_serdes_new.sym=sym
+mupix_serdes_1250.pp=pp
+mupix_serdes_1250.tft=tft
+mupix_serdes_1250.txt=pcs_module
+mupix_serdes_1250.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXONLY"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 125.0
+#define _ch0_rx_datarange "MED"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "125.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 125.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "DISABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXONLY"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 125.0
+#define _ch1_rx_datarange "MED"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "125.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 125.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "DISABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXONLY"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "ENABLED"
+#define _ch2_tx_ficlk_rate 125.0
+#define _ch2_rx_datarange "MED"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "125.0"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 125.0
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "AC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "DISABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXONLY"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 125.0
+#define _ch3_rx_datarange "MED"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "125.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 125.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "DISABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MED"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 125.0
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "ENABLED"
+#define _sci_ports "DISABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "ENABLED"
+#define _circuit_name mupix_serdes_1250
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: Lattice Semiconductor Corporation
+ MODULE: mupix_serdes_1250
+ DESIGN: mupix_serdes_1250
+ FILENAME: mupix_serdes_1250.readme
+ PROJECT: Unknown
+ VERSION: 2.0
+ This file is auto generated by the ispLEVER
+
+
+NOTE: This readme file has been provided to instantiate the interface
+netlist. Since this template contains synthesis attributes for precision that
+are crucial to the design flow, we recommend that you use this
+template in your FPGA design.
+entity chip is
+port (
+
+-- Add your FPGA design top level I/Os here
+
+
+-- ASIC side pins for PCSD. These pins must exist for the
+-- PCS core.
+ refclkp : in std_logic;
+ refclkn : in std_logic;
+ hdinp_ch0 : in std_logic;
+ hdinn_ch0 : in std_logic;
+ hdinp_ch1 : in std_logic;
+ hdinn_ch1 : in std_logic;
+ hdinp_ch2 : in std_logic;
+ hdinn_ch2 : in std_logic;
+ hdinp_ch3 : in std_logic;
+ hdinn_ch3 : in std_logic;
+
+ hdoutp_ch0 : out std_logic;
+ hdoutn_ch0 : out std_logic;
+ hdoutp_ch1 : out std_logic;
+ hdoutn_ch1 : out std_logic;
+ hdoutp_ch2 : out std_logic;
+ hdoutn_ch2 : out std_logic;
+ hdoutp_ch3 : out std_logic;
+ hdoutn_ch3 : out std_logic;
+
+
+);
+end chip;
+
+architecture chip_arch of chip is
+
+-- This defines all the high-speed ports. You may have to remove
+-- some of them depending on your design.
+attribute nopad : string;
+attribute nopad of
+ refclkp, refclkn,
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
+
+ COMPONENT mupix_serdes_1250
+ PORT(
+ hdinp_ch0 : IN std_logic;
+ hdinn_ch0 : IN std_logic;
+ rxiclk_ch0 : IN std_logic;
+ fpga_rxrefclk_ch0 : IN std_logic;
+ word_align_en_ch0_c : IN std_logic;
+ rx_pwrup_ch0_c : IN std_logic;
+ rx_div2_mode_ch0_c : IN std_logic;
+ hdinp_ch1 : IN std_logic;
+ hdinn_ch1 : IN std_logic;
+ rxiclk_ch1 : IN std_logic;
+ fpga_rxrefclk_ch1 : IN std_logic;
+ word_align_en_ch1_c : IN std_logic;
+ rx_pwrup_ch1_c : IN std_logic;
+ rx_div2_mode_ch1_c : IN std_logic;
+ hdinp_ch2 : IN std_logic;
+ hdinn_ch2 : IN std_logic;
+ rxiclk_ch2 : IN std_logic;
+ fpga_rxrefclk_ch2 : IN std_logic;
+ word_align_en_ch2_c : IN std_logic;
+ rx_pwrup_ch2_c : IN std_logic;
+ rx_div2_mode_ch2_c : IN std_logic;
+ hdinp_ch3 : IN std_logic;
+ hdinn_ch3 : IN std_logic;
+ rxiclk_ch3 : IN std_logic;
+ fpga_rxrefclk_ch3 : IN std_logic;
+ word_align_en_ch3_c : IN std_logic;
+ rx_pwrup_ch3_c : IN std_logic;
+ rx_div2_mode_ch3_c : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_sync_qd_c : IN std_logic;
+ rst_n : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ rx_full_clk_ch0 : OUT std_logic;
+ rx_half_clk_ch0 : OUT std_logic;
+ rxdata_ch0 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch0 : OUT std_logic;
+ rx_disp_err_ch0 : OUT std_logic;
+ rx_cv_err_ch0 : OUT std_logic;
+ rx_los_low_ch0_s : OUT std_logic;
+ rx_cdr_lol_ch0_s : OUT std_logic;
+ rx_full_clk_ch1 : OUT std_logic;
+ rx_half_clk_ch1 : OUT std_logic;
+ rxdata_ch1 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch1 : OUT std_logic;
+ rx_disp_err_ch1 : OUT std_logic;
+ rx_cv_err_ch1 : OUT std_logic;
+ rx_los_low_ch1_s : OUT std_logic;
+ rx_cdr_lol_ch1_s : OUT std_logic;
+ rx_full_clk_ch2 : OUT std_logic;
+ rx_half_clk_ch2 : OUT std_logic;
+ rxdata_ch2 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch2 : OUT std_logic;
+ rx_disp_err_ch2 : OUT std_logic;
+ rx_cv_err_ch2 : OUT std_logic;
+ rx_los_low_ch2_s : OUT std_logic;
+ rx_cdr_lol_ch2_s : OUT std_logic;
+ rx_full_clk_ch3 : OUT std_logic;
+ rx_half_clk_ch3 : OUT std_logic;
+ rxdata_ch3 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch3 : OUT std_logic;
+ rx_disp_err_ch3 : OUT std_logic;
+ rx_cv_err_ch3 : OUT std_logic;
+ rx_los_low_ch3_s : OUT std_logic;
+ rx_cdr_lol_ch3_s : OUT std_logic;
+ refclk2fpga : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+ uut: mupix_serdes_1250 PORT MAP(
+ hdinp_ch0 => hdinp_ch0,
+ hdinn_ch0 => hdinn_ch0,
+ rxiclk_ch0 => rxiclk_ch0,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
+ rxdata_ch0 => rxdata_ch0,
+ rx_k_ch0 => rx_k_ch0,
+ rx_disp_err_ch0 => rx_disp_err_ch0,
+ rx_cv_err_ch0 => rx_cv_err_ch0,
+ word_align_en_ch0_c => word_align_en_ch0_c,
+ rx_pwrup_ch0_c => rx_pwrup_ch0_c,
+ rx_los_low_ch0_s => rx_los_low_ch0_s,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
+ rx_div2_mode_ch0_c => rx_div2_mode_ch0_c,
+ hdinp_ch1 => hdinp_ch1,
+ hdinn_ch1 => hdinn_ch1,
+ rxiclk_ch1 => rxiclk_ch1,
+ rx_full_clk_ch1 => rx_full_clk_ch1,
+ rx_half_clk_ch1 => rx_half_clk_ch1,
+ fpga_rxrefclk_ch1 => fpga_rxrefclk_ch1,
+ rxdata_ch1 => rxdata_ch1,
+ rx_k_ch1 => rx_k_ch1,
+ rx_disp_err_ch1 => rx_disp_err_ch1,
+ rx_cv_err_ch1 => rx_cv_err_ch1,
+ word_align_en_ch1_c => word_align_en_ch1_c,
+ rx_pwrup_ch1_c => rx_pwrup_ch1_c,
+ rx_los_low_ch1_s => rx_los_low_ch1_s,
+ rx_cdr_lol_ch1_s => rx_cdr_lol_ch1_s,
+ rx_div2_mode_ch1_c => rx_div2_mode_ch1_c,
+ hdinp_ch2 => hdinp_ch2,
+ hdinn_ch2 => hdinn_ch2,
+ rxiclk_ch2 => rxiclk_ch2,
+ rx_full_clk_ch2 => rx_full_clk_ch2,
+ rx_half_clk_ch2 => rx_half_clk_ch2,
+ fpga_rxrefclk_ch2 => fpga_rxrefclk_ch2,
+ rxdata_ch2 => rxdata_ch2,
+ rx_k_ch2 => rx_k_ch2,
+ rx_disp_err_ch2 => rx_disp_err_ch2,
+ rx_cv_err_ch2 => rx_cv_err_ch2,
+ word_align_en_ch2_c => word_align_en_ch2_c,
+ rx_pwrup_ch2_c => rx_pwrup_ch2_c,
+ rx_los_low_ch2_s => rx_los_low_ch2_s,
+ rx_cdr_lol_ch2_s => rx_cdr_lol_ch2_s,
+ rx_div2_mode_ch2_c => rx_div2_mode_ch2_c,
+ hdinp_ch3 => hdinp_ch3,
+ hdinn_ch3 => hdinn_ch3,
+ rxiclk_ch3 => rxiclk_ch3,
+ rx_full_clk_ch3 => rx_full_clk_ch3,
+ rx_half_clk_ch3 => rx_half_clk_ch3,
+ fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
+ rxdata_ch3 => rxdata_ch3,
+ rx_k_ch3 => rx_k_ch3,
+ rx_disp_err_ch3 => rx_disp_err_ch3,
+ rx_cv_err_ch3 => rx_cv_err_ch3,
+ word_align_en_ch3_c => word_align_en_ch3_c,
+ rx_pwrup_ch3_c => rx_pwrup_ch3_c,
+ rx_los_low_ch3_s => rx_los_low_ch3_s,
+ rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
+ rx_div2_mode_ch3_c => rx_div2_mode_ch3_c,
+ fpga_txrefclk => fpga_txrefclk,
+ tx_sync_qd_c => tx_sync_qd_c,
+ refclk2fpga => refclk2fpga,
+ rst_n => rst_n,
+ serdes_rst_qd_c => serdes_rst_qd_c
+ );
+
+
+
+
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
--- CONFIG_FILE : String := "mupix_serdes_new.txt";
+-- CONFIG_FILE : String := "mupix_serdes_1250.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_CORE";
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-entity mupix_serdes_newrx_reset_sm is
+entity mupix_serdes_1250rx_reset_sm is
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
rx_los_low_ch_s : in std_logic;
rx_pcs_rst_ch_c : out std_logic
);
-end mupix_serdes_newrx_reset_sm ;
+end mupix_serdes_1250rx_reset_sm ;
-architecture rx_reset_sm_arch of mupix_serdes_newrx_reset_sm is
+architecture rx_reset_sm_arch of mupix_serdes_1250rx_reset_sm is
type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
-entity mupix_serdes_new is
- GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_new.txt");
+entity mupix_serdes_1250 is
+ GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_1250.txt");
port (
------------------
-- CH0 --
rst_n : in std_logic;
serdes_rst_qd_c : in std_logic);
-end mupix_serdes_new;
+end mupix_serdes_1250;
-architecture mupix_serdes_new_arch of mupix_serdes_new is
+architecture mupix_serdes_1250_arch of mupix_serdes_1250 is
component VLO
port (
Z : out std_logic);
end component;
-component mupix_serdes_newrx_reset_sm
+component mupix_serdes_1250rx_reset_sm
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
END IF;
END PROCESS;
-rx_reset_sm_ch0 : mupix_serdes_newrx_reset_sm
+rx_reset_sm_ch0 : mupix_serdes_1250rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch1 : mupix_serdes_newrx_reset_sm
+rx_reset_sm_ch1 : mupix_serdes_1250rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch2 : mupix_serdes_newrx_reset_sm
+rx_reset_sm_ch2 : mupix_serdes_1250rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch3 : mupix_serdes_newrx_reset_sm
+rx_reset_sm_ch3 : mupix_serdes_1250rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
wait;
END PROCESS;
--synopsys translate_on
-end mupix_serdes_new_arch ;
+end mupix_serdes_1250_arch ;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_serdes_400" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:04:21.355" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_serdes_400.lpc" type="lpc" modified="2018 08 02 15:02:05.000"/>
+ <File name="mupix_serdes_400.pp" type="pp" modified="2018 08 02 15:02:05.000"/>
+ <File name="mupix_serdes_400.sym" type="sym" modified="2018 08 02 15:02:05.000"/>
+ <File name="mupix_serdes_400.tft" type="tft" modified="2018 08 02 15:02:05.000"/>
+ <File name="mupix_serdes_400.txt" type="pcs_module" modified="2018 08 02 15:02:05.000"/>
+ <File name="mupix_serdes_400.vhd" type="top_level_vhdl" modified="2018 08 02 15:02:05.000"/>
+ </Package>
+</DiamondModule>
[Device]
Family=latticeecp3
PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
Package=FPBGA672
OperatingCondition=COM
Status=P
CoreStatus=Demo
CoreName=PCS
CoreRevision=8.2
-ModuleName=mupix_serdes_sim
+ModuleName=mupix_serdes_400
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=07/16/2018
-Time=14:50:00
+Date=08/02/2018
+Time=15:02:05
[Parameters]
Verilog=0
PARTrace3=0
[FilesGenerated]
-mupix_serdes_sim.pp=pp
-mupix_serdes_sim.tft=tft
-mupix_serdes_sim.txt=pcs_module
-mupix_serdes_sim.sym=sym
+mupix_serdes_400.pp=pp
+mupix_serdes_400.tft=tft
+mupix_serdes_400.txt=pcs_module
+mupix_serdes_400.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXONLY"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 40.0
+#define _ch0_rx_datarange "LOW"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "40.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 40.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "DISABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXONLY"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 40.0
+#define _ch1_rx_datarange "LOW"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "40.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 40.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "DISABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXONLY"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "ENABLED"
+#define _ch2_tx_ficlk_rate 40.0
+#define _ch2_rx_datarange "LOW"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "40.0"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 40.0
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "AC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "DISABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXONLY"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 40.0
+#define _ch3_rx_datarange "LOW"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "40.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 40.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "DISABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "LOW"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 40.0
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "ENABLED"
+#define _sci_ports "DISABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "ENABLED"
+#define _circuit_name mupix_serdes_400
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: Lattice Semiconductor Corporation
+ MODULE: mupix_serdes_400
+ DESIGN: mupix_serdes_400
+ FILENAME: mupix_serdes_400.readme
+ PROJECT: Unknown
+ VERSION: 2.0
+ This file is auto generated by the ispLEVER
+
+
+NOTE: This readme file has been provided to instantiate the interface
+netlist. Since this template contains synthesis attributes for precision that
+are crucial to the design flow, we recommend that you use this
+template in your FPGA design.
+entity chip is
+port (
+
+-- Add your FPGA design top level I/Os here
+
+
+-- ASIC side pins for PCSD. These pins must exist for the
+-- PCS core.
+ refclkp : in std_logic;
+ refclkn : in std_logic;
+ hdinp_ch0 : in std_logic;
+ hdinn_ch0 : in std_logic;
+ hdinp_ch1 : in std_logic;
+ hdinn_ch1 : in std_logic;
+ hdinp_ch2 : in std_logic;
+ hdinn_ch2 : in std_logic;
+ hdinp_ch3 : in std_logic;
+ hdinn_ch3 : in std_logic;
+
+ hdoutp_ch0 : out std_logic;
+ hdoutn_ch0 : out std_logic;
+ hdoutp_ch1 : out std_logic;
+ hdoutn_ch1 : out std_logic;
+ hdoutp_ch2 : out std_logic;
+ hdoutn_ch2 : out std_logic;
+ hdoutp_ch3 : out std_logic;
+ hdoutn_ch3 : out std_logic;
+
+
+);
+end chip;
+
+architecture chip_arch of chip is
+
+-- This defines all the high-speed ports. You may have to remove
+-- some of them depending on your design.
+attribute nopad : string;
+attribute nopad of
+ refclkp, refclkn,
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
+
+ COMPONENT mupix_serdes_400
+ PORT(
+ hdinp_ch0 : IN std_logic;
+ hdinn_ch0 : IN std_logic;
+ rxiclk_ch0 : IN std_logic;
+ fpga_rxrefclk_ch0 : IN std_logic;
+ word_align_en_ch0_c : IN std_logic;
+ rx_pwrup_ch0_c : IN std_logic;
+ rx_div2_mode_ch0_c : IN std_logic;
+ hdinp_ch1 : IN std_logic;
+ hdinn_ch1 : IN std_logic;
+ rxiclk_ch1 : IN std_logic;
+ fpga_rxrefclk_ch1 : IN std_logic;
+ word_align_en_ch1_c : IN std_logic;
+ rx_pwrup_ch1_c : IN std_logic;
+ rx_div2_mode_ch1_c : IN std_logic;
+ hdinp_ch2 : IN std_logic;
+ hdinn_ch2 : IN std_logic;
+ rxiclk_ch2 : IN std_logic;
+ fpga_rxrefclk_ch2 : IN std_logic;
+ word_align_en_ch2_c : IN std_logic;
+ rx_pwrup_ch2_c : IN std_logic;
+ rx_div2_mode_ch2_c : IN std_logic;
+ hdinp_ch3 : IN std_logic;
+ hdinn_ch3 : IN std_logic;
+ rxiclk_ch3 : IN std_logic;
+ fpga_rxrefclk_ch3 : IN std_logic;
+ word_align_en_ch3_c : IN std_logic;
+ rx_pwrup_ch3_c : IN std_logic;
+ rx_div2_mode_ch3_c : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_sync_qd_c : IN std_logic;
+ rst_n : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ rx_full_clk_ch0 : OUT std_logic;
+ rx_half_clk_ch0 : OUT std_logic;
+ rxdata_ch0 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch0 : OUT std_logic;
+ rx_disp_err_ch0 : OUT std_logic;
+ rx_cv_err_ch0 : OUT std_logic;
+ rx_los_low_ch0_s : OUT std_logic;
+ rx_cdr_lol_ch0_s : OUT std_logic;
+ rx_full_clk_ch1 : OUT std_logic;
+ rx_half_clk_ch1 : OUT std_logic;
+ rxdata_ch1 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch1 : OUT std_logic;
+ rx_disp_err_ch1 : OUT std_logic;
+ rx_cv_err_ch1 : OUT std_logic;
+ rx_los_low_ch1_s : OUT std_logic;
+ rx_cdr_lol_ch1_s : OUT std_logic;
+ rx_full_clk_ch2 : OUT std_logic;
+ rx_half_clk_ch2 : OUT std_logic;
+ rxdata_ch2 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch2 : OUT std_logic;
+ rx_disp_err_ch2 : OUT std_logic;
+ rx_cv_err_ch2 : OUT std_logic;
+ rx_los_low_ch2_s : OUT std_logic;
+ rx_cdr_lol_ch2_s : OUT std_logic;
+ rx_full_clk_ch3 : OUT std_logic;
+ rx_half_clk_ch3 : OUT std_logic;
+ rxdata_ch3 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch3 : OUT std_logic;
+ rx_disp_err_ch3 : OUT std_logic;
+ rx_cv_err_ch3 : OUT std_logic;
+ rx_los_low_ch3_s : OUT std_logic;
+ rx_cdr_lol_ch3_s : OUT std_logic;
+ refclk2fpga : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+ uut: mupix_serdes_400 PORT MAP(
+ hdinp_ch0 => hdinp_ch0,
+ hdinn_ch0 => hdinn_ch0,
+ rxiclk_ch0 => rxiclk_ch0,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
+ rxdata_ch0 => rxdata_ch0,
+ rx_k_ch0 => rx_k_ch0,
+ rx_disp_err_ch0 => rx_disp_err_ch0,
+ rx_cv_err_ch0 => rx_cv_err_ch0,
+ word_align_en_ch0_c => word_align_en_ch0_c,
+ rx_pwrup_ch0_c => rx_pwrup_ch0_c,
+ rx_los_low_ch0_s => rx_los_low_ch0_s,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
+ rx_div2_mode_ch0_c => rx_div2_mode_ch0_c,
+ hdinp_ch1 => hdinp_ch1,
+ hdinn_ch1 => hdinn_ch1,
+ rxiclk_ch1 => rxiclk_ch1,
+ rx_full_clk_ch1 => rx_full_clk_ch1,
+ rx_half_clk_ch1 => rx_half_clk_ch1,
+ fpga_rxrefclk_ch1 => fpga_rxrefclk_ch1,
+ rxdata_ch1 => rxdata_ch1,
+ rx_k_ch1 => rx_k_ch1,
+ rx_disp_err_ch1 => rx_disp_err_ch1,
+ rx_cv_err_ch1 => rx_cv_err_ch1,
+ word_align_en_ch1_c => word_align_en_ch1_c,
+ rx_pwrup_ch1_c => rx_pwrup_ch1_c,
+ rx_los_low_ch1_s => rx_los_low_ch1_s,
+ rx_cdr_lol_ch1_s => rx_cdr_lol_ch1_s,
+ rx_div2_mode_ch1_c => rx_div2_mode_ch1_c,
+ hdinp_ch2 => hdinp_ch2,
+ hdinn_ch2 => hdinn_ch2,
+ rxiclk_ch2 => rxiclk_ch2,
+ rx_full_clk_ch2 => rx_full_clk_ch2,
+ rx_half_clk_ch2 => rx_half_clk_ch2,
+ fpga_rxrefclk_ch2 => fpga_rxrefclk_ch2,
+ rxdata_ch2 => rxdata_ch2,
+ rx_k_ch2 => rx_k_ch2,
+ rx_disp_err_ch2 => rx_disp_err_ch2,
+ rx_cv_err_ch2 => rx_cv_err_ch2,
+ word_align_en_ch2_c => word_align_en_ch2_c,
+ rx_pwrup_ch2_c => rx_pwrup_ch2_c,
+ rx_los_low_ch2_s => rx_los_low_ch2_s,
+ rx_cdr_lol_ch2_s => rx_cdr_lol_ch2_s,
+ rx_div2_mode_ch2_c => rx_div2_mode_ch2_c,
+ hdinp_ch3 => hdinp_ch3,
+ hdinn_ch3 => hdinn_ch3,
+ rxiclk_ch3 => rxiclk_ch3,
+ rx_full_clk_ch3 => rx_full_clk_ch3,
+ rx_half_clk_ch3 => rx_half_clk_ch3,
+ fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
+ rxdata_ch3 => rxdata_ch3,
+ rx_k_ch3 => rx_k_ch3,
+ rx_disp_err_ch3 => rx_disp_err_ch3,
+ rx_cv_err_ch3 => rx_cv_err_ch3,
+ word_align_en_ch3_c => word_align_en_ch3_c,
+ rx_pwrup_ch3_c => rx_pwrup_ch3_c,
+ rx_los_low_ch3_s => rx_los_low_ch3_s,
+ rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
+ rx_div2_mode_ch3_c => rx_div2_mode_ch3_c,
+ fpga_txrefclk => fpga_txrefclk,
+ tx_sync_qd_c => tx_sync_qd_c,
+ refclk2fpga => refclk2fpga,
+ rst_n => rst_n,
+ serdes_rst_qd_c => serdes_rst_qd_c
+ );
+
+
+
+
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
--- CONFIG_FILE : String := "mupix_serdes_sim.txt";
+-- CONFIG_FILE : String := "mupix_serdes_400.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_CORE";
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-entity mupix_serdes_simrx_reset_sm is
+entity mupix_serdes_400rx_reset_sm is
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
rx_los_low_ch_s : in std_logic;
rx_pcs_rst_ch_c : out std_logic
);
-end mupix_serdes_simrx_reset_sm ;
+end mupix_serdes_400rx_reset_sm ;
-architecture rx_reset_sm_arch of mupix_serdes_simrx_reset_sm is
+architecture rx_reset_sm_arch of mupix_serdes_400rx_reset_sm is
type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
-entity mupix_serdes_sim is
- GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_sim.txt");
+entity mupix_serdes_400 is
+ GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_400.txt");
port (
------------------
-- CH0 --
rst_n : in std_logic;
serdes_rst_qd_c : in std_logic);
-end mupix_serdes_sim;
+end mupix_serdes_400;
-architecture mupix_serdes_sim_arch of mupix_serdes_sim is
+architecture mupix_serdes_400_arch of mupix_serdes_400 is
component VLO
port (
Z : out std_logic);
end component;
-component mupix_serdes_simrx_reset_sm
+component mupix_serdes_400rx_reset_sm
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
END IF;
END PROCESS;
-rx_reset_sm_ch0 : mupix_serdes_simrx_reset_sm
+rx_reset_sm_ch0 : mupix_serdes_400rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch1 : mupix_serdes_simrx_reset_sm
+rx_reset_sm_ch1 : mupix_serdes_400rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch2 : mupix_serdes_simrx_reset_sm
+rx_reset_sm_ch2 : mupix_serdes_400rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch3 : mupix_serdes_simrx_reset_sm
+rx_reset_sm_ch3 : mupix_serdes_400rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
wait;
END PROCESS;
--synopsys translate_on
-end mupix_serdes_sim_arch ;
+end mupix_serdes_400_arch ;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_serdes_600" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:41:29.788" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_serdes_600.lpc" type="lpc" modified="2018 08 02 15:41:27.000"/>
+ <File name="mupix_serdes_600.pp" type="pp" modified="2018 08 02 15:41:27.000"/>
+ <File name="mupix_serdes_600.sym" type="sym" modified="2018 08 02 15:41:27.000"/>
+ <File name="mupix_serdes_600.tft" type="tft" modified="2018 08 02 15:41:27.000"/>
+ <File name="mupix_serdes_600.txt" type="pcs_module" modified="2018 08 02 15:41:27.000"/>
+ <File name="mupix_serdes_600.vhd" type="top_level_vhdl" modified="2018 08 02 15:41:27.000"/>
+ </Package>
+</DiamondModule>
[Device]
Family=latticeecp3
PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
Package=FPBGA672
OperatingCondition=COM
Status=P
CoreStatus=Demo
CoreName=PCS
CoreRevision=8.2
-ModuleName=mupix_serdes
+ModuleName=mupix_serdes_600
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/11/2018
-Time=14:18:09
+Date=08/02/2018
+Time=15:41:27
[Parameters]
Verilog=0
_ldr1=DISABLED
_ldr2=DISABLED
_ldr3=DISABLED
-_datarange=1.25
+_datarange=0.6
_pll_txsrc=INTERNAL
_refclk_mult=10X
-_refclk_rate=125.0
+_refclk_rate=60.0
_tx_protocol0=DISABLED
_tx_protocol1=DISABLED
_tx_protocol2=DISABLED
_tx_fifo1=ENABLED
_tx_fifo2=ENABLED
_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=125.0
-_tx_ficlk_rate3=125.0
+_tx_ficlk_rate0=60.0
+_tx_ficlk_rate1=60.0
+_tx_ficlk_rate2=60.0
+_tx_ficlk_rate3=60.0
_pll_rxsrc0=INTERNAL
_pll_rxsrc1=INTERNAL
_pll_rxsrc2=INTERNAL
Multiplier1=
Multiplier2=
Multiplier3=
-_rx_datarange0=1.25
-_rx_datarange1=1.25
-_rx_datarange2=1.25
-_rx_datarange3=1.25
+_rx_datarange0=0.6
+_rx_datarange1=0.6
+_rx_datarange2=0.6
+_rx_datarange3=0.6
_rx_protocol0=G8B10B
_rx_protocol1=G8B10B
_rx_protocol2=G8B10B
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rx_data_rate3=FULL
-_rxrefclk_rate0=125.0
-_rxrefclk_rate1=125.0
-_rxrefclk_rate2=125.0
-_rxrefclk_rate3=125.0
+_rxrefclk_rate0=60.0
+_rxrefclk_rate1=60.0
+_rxrefclk_rate2=60.0
+_rxrefclk_rate3=60.0
_rx_data_width0=8
_rx_data_width1=8
_rx_data_width2=8
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
-_rx_ficlk_rate0=125.0
-_rx_ficlk_rate1=125.0
-_rx_ficlk_rate2=125.0
-_rx_ficlk_rate3=125.0
+_rx_ficlk_rate0=60.0
+_rx_ficlk_rate1=60.0
+_rx_ficlk_rate2=60.0
+_rx_ficlk_rate3=60.0
_tdrv_ch0=0
_tdrv_ch1=0
_tdrv_ch2=0
_rxwa1=ENABLED
_rxwa2=ENABLED
_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
+_ilsm0=DISABLED
+_ilsm1=DISABLED
+_ilsm2=DISABLED
+_ilsm3=DISABLED
_scomma0=K28P157
_scomma1=K28P157
_scomma2=K28P157
PARTrace3=0
[FilesGenerated]
-mupix_serdes.pp=pp
-mupix_serdes.tft=tft
-mupix_serdes.txt=pcs_module
-mupix_serdes.sym=sym
+mupix_serdes_600.pp=pp
+mupix_serdes_600.tft=tft
+mupix_serdes_600.txt=pcs_module
+mupix_serdes_600.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXONLY"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 60.0
+#define _ch0_rx_datarange "MEDLOW"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "60.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 60.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "DISABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXONLY"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 60.0
+#define _ch1_rx_datarange "MEDLOW"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "60.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 60.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "DISABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXONLY"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "ENABLED"
+#define _ch2_tx_ficlk_rate 60.0
+#define _ch2_rx_datarange "MEDLOW"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "60.0"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 60.0
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "AC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "DISABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXONLY"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 60.0
+#define _ch3_rx_datarange "MEDLOW"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "60.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 60.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "DISABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDLOW"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 60.0
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "ENABLED"
+#define _sci_ports "DISABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "ENABLED"
+#define _circuit_name mupix_serdes_600
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: Lattice Semiconductor Corporation
+ MODULE: mupix_serdes_600
+ DESIGN: mupix_serdes_600
+ FILENAME: mupix_serdes_600.readme
+ PROJECT: Unknown
+ VERSION: 2.0
+ This file is auto generated by the ispLEVER
+
+
+NOTE: This readme file has been provided to instantiate the interface
+netlist. Since this template contains synthesis attributes for precision that
+are crucial to the design flow, we recommend that you use this
+template in your FPGA design.
+entity chip is
+port (
+
+-- Add your FPGA design top level I/Os here
+
+
+-- ASIC side pins for PCSD. These pins must exist for the
+-- PCS core.
+ refclkp : in std_logic;
+ refclkn : in std_logic;
+ hdinp_ch0 : in std_logic;
+ hdinn_ch0 : in std_logic;
+ hdinp_ch1 : in std_logic;
+ hdinn_ch1 : in std_logic;
+ hdinp_ch2 : in std_logic;
+ hdinn_ch2 : in std_logic;
+ hdinp_ch3 : in std_logic;
+ hdinn_ch3 : in std_logic;
+
+ hdoutp_ch0 : out std_logic;
+ hdoutn_ch0 : out std_logic;
+ hdoutp_ch1 : out std_logic;
+ hdoutn_ch1 : out std_logic;
+ hdoutp_ch2 : out std_logic;
+ hdoutn_ch2 : out std_logic;
+ hdoutp_ch3 : out std_logic;
+ hdoutn_ch3 : out std_logic;
+
+
+);
+end chip;
+
+architecture chip_arch of chip is
+
+-- This defines all the high-speed ports. You may have to remove
+-- some of them depending on your design.
+attribute nopad : string;
+attribute nopad of
+ refclkp, refclkn,
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
+
+ COMPONENT mupix_serdes_600
+ PORT(
+ hdinp_ch0 : IN std_logic;
+ hdinn_ch0 : IN std_logic;
+ rxiclk_ch0 : IN std_logic;
+ fpga_rxrefclk_ch0 : IN std_logic;
+ word_align_en_ch0_c : IN std_logic;
+ rx_pwrup_ch0_c : IN std_logic;
+ rx_div2_mode_ch0_c : IN std_logic;
+ hdinp_ch1 : IN std_logic;
+ hdinn_ch1 : IN std_logic;
+ rxiclk_ch1 : IN std_logic;
+ fpga_rxrefclk_ch1 : IN std_logic;
+ word_align_en_ch1_c : IN std_logic;
+ rx_pwrup_ch1_c : IN std_logic;
+ rx_div2_mode_ch1_c : IN std_logic;
+ hdinp_ch2 : IN std_logic;
+ hdinn_ch2 : IN std_logic;
+ rxiclk_ch2 : IN std_logic;
+ fpga_rxrefclk_ch2 : IN std_logic;
+ word_align_en_ch2_c : IN std_logic;
+ rx_pwrup_ch2_c : IN std_logic;
+ rx_div2_mode_ch2_c : IN std_logic;
+ hdinp_ch3 : IN std_logic;
+ hdinn_ch3 : IN std_logic;
+ rxiclk_ch3 : IN std_logic;
+ fpga_rxrefclk_ch3 : IN std_logic;
+ word_align_en_ch3_c : IN std_logic;
+ rx_pwrup_ch3_c : IN std_logic;
+ rx_div2_mode_ch3_c : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_sync_qd_c : IN std_logic;
+ rst_n : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ rx_full_clk_ch0 : OUT std_logic;
+ rx_half_clk_ch0 : OUT std_logic;
+ rxdata_ch0 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch0 : OUT std_logic;
+ rx_disp_err_ch0 : OUT std_logic;
+ rx_cv_err_ch0 : OUT std_logic;
+ rx_los_low_ch0_s : OUT std_logic;
+ rx_cdr_lol_ch0_s : OUT std_logic;
+ rx_full_clk_ch1 : OUT std_logic;
+ rx_half_clk_ch1 : OUT std_logic;
+ rxdata_ch1 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch1 : OUT std_logic;
+ rx_disp_err_ch1 : OUT std_logic;
+ rx_cv_err_ch1 : OUT std_logic;
+ rx_los_low_ch1_s : OUT std_logic;
+ rx_cdr_lol_ch1_s : OUT std_logic;
+ rx_full_clk_ch2 : OUT std_logic;
+ rx_half_clk_ch2 : OUT std_logic;
+ rxdata_ch2 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch2 : OUT std_logic;
+ rx_disp_err_ch2 : OUT std_logic;
+ rx_cv_err_ch2 : OUT std_logic;
+ rx_los_low_ch2_s : OUT std_logic;
+ rx_cdr_lol_ch2_s : OUT std_logic;
+ rx_full_clk_ch3 : OUT std_logic;
+ rx_half_clk_ch3 : OUT std_logic;
+ rxdata_ch3 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch3 : OUT std_logic;
+ rx_disp_err_ch3 : OUT std_logic;
+ rx_cv_err_ch3 : OUT std_logic;
+ rx_los_low_ch3_s : OUT std_logic;
+ rx_cdr_lol_ch3_s : OUT std_logic;
+ refclk2fpga : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+ uut: mupix_serdes_600 PORT MAP(
+ hdinp_ch0 => hdinp_ch0,
+ hdinn_ch0 => hdinn_ch0,
+ rxiclk_ch0 => rxiclk_ch0,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
+ rxdata_ch0 => rxdata_ch0,
+ rx_k_ch0 => rx_k_ch0,
+ rx_disp_err_ch0 => rx_disp_err_ch0,
+ rx_cv_err_ch0 => rx_cv_err_ch0,
+ word_align_en_ch0_c => word_align_en_ch0_c,
+ rx_pwrup_ch0_c => rx_pwrup_ch0_c,
+ rx_los_low_ch0_s => rx_los_low_ch0_s,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
+ rx_div2_mode_ch0_c => rx_div2_mode_ch0_c,
+ hdinp_ch1 => hdinp_ch1,
+ hdinn_ch1 => hdinn_ch1,
+ rxiclk_ch1 => rxiclk_ch1,
+ rx_full_clk_ch1 => rx_full_clk_ch1,
+ rx_half_clk_ch1 => rx_half_clk_ch1,
+ fpga_rxrefclk_ch1 => fpga_rxrefclk_ch1,
+ rxdata_ch1 => rxdata_ch1,
+ rx_k_ch1 => rx_k_ch1,
+ rx_disp_err_ch1 => rx_disp_err_ch1,
+ rx_cv_err_ch1 => rx_cv_err_ch1,
+ word_align_en_ch1_c => word_align_en_ch1_c,
+ rx_pwrup_ch1_c => rx_pwrup_ch1_c,
+ rx_los_low_ch1_s => rx_los_low_ch1_s,
+ rx_cdr_lol_ch1_s => rx_cdr_lol_ch1_s,
+ rx_div2_mode_ch1_c => rx_div2_mode_ch1_c,
+ hdinp_ch2 => hdinp_ch2,
+ hdinn_ch2 => hdinn_ch2,
+ rxiclk_ch2 => rxiclk_ch2,
+ rx_full_clk_ch2 => rx_full_clk_ch2,
+ rx_half_clk_ch2 => rx_half_clk_ch2,
+ fpga_rxrefclk_ch2 => fpga_rxrefclk_ch2,
+ rxdata_ch2 => rxdata_ch2,
+ rx_k_ch2 => rx_k_ch2,
+ rx_disp_err_ch2 => rx_disp_err_ch2,
+ rx_cv_err_ch2 => rx_cv_err_ch2,
+ word_align_en_ch2_c => word_align_en_ch2_c,
+ rx_pwrup_ch2_c => rx_pwrup_ch2_c,
+ rx_los_low_ch2_s => rx_los_low_ch2_s,
+ rx_cdr_lol_ch2_s => rx_cdr_lol_ch2_s,
+ rx_div2_mode_ch2_c => rx_div2_mode_ch2_c,
+ hdinp_ch3 => hdinp_ch3,
+ hdinn_ch3 => hdinn_ch3,
+ rxiclk_ch3 => rxiclk_ch3,
+ rx_full_clk_ch3 => rx_full_clk_ch3,
+ rx_half_clk_ch3 => rx_half_clk_ch3,
+ fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
+ rxdata_ch3 => rxdata_ch3,
+ rx_k_ch3 => rx_k_ch3,
+ rx_disp_err_ch3 => rx_disp_err_ch3,
+ rx_cv_err_ch3 => rx_cv_err_ch3,
+ word_align_en_ch3_c => word_align_en_ch3_c,
+ rx_pwrup_ch3_c => rx_pwrup_ch3_c,
+ rx_los_low_ch3_s => rx_los_low_ch3_s,
+ rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
+ rx_div2_mode_ch3_c => rx_div2_mode_ch3_c,
+ fpga_txrefclk => fpga_txrefclk,
+ tx_sync_qd_c => tx_sync_qd_c,
+ refclk2fpga => refclk2fpga,
+ rst_n => rst_n,
+ serdes_rst_qd_c => serdes_rst_qd_c
+ );
+
+
+
+
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
CH2_CDR_SRC "REFCLK_CORE"
CH3_CDR_SRC "REFCLK_CORE"
PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MED"
-CH0_RX_DATARATE_RANGE "MED"
-CH1_RX_DATARATE_RANGE "MED"
-CH2_RX_DATARATE_RANGE "MED"
-CH3_RX_DATARATE_RANGE "MED"
+TX_DATARATE_RANGE "MEDLOW"
+CH0_RX_DATARATE_RANGE "MEDLOW"
+CH1_RX_DATARATE_RANGE "MEDLOW"
+CH2_RX_DATARATE_RANGE "MEDLOW"
+CH3_RX_DATARATE_RANGE "MEDLOW"
REFCK_MULT "10X"
-#REFCLK_RATE 125.0
+#REFCLK_RATE 60.0
CH0_RX_DATA_RATE "FULL"
CH1_RX_DATA_RATE "FULL"
CH2_RX_DATA_RATE "FULL"
CH1_TDRV "0"
CH2_TDRV "0"
CH3_TDRV "0"
-#CH0_TX_FICLK_RATE 125.0
-#CH1_TX_FICLK_RATE 125.0
-#CH2_TX_FICLK_RATE 125.0
-#CH3_TX_FICLK_RATE 125.0
-#CH0_RXREFCLK_RATE "125.0"
-#CH1_RXREFCLK_RATE "125.0"
-#CH2_RXREFCLK_RATE "125.0"
-#CH3_RXREFCLK_RATE "125.0"
-#CH0_RX_FICLK_RATE 125.0
-#CH1_RX_FICLK_RATE 125.0
-#CH2_RX_FICLK_RATE 125.0
-#CH3_RX_FICLK_RATE 125.0
+#CH0_TX_FICLK_RATE 60.0
+#CH1_TX_FICLK_RATE 60.0
+#CH2_TX_FICLK_RATE 60.0
+#CH3_TX_FICLK_RATE 60.0
+#CH0_RXREFCLK_RATE "60.0"
+#CH1_RXREFCLK_RATE "60.0"
+#CH2_RXREFCLK_RATE "60.0"
+#CH3_RXREFCLK_RATE "60.0"
+#CH0_RX_FICLK_RATE 60.0
+#CH1_RX_FICLK_RATE 60.0
+#CH2_RX_FICLK_RATE 60.0
+#CH3_RX_FICLK_RATE 60.0
CH0_TX_PRE "DISABLED"
CH1_TX_PRE "DISABLED"
CH2_TX_PRE "DISABLED"
CH1_RXWA "ENABLED"
CH2_RXWA "ENABLED"
CH3_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH1_ILSM "ENABLED"
-CH2_ILSM "ENABLED"
-CH3_ILSM "ENABLED"
+CH0_ILSM "DISABLED"
+CH1_ILSM "DISABLED"
+CH2_ILSM "DISABLED"
+CH3_ILSM "DISABLED"
CH0_CTC "DISABLED"
CH1_CTC "DISABLED"
CH2_CTC "DISABLED"
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
--- CONFIG_FILE : String := "mupix_serdes.txt";
+-- CONFIG_FILE : String := "mupix_serdes_600.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_CORE";
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-entity mupix_serdesrx_reset_sm is
+entity mupix_serdes_600rx_reset_sm is
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
rx_los_low_ch_s : in std_logic;
rx_pcs_rst_ch_c : out std_logic
);
-end mupix_serdesrx_reset_sm ;
+end mupix_serdes_600rx_reset_sm ;
-architecture rx_reset_sm_arch of mupix_serdesrx_reset_sm is
+architecture rx_reset_sm_arch of mupix_serdes_600rx_reset_sm is
type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
-entity mupix_serdes is
- GENERIC (USER_CONFIG_FILE : String := "mupix_serdes.txt");
+entity mupix_serdes_600 is
+ GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_600.txt");
port (
------------------
-- CH0 --
rx_k_ch0 : out std_logic;
rx_disp_err_ch0 : out std_logic;
rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
rx_pwrup_ch0_c : in std_logic;
rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
rx_cdr_lol_ch0_s : out std_logic;
rx_div2_mode_ch0_c : in std_logic;
-- CH1 --
rx_k_ch1 : out std_logic;
rx_disp_err_ch1 : out std_logic;
rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
rx_pwrup_ch1_c : in std_logic;
rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
rx_cdr_lol_ch1_s : out std_logic;
rx_div2_mode_ch1_c : in std_logic;
-- CH2 --
rx_k_ch2 : out std_logic;
rx_disp_err_ch2 : out std_logic;
rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
rx_pwrup_ch2_c : in std_logic;
rx_los_low_ch2_s : out std_logic;
- lsm_status_ch2_s : out std_logic;
rx_cdr_lol_ch2_s : out std_logic;
rx_div2_mode_ch2_c : in std_logic;
-- CH3 --
rx_k_ch3 : out std_logic;
rx_disp_err_ch3 : out std_logic;
rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
rx_pwrup_ch3_c : in std_logic;
rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
rx_cdr_lol_ch3_s : out std_logic;
rx_div2_mode_ch3_c : in std_logic;
---- Miscillaneous ports
rst_n : in std_logic;
serdes_rst_qd_c : in std_logic);
-end mupix_serdes;
+end mupix_serdes_600;
-architecture mupix_serdes_arch of mupix_serdes is
+architecture mupix_serdes_600_arch of mupix_serdes_600 is
component VLO
port (
Z : out std_logic);
end component;
-component mupix_serdesrx_reset_sm
+component mupix_serdes_600rx_reset_sm
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
attribute CH3_CDR_SRC: string;
attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "60.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "30.0000";
attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "60.0";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
FFC_PCIE_CT_0 => fpsc_vlo,
FFC_PCI_DET_EN_0 => fpsc_vlo,
FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => word_align_en_ch0_c,
FFC_EI_EN_0 => fpsc_vlo,
FFC_LANE_TX_RST_0 => fpsc_vlo,
FFC_TXPWDNB_0 => fpsc_vlo,
FFS_RLOS_HI_0 => open,
FFS_PCIE_CON_0 => open,
FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_LS_SYNC_STATUS_0 => open,
FFS_CC_OVERRUN_0 => open,
FFS_CC_UNDERRUN_0 => open,
FFS_SKP_ADDED_0 => open,
FFC_PCIE_CT_1 => fpsc_vlo,
FFC_PCI_DET_EN_1 => fpsc_vlo,
FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => word_align_en_ch1_c,
FFC_EI_EN_1 => fpsc_vlo,
FFC_LANE_TX_RST_1 => fpsc_vlo,
FFC_TXPWDNB_1 => fpsc_vlo,
FFS_RLOS_HI_1 => open,
FFS_PCIE_CON_1 => open,
FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_LS_SYNC_STATUS_1 => open,
FFS_CC_OVERRUN_1 => open,
FFS_CC_UNDERRUN_1 => open,
FFS_SKP_ADDED_1 => open,
FFC_PCIE_CT_2 => fpsc_vlo,
FFC_PCI_DET_EN_2 => fpsc_vlo,
FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => word_align_en_ch2_c,
FFC_EI_EN_2 => fpsc_vlo,
FFC_LANE_TX_RST_2 => fpsc_vlo,
FFC_TXPWDNB_2 => fpsc_vlo,
FFS_RLOS_HI_2 => open,
FFS_PCIE_CON_2 => open,
FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+ FFS_LS_SYNC_STATUS_2 => open,
FFS_CC_OVERRUN_2 => open,
FFS_CC_UNDERRUN_2 => open,
FFS_SKP_ADDED_2 => open,
FFC_PCIE_CT_3 => fpsc_vlo,
FFC_PCI_DET_EN_3 => fpsc_vlo,
FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => word_align_en_ch3_c,
FFC_EI_EN_3 => fpsc_vlo,
FFC_LANE_TX_RST_3 => fpsc_vlo,
FFC_TXPWDNB_3 => fpsc_vlo,
FFS_RLOS_HI_3 => open,
FFS_PCIE_CON_3 => open,
FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_LS_SYNC_STATUS_3 => open,
FFS_CC_OVERRUN_3 => open,
FFS_CC_UNDERRUN_3 => open,
FFS_SKP_ADDED_3 => open,
END IF;
END PROCESS;
-rx_reset_sm_ch0 : mupix_serdesrx_reset_sm
+rx_reset_sm_ch0 : mupix_serdes_600rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch1 : mupix_serdesrx_reset_sm
+rx_reset_sm_ch1 : mupix_serdes_600rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch2 : mupix_serdesrx_reset_sm
+rx_reset_sm_ch2 : mupix_serdes_600rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
END IF;
END PROCESS;
-rx_reset_sm_ch3 : mupix_serdesrx_reset_sm
+rx_reset_sm_ch3 : mupix_serdes_600rx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
wait;
END PROCESS;
--synopsys translate_on
-end mupix_serdes_arch ;
+end mupix_serdes_600_arch ;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="mupix_serdes_800" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 02 15:09:33.566" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="mupix_serdes_800.lpc" type="lpc" modified="2018 08 02 15:09:31.000"/>
+ <File name="mupix_serdes_800.pp" type="pp" modified="2018 08 02 15:09:31.000"/>
+ <File name="mupix_serdes_800.sym" type="sym" modified="2018 08 02 15:09:32.000"/>
+ <File name="mupix_serdes_800.tft" type="tft" modified="2018 08 02 15:09:31.000"/>
+ <File name="mupix_serdes_800.txt" type="pcs_module" modified="2018 08 02 15:09:31.000"/>
+ <File name="mupix_serdes_800.vhd" type="top_level_vhdl" modified="2018 08 02 15:09:31.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=mupix_serdes_800
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/02/2018
+Time=15:09:31
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXONLY
+_mode1=RXONLY
+_mode2=RXONLY
+_mode3=RXONLY
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=0.8
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=80.0
+_tx_protocol0=DISABLED
+_tx_protocol1=DISABLED
+_tx_protocol2=DISABLED
+_tx_protocol3=DISABLED
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=80.0
+_tx_ficlk_rate1=80.0
+_tx_ficlk_rate2=80.0
+_tx_ficlk_rate3=80.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=0.8
+_rx_datarange1=0.8
+_rx_datarange2=0.8
+_rx_datarange3=0.8
+_rx_protocol0=G8B10B
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=80.0
+_rxrefclk_rate1=80.0
+_rxrefclk_rate2=80.0
+_rxrefclk_rate3=80.0
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=80.0
+_rx_ficlk_rate1=80.0
+_rx_ficlk_rate2=80.0
+_rx_ficlk_rate3=80.0
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=AC
+_rx_dcc1=AC
+_rx_dcc2=AC
+_rx_dcc3=AC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=DISABLED
+_ilsm1=DISABLED
+_ilsm2=DISABLED
+_ilsm3=DISABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=00
+_k01=00
+_k02=00
+_k03=00
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00000000
+_byten01=00000000
+_byten02=00000000
+_byten03=00000000
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=ENABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=DISABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+mupix_serdes_800.pp=pp
+mupix_serdes_800.tft=tft
+mupix_serdes_800.txt=pcs_module
+mupix_serdes_800.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXONLY"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 80.0
+#define _ch0_rx_datarange "MEDLOW"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "80.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 80.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "DISABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXONLY"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 80.0
+#define _ch1_rx_datarange "MEDLOW"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "80.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 80.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "DISABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXONLY"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "ENABLED"
+#define _ch2_tx_ficlk_rate 80.0
+#define _ch2_rx_datarange "MEDLOW"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "80.0"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 80.0
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "AC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "DISABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXONLY"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 80.0
+#define _ch3_rx_datarange "MEDLOW"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "80.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 80.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "DISABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDLOW"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 80.0
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "ENABLED"
+#define _sci_ports "DISABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "ENABLED"
+#define _circuit_name mupix_serdes_800
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: Lattice Semiconductor Corporation
+ MODULE: mupix_serdes_800
+ DESIGN: mupix_serdes_800
+ FILENAME: mupix_serdes_800.readme
+ PROJECT: Unknown
+ VERSION: 2.0
+ This file is auto generated by the ispLEVER
+
+
+NOTE: This readme file has been provided to instantiate the interface
+netlist. Since this template contains synthesis attributes for precision that
+are crucial to the design flow, we recommend that you use this
+template in your FPGA design.
+entity chip is
+port (
+
+-- Add your FPGA design top level I/Os here
+
+
+-- ASIC side pins for PCSD. These pins must exist for the
+-- PCS core.
+ refclkp : in std_logic;
+ refclkn : in std_logic;
+ hdinp_ch0 : in std_logic;
+ hdinn_ch0 : in std_logic;
+ hdinp_ch1 : in std_logic;
+ hdinn_ch1 : in std_logic;
+ hdinp_ch2 : in std_logic;
+ hdinn_ch2 : in std_logic;
+ hdinp_ch3 : in std_logic;
+ hdinn_ch3 : in std_logic;
+
+ hdoutp_ch0 : out std_logic;
+ hdoutn_ch0 : out std_logic;
+ hdoutp_ch1 : out std_logic;
+ hdoutn_ch1 : out std_logic;
+ hdoutp_ch2 : out std_logic;
+ hdoutn_ch2 : out std_logic;
+ hdoutp_ch3 : out std_logic;
+ hdoutn_ch3 : out std_logic;
+
+
+);
+end chip;
+
+architecture chip_arch of chip is
+
+-- This defines all the high-speed ports. You may have to remove
+-- some of them depending on your design.
+attribute nopad : string;
+attribute nopad of
+ refclkp, refclkn,
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";
+
+ COMPONENT mupix_serdes_800
+ PORT(
+ hdinp_ch0 : IN std_logic;
+ hdinn_ch0 : IN std_logic;
+ rxiclk_ch0 : IN std_logic;
+ fpga_rxrefclk_ch0 : IN std_logic;
+ word_align_en_ch0_c : IN std_logic;
+ rx_pwrup_ch0_c : IN std_logic;
+ rx_div2_mode_ch0_c : IN std_logic;
+ hdinp_ch1 : IN std_logic;
+ hdinn_ch1 : IN std_logic;
+ rxiclk_ch1 : IN std_logic;
+ fpga_rxrefclk_ch1 : IN std_logic;
+ word_align_en_ch1_c : IN std_logic;
+ rx_pwrup_ch1_c : IN std_logic;
+ rx_div2_mode_ch1_c : IN std_logic;
+ hdinp_ch2 : IN std_logic;
+ hdinn_ch2 : IN std_logic;
+ rxiclk_ch2 : IN std_logic;
+ fpga_rxrefclk_ch2 : IN std_logic;
+ word_align_en_ch2_c : IN std_logic;
+ rx_pwrup_ch2_c : IN std_logic;
+ rx_div2_mode_ch2_c : IN std_logic;
+ hdinp_ch3 : IN std_logic;
+ hdinn_ch3 : IN std_logic;
+ rxiclk_ch3 : IN std_logic;
+ fpga_rxrefclk_ch3 : IN std_logic;
+ word_align_en_ch3_c : IN std_logic;
+ rx_pwrup_ch3_c : IN std_logic;
+ rx_div2_mode_ch3_c : IN std_logic;
+ fpga_txrefclk : IN std_logic;
+ tx_sync_qd_c : IN std_logic;
+ rst_n : IN std_logic;
+ serdes_rst_qd_c : IN std_logic;
+ rx_full_clk_ch0 : OUT std_logic;
+ rx_half_clk_ch0 : OUT std_logic;
+ rxdata_ch0 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch0 : OUT std_logic;
+ rx_disp_err_ch0 : OUT std_logic;
+ rx_cv_err_ch0 : OUT std_logic;
+ rx_los_low_ch0_s : OUT std_logic;
+ rx_cdr_lol_ch0_s : OUT std_logic;
+ rx_full_clk_ch1 : OUT std_logic;
+ rx_half_clk_ch1 : OUT std_logic;
+ rxdata_ch1 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch1 : OUT std_logic;
+ rx_disp_err_ch1 : OUT std_logic;
+ rx_cv_err_ch1 : OUT std_logic;
+ rx_los_low_ch1_s : OUT std_logic;
+ rx_cdr_lol_ch1_s : OUT std_logic;
+ rx_full_clk_ch2 : OUT std_logic;
+ rx_half_clk_ch2 : OUT std_logic;
+ rxdata_ch2 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch2 : OUT std_logic;
+ rx_disp_err_ch2 : OUT std_logic;
+ rx_cv_err_ch2 : OUT std_logic;
+ rx_los_low_ch2_s : OUT std_logic;
+ rx_cdr_lol_ch2_s : OUT std_logic;
+ rx_full_clk_ch3 : OUT std_logic;
+ rx_half_clk_ch3 : OUT std_logic;
+ rxdata_ch3 : OUT std_logic_vector(7 downto 0);
+ rx_k_ch3 : OUT std_logic;
+ rx_disp_err_ch3 : OUT std_logic;
+ rx_cv_err_ch3 : OUT std_logic;
+ rx_los_low_ch3_s : OUT std_logic;
+ rx_cdr_lol_ch3_s : OUT std_logic;
+ refclk2fpga : OUT std_logic
+ );
+ END COMPONENT;
+
+
+
+ uut: mupix_serdes_800 PORT MAP(
+ hdinp_ch0 => hdinp_ch0,
+ hdinn_ch0 => hdinn_ch0,
+ rxiclk_ch0 => rxiclk_ch0,
+ rx_full_clk_ch0 => rx_full_clk_ch0,
+ rx_half_clk_ch0 => rx_half_clk_ch0,
+ fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0,
+ rxdata_ch0 => rxdata_ch0,
+ rx_k_ch0 => rx_k_ch0,
+ rx_disp_err_ch0 => rx_disp_err_ch0,
+ rx_cv_err_ch0 => rx_cv_err_ch0,
+ word_align_en_ch0_c => word_align_en_ch0_c,
+ rx_pwrup_ch0_c => rx_pwrup_ch0_c,
+ rx_los_low_ch0_s => rx_los_low_ch0_s,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s,
+ rx_div2_mode_ch0_c => rx_div2_mode_ch0_c,
+ hdinp_ch1 => hdinp_ch1,
+ hdinn_ch1 => hdinn_ch1,
+ rxiclk_ch1 => rxiclk_ch1,
+ rx_full_clk_ch1 => rx_full_clk_ch1,
+ rx_half_clk_ch1 => rx_half_clk_ch1,
+ fpga_rxrefclk_ch1 => fpga_rxrefclk_ch1,
+ rxdata_ch1 => rxdata_ch1,
+ rx_k_ch1 => rx_k_ch1,
+ rx_disp_err_ch1 => rx_disp_err_ch1,
+ rx_cv_err_ch1 => rx_cv_err_ch1,
+ word_align_en_ch1_c => word_align_en_ch1_c,
+ rx_pwrup_ch1_c => rx_pwrup_ch1_c,
+ rx_los_low_ch1_s => rx_los_low_ch1_s,
+ rx_cdr_lol_ch1_s => rx_cdr_lol_ch1_s,
+ rx_div2_mode_ch1_c => rx_div2_mode_ch1_c,
+ hdinp_ch2 => hdinp_ch2,
+ hdinn_ch2 => hdinn_ch2,
+ rxiclk_ch2 => rxiclk_ch2,
+ rx_full_clk_ch2 => rx_full_clk_ch2,
+ rx_half_clk_ch2 => rx_half_clk_ch2,
+ fpga_rxrefclk_ch2 => fpga_rxrefclk_ch2,
+ rxdata_ch2 => rxdata_ch2,
+ rx_k_ch2 => rx_k_ch2,
+ rx_disp_err_ch2 => rx_disp_err_ch2,
+ rx_cv_err_ch2 => rx_cv_err_ch2,
+ word_align_en_ch2_c => word_align_en_ch2_c,
+ rx_pwrup_ch2_c => rx_pwrup_ch2_c,
+ rx_los_low_ch2_s => rx_los_low_ch2_s,
+ rx_cdr_lol_ch2_s => rx_cdr_lol_ch2_s,
+ rx_div2_mode_ch2_c => rx_div2_mode_ch2_c,
+ hdinp_ch3 => hdinp_ch3,
+ hdinn_ch3 => hdinn_ch3,
+ rxiclk_ch3 => rxiclk_ch3,
+ rx_full_clk_ch3 => rx_full_clk_ch3,
+ rx_half_clk_ch3 => rx_half_clk_ch3,
+ fpga_rxrefclk_ch3 => fpga_rxrefclk_ch3,
+ rxdata_ch3 => rxdata_ch3,
+ rx_k_ch3 => rx_k_ch3,
+ rx_disp_err_ch3 => rx_disp_err_ch3,
+ rx_cv_err_ch3 => rx_cv_err_ch3,
+ word_align_en_ch3_c => word_align_en_ch3_c,
+ rx_pwrup_ch3_c => rx_pwrup_ch3_c,
+ rx_los_low_ch3_s => rx_los_low_ch3_s,
+ rx_cdr_lol_ch3_s => rx_cdr_lol_ch3_s,
+ rx_div2_mode_ch3_c => rx_div2_mode_ch3_c,
+ fpga_txrefclk => fpga_txrefclk,
+ tx_sync_qd_c => tx_sync_qd_c,
+ refclk2fpga => refclk2fpga,
+ rst_n => rst_n,
+ serdes_rst_qd_c => serdes_rst_qd_c
+ );
+
+
+
+
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL "G8B10B"
+CH1_PROTOCOL "G8B10B"
+CH2_PROTOCOL "G8B10B"
+CH3_PROTOCOL "G8B10B"
+CH0_MODE "RXONLY"
+CH1_MODE "RXONLY"
+CH2_MODE "RXONLY"
+CH3_MODE "RXONLY"
+CH0_CDR_SRC "REFCLK_CORE"
+CH1_CDR_SRC "REFCLK_CORE"
+CH2_CDR_SRC "REFCLK_CORE"
+CH3_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDLOW"
+CH0_RX_DATARATE_RANGE "MEDLOW"
+CH1_RX_DATARATE_RANGE "MEDLOW"
+CH2_RX_DATARATE_RANGE "MEDLOW"
+CH3_RX_DATARATE_RANGE "MEDLOW"
+REFCK_MULT "10X"
+#REFCLK_RATE 80.0
+CH0_RX_DATA_RATE "FULL"
+CH1_RX_DATA_RATE "FULL"
+CH2_RX_DATA_RATE "FULL"
+CH3_RX_DATA_RATE "FULL"
+CH0_TX_DATA_RATE "FULL"
+CH1_TX_DATA_RATE "FULL"
+CH2_TX_DATA_RATE "FULL"
+CH3_TX_DATA_RATE "FULL"
+CH0_TX_DATA_WIDTH "8"
+CH1_TX_DATA_WIDTH "8"
+CH2_TX_DATA_WIDTH "8"
+CH3_TX_DATA_WIDTH "8"
+CH0_RX_DATA_WIDTH "8"
+CH1_RX_DATA_WIDTH "8"
+CH2_RX_DATA_WIDTH "8"
+CH3_RX_DATA_WIDTH "8"
+CH0_TX_FIFO "ENABLED"
+CH1_TX_FIFO "ENABLED"
+CH2_TX_FIFO "ENABLED"
+CH3_TX_FIFO "ENABLED"
+CH0_RX_FIFO "ENABLED"
+CH1_RX_FIFO "ENABLED"
+CH2_RX_FIFO "ENABLED"
+CH3_RX_FIFO "ENABLED"
+CH0_TDRV "0"
+CH1_TDRV "0"
+CH2_TDRV "0"
+CH3_TDRV "0"
+#CH0_TX_FICLK_RATE 80.0
+#CH1_TX_FICLK_RATE 80.0
+#CH2_TX_FICLK_RATE 80.0
+#CH3_TX_FICLK_RATE 80.0
+#CH0_RXREFCLK_RATE "80.0"
+#CH1_RXREFCLK_RATE "80.0"
+#CH2_RXREFCLK_RATE "80.0"
+#CH3_RXREFCLK_RATE "80.0"
+#CH0_RX_FICLK_RATE 80.0
+#CH1_RX_FICLK_RATE 80.0
+#CH2_RX_FICLK_RATE 80.0
+#CH3_RX_FICLK_RATE 80.0
+CH0_TX_PRE "DISABLED"
+CH1_TX_PRE "DISABLED"
+CH2_TX_PRE "DISABLED"
+CH3_TX_PRE "DISABLED"
+CH0_RTERM_TX "50"
+CH1_RTERM_TX "50"
+CH2_RTERM_TX "50"
+CH3_RTERM_TX "50"
+CH0_RX_EQ "DISABLED"
+CH1_RX_EQ "DISABLED"
+CH2_RX_EQ "DISABLED"
+CH3_RX_EQ "DISABLED"
+CH0_RTERM_RX "50"
+CH1_RTERM_RX "50"
+CH2_RTERM_RX "50"
+CH3_RTERM_RX "50"
+CH0_RX_DCC "AC"
+CH1_RX_DCC "AC"
+CH2_RX_DCC "AC"
+CH3_RX_DCC "AC"
+CH0_LOS_THRESHOLD_LO "2"
+CH1_LOS_THRESHOLD_LO "2"
+CH2_LOS_THRESHOLD_LO "2"
+CH3_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH0_TX_SB "DISABLED"
+CH1_TX_SB "DISABLED"
+CH2_TX_SB "DISABLED"
+CH3_TX_SB "DISABLED"
+CH0_RX_SB "DISABLED"
+CH1_RX_SB "DISABLED"
+CH2_RX_SB "DISABLED"
+CH3_RX_SB "DISABLED"
+CH0_TX_8B10B "ENABLED"
+CH1_TX_8B10B "ENABLED"
+CH2_TX_8B10B "ENABLED"
+CH3_TX_8B10B "ENABLED"
+CH0_RX_8B10B "ENABLED"
+CH1_RX_8B10B "ENABLED"
+CH2_RX_8B10B "ENABLED"
+CH3_RX_8B10B "ENABLED"
+CH0_COMMA_A "1100000101"
+CH1_COMMA_A "1100000101"
+CH2_COMMA_A "1100000101"
+CH3_COMMA_A "1100000101"
+CH0_COMMA_B "0011111010"
+CH1_COMMA_B "0011111010"
+CH2_COMMA_B "0011111010"
+CH3_COMMA_B "0011111010"
+CH0_COMMA_M "1111111100"
+CH1_COMMA_M "1111111100"
+CH2_COMMA_M "1111111100"
+CH3_COMMA_M "1111111100"
+CH0_RXWA "ENABLED"
+CH1_RXWA "ENABLED"
+CH2_RXWA "ENABLED"
+CH3_RXWA "ENABLED"
+CH0_ILSM "DISABLED"
+CH1_ILSM "DISABLED"
+CH2_ILSM "DISABLED"
+CH3_ILSM "DISABLED"
+CH0_CTC "DISABLED"
+CH1_CTC "DISABLED"
+CH2_CTC "DISABLED"
+CH3_CTC "DISABLED"
+CH0_CC_MATCH4 "0000000000"
+CH1_CC_MATCH4 "0000000000"
+CH2_CC_MATCH4 "0000000000"
+CH3_CC_MATCH4 "0000000000"
+CH0_CC_MATCH_MODE "1"
+CH1_CC_MATCH_MODE "1"
+CH2_CC_MATCH_MODE "1"
+CH3_CC_MATCH_MODE "1"
+CH0_CC_MIN_IPG "3"
+CH1_CC_MIN_IPG "3"
+CH2_CC_MIN_IPG "3"
+CH3_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH0_SSLB "DISABLED"
+CH1_SSLB "DISABLED"
+CH2_SSLB "DISABLED"
+CH3_SSLB "DISABLED"
+CH0_SPLBPORTS "DISABLED"
+CH1_SPLBPORTS "DISABLED"
+CH2_SPLBPORTS "DISABLED"
+CH3_SPLBPORTS "DISABLED"
+CH0_PCSLBPORTS "DISABLED"
+CH1_PCSLBPORTS "DISABLED"
+CH2_PCSLBPORTS "DISABLED"
+CH3_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "ENABLED"
+
+
--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "mupix_serdes_800.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+--THIS MODULE IS INSTANTIATED PER RX CHANNEL
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity mupix_serdes_800rx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end mupix_serdes_800rx_reset_sm ;
+
+architecture rx_reset_sm_arch of mupix_serdes_800rx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int: std_logic;
+signal rx_los_low_int: std_logic;
+signal plol_los_int: std_logic;
+signal rx_lol_los : std_logic;
+signal rx_lol_los_int: std_logic;
+signal rx_lol_los_del: std_logic;
+signal rx_pcs_rst_ch_c_int: std_logic;
+signal rx_serdes_rst_ch_c_int: std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(1 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2 : std_logic;
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= WAIT_FOR_PLOL;
+ rx_lol_los_int <= '1';
+ rx_lol_los_del <= '1';
+ tx_pll_lol_qd_s_int <= '1';
+ rx_pcs_rst_ch_c <= '1';
+ rx_serdes_rst_ch_c <= '0';
+ rx_los_low_int <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ rx_lol_los_del <= rx_lol_los;
+ rx_lol_los_int <= rx_lol_los_del;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+ rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+ rx_los_low_int <= rx_los_low_ch_s;
+ end if;
+ end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "00";
+ TIMER1 <= '0';
+ else
+ if counter1(1) = '1' then
+ TIMER1 <='1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+ when WAIT_FOR_PLOL =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
+ ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
+ else
+ ns <= RX_SERDES_RESET;
+ end if;
+
+ when RX_SERDES_RESET =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+
+ when WAIT_FOR_TIMER1 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_LOL_LOS;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_LOL_LOS =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
+ if TIMER2 = '1' then
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+ else
+ ns <= CHECK_LOL_LOS; --RESET TIMER2
+ end if;
+
+ when NORMAL =>
+ rx_pcs_rst_ch_c_int <= '0';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= WAIT_FOR_PLOL;
+
+ end case;
+
+end process;
+
+
+end rx_reset_sm_arch;
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity mupix_serdes_800 is
+ GENERIC (USER_CONFIG_FILE : String := "mupix_serdes_800.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ word_align_en_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ word_align_en_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ word_align_en_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ word_align_en_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end mupix_serdes_800;
+
+
+architecture mupix_serdes_800_arch of mupix_serdes_800 is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+component mupix_serdes_800rx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end component ;
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH0_CDR_SRC: string;
+ attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH2_CDR_SRC: string;
+ attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "80.0000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "40.0000";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "80.0";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+signal rx_serdes_rst_ch0_c : std_logic;
+signal rx_serdes_rst_ch1_c : std_logic;
+signal rx_serdes_rst_ch2_c : std_logic;
+signal rx_serdes_rst_ch3_c : std_logic;
+signal rx_pcs_rst_ch0_c : std_logic;
+signal rx_pcs_rst_ch1_c : std_logic;
+signal rx_pcs_rst_ch2_c : std_logic;
+signal rx_pcs_rst_ch3_c : std_logic;
+
+-- reset sequence for rx
+signal refclkdiv2_rx_ch0 : std_logic;
+signal refclkdiv2_rx_ch1 : std_logic;
+signal refclkdiv2_rx_ch2 : std_logic;
+signal refclkdiv2_rx_ch3 : std_logic;
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH0_CDR_SRC => "REFCLK_CORE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH2_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => hdinp_ch0,
+ HDINN0 => hdinn_ch0,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => rx_full_clk_ch0,
+ FF_RX_H_CLK_0 => rx_half_clk_ch0,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => rxdata_ch0(0),
+ FF_RX_D_0_1 => rxdata_ch0(1),
+ FF_RX_D_0_2 => rxdata_ch0(2),
+ FF_RX_D_0_3 => rxdata_ch0(3),
+ FF_RX_D_0_4 => rxdata_ch0(4),
+ FF_RX_D_0_5 => rxdata_ch0(5),
+ FF_RX_D_0_6 => rxdata_ch0(6),
+ FF_RX_D_0_7 => rxdata_ch0(7),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => word_align_en_ch0_c,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1,
+ FF_RX_D_1_9 => rx_disp_err_ch1,
+ FF_RX_D_1_10 => rx_cv_err_ch1,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => word_align_en_ch1_c,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => hdinp_ch2,
+ HDINN2 => hdinn_ch2,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => rxiclk_ch2,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => rx_full_clk_ch2,
+ FF_RX_H_CLK_2 => rx_half_clk_ch2,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => rxdata_ch2(0),
+ FF_RX_D_2_1 => rxdata_ch2(1),
+ FF_RX_D_2_2 => rxdata_ch2(2),
+ FF_RX_D_2_3 => rxdata_ch2(3),
+ FF_RX_D_2_4 => rxdata_ch2(4),
+ FF_RX_D_2_5 => rxdata_ch2(5),
+ FF_RX_D_2_6 => rxdata_ch2(6),
+ FF_RX_D_2_7 => rxdata_ch2(7),
+ FF_RX_D_2_8 => rx_k_ch2,
+ FF_RX_D_2_9 => rx_disp_err_ch2,
+ FF_RX_D_2_10 => rx_cv_err_ch2,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => rx_serdes_rst_ch2_c,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => word_align_en_ch2_c,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+ FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+ FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => rxiclk_ch3,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => word_align_en_ch3_c,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => open,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => fpsc_vlo,
+ SCIWDATA6 => fpsc_vlo,
+ SCIWDATA5 => fpsc_vlo,
+ SCIWDATA4 => fpsc_vlo,
+ SCIWDATA3 => fpsc_vlo,
+ SCIWDATA2 => fpsc_vlo,
+ SCIWDATA1 => fpsc_vlo,
+ SCIWDATA0 => fpsc_vlo,
+ SCIADDR5 => fpsc_vlo,
+ SCIADDR4 => fpsc_vlo,
+ SCIADDR3 => fpsc_vlo,
+ SCIADDR2 => fpsc_vlo,
+ SCIADDR1 => fpsc_vlo,
+ SCIADDR0 => fpsc_vlo,
+ SCIRDATA7 => open,
+ SCIRDATA6 => open,
+ SCIRDATA5 => open,
+ SCIRDATA4 => open,
+ SCIRDATA3 => open,
+ SCIRDATA2 => open,
+ SCIRDATA1 => open,
+ SCIRDATA0 => open,
+ SCIENAUX => fpsc_vlo,
+ SCISELAUX => fpsc_vlo,
+ SCIRD => fpsc_vlo,
+ SCIWSTN => fpsc_vlo,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => fpsc_vlo,
+ FFC_TRST => fpsc_vlo,
+ FFS_PLOL => open,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+-- reset sequence for rx
+
+ P1 : PROCESS(fpga_rxrefclk_ch0, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch0 <= '0';
+ ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN
+ refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch0 : mupix_serdes_800rx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch0,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig,
+ rx_los_low_ch_s => rx_los_low_ch0_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c);
+
+ P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch1 <= '0';
+ ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
+ refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch1 : mupix_serdes_800rx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch1,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
+ rx_los_low_ch_s => rx_los_low_ch1_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
+
+ P3 : PROCESS(fpga_rxrefclk_ch2, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch2 <= '0';
+ ELSIF (fpga_rxrefclk_ch2'event and fpga_rxrefclk_ch2 = '1') THEN
+ refclkdiv2_rx_ch2 <= not refclkdiv2_rx_ch2;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch2 : mupix_serdes_800rx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch2,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch2_sig,
+ rx_los_low_ch_s => rx_los_low_ch2_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch2_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch2_c);
+
+ P4 : PROCESS(fpga_rxrefclk_ch3, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch3 <= '0';
+ ELSIF (fpga_rxrefclk_ch3'event and fpga_rxrefclk_ch3 = '1') THEN
+ refclkdiv2_rx_ch3 <= not refclkdiv2_rx_ch3;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch3 : mupix_serdes_800rx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch3,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch3_sig,
+ rx_los_low_ch_s => rx_los_low_ch3_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch3_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch3_c);
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end mupix_serdes_800_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="mupix_serdes" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 01 11 14:37:59.578" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="mupix_serdes.lpc" type="lpc" modified="2018 01 11 14:18:09.000"/>
- <File name="mupix_serdes.pp" type="pp" modified="2018 01 11 14:18:09.000"/>
- <File name="mupix_serdes.sym" type="sym" modified="2018 01 11 14:18:10.000"/>
- <File name="mupix_serdes.tft" type="tft" modified="2018 01 11 14:18:09.000"/>
- <File name="mupix_serdes.txt" type="pcs_module" modified="2018 01 11 14:18:09.000"/>
- <File name="mupix_serdes.vhd" type="top_level_vhdl" modified="2018 01 11 14:18:09.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="mupix_serdes_new" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 05 25 10:06:05.483" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="mupix_serdes_new.lpc" type="lpc" modified="2018 05 25 10:05:57.000"/>
- <File name="mupix_serdes_new.pp" type="pp" modified="2018 05 25 10:05:57.000"/>
- <File name="mupix_serdes_new.sym" type="sym" modified="2018 05 25 10:05:58.000"/>
- <File name="mupix_serdes_new.tft" type="tft" modified="2018 05 25 10:05:57.000"/>
- <File name="mupix_serdes_new.txt" type="pcs_module" modified="2018 05 25 10:05:57.000"/>
- <File name="mupix_serdes_new.vhd" type="top_level_vhdl" modified="2018 05 25 10:05:57.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="mupix_serdes_sim" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 07 16 14:50:04.540" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="mupix_serdes_sim.lpc" type="lpc" modified="2018 07 16 14:50:00.000"/>
- <File name="mupix_serdes_sim.pp" type="pp" modified="2018 07 16 14:50:00.000"/>
- <File name="mupix_serdes_sim.sym" type="sym" modified="2018 07 16 14:50:00.000"/>
- <File name="mupix_serdes_sim.tft" type="tft" modified="2018 07 16 14:50:00.000"/>
- <File name="mupix_serdes_sim.txt" type="pcs_module" modified="2018 07 16 14:50:00.000"/>
- <File name="mupix_serdes_sim.vhd" type="top_level_vhdl" modified="2018 07 16 14:50:00.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_mupix_main" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 12 22 11:58:08.360" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="pll_mupix_main.lpc" type="lpc" modified="2017 12 22 11:58:04.000"/>
- <File name="pll_mupix_main.vhd" type="top_level_vhdl" modified="2017 12 22 11:58:04.000"/>
- <File name="pll_mupix_main_tmpl.vhd" type="template_vhdl" modified="2017 12 22 11:58:04.000"/>
- </Package>
-</DiamondModule>
use work.StdTypes.all;
use work.Constants.all;
+use work.Mupix_Serdes.all;
entity MupixDataLinkWithUnpacker is
generic (
g_useRecoveredClock : integer range 0 to 1 := c_Yes;
- g_linkSimulation : integer range 0 to 1 := c_Yes
+ g_clock_speed : clk_speed_t := c_40MHz
);
port(
sysclk : in std_logic; --trb system clock (typically 100 MHz)
Full : out std_logic);
end component serdes_fifo;
- component mupix_serdes_new
- generic (USER_CONFIG_FILE : string := "mupix_serdes_new.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic; -- input serial link from mupix
- rxiclk_ch0 : in std_logic; -- rx clock for fifo bridge (should be sysclock or recovered clock?)
- rx_full_clk_ch0 : out std_logic; -- full receive clock from serdes
- rx_half_clk_ch0 : out std_logic; -- half receive clock from serdes
- fpga_rxrefclk_ch0 : in std_logic; -- reference clock from fpga fabric
- rxdata_ch0 : out std_logic_vector (7 downto 0); -- received data
- rx_k_ch0 : out std_logic; -- control charactor indicator
- rx_disp_err_ch0 : out std_logic; -- indicate disparity error
- rx_cv_err_ch0 : out std_logic; -- error in data
- word_align_en_ch0_c : in std_logic; -- enable word alignment (pulse high)
- rx_pwrup_ch0_c : in std_logic; -- power up receive channel
- rx_los_low_ch0_s : out std_logic; -- signal lost
- rx_cdr_lol_ch0_s : out std_logic; -- clock recovery failure
- rx_div2_mode_ch0_c : in std_logic; -- enable clock div mode
--- CH1 --
- hdinp_ch1, hdinn_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- rxdata_ch1 : out std_logic_vector (7 downto 0);
- rx_k_ch1 : out std_logic;
- rx_disp_err_ch1 : out std_logic;
- rx_cv_err_ch1 : out std_logic;
- word_align_en_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- rx_div2_mode_ch1_c : in std_logic;
--- CH2 --
- hdinp_ch2, hdinn_ch2 : in std_logic;
- rxiclk_ch2 : in std_logic;
- rx_full_clk_ch2 : out std_logic;
- rx_half_clk_ch2 : out std_logic;
- fpga_rxrefclk_ch2 : in std_logic;
- rxdata_ch2 : out std_logic_vector (7 downto 0);
- rx_k_ch2 : out std_logic;
- rx_disp_err_ch2 : out std_logic;
- rx_cv_err_ch2 : out std_logic;
- word_align_en_ch2_c : in std_logic;
- rx_pwrup_ch2_c : in std_logic;
- rx_los_low_ch2_s : out std_logic;
- rx_cdr_lol_ch2_s : out std_logic;
- rx_div2_mode_ch2_c : in std_logic;
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- rxiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- word_align_en_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- rx_div2_mode_ch3_c : in std_logic;
----- Miscillaneous ports
- fpga_txrefclk : in std_logic; -- tx reference clock
- tx_sync_qd_c : in std_logic; -- serializer reset
- refclk2fpga : out std_logic; -- reference clock to fpga core
- rst_n : in std_logic; -- reset all
- serdes_rst_qd_c : in std_logic); -- reset serdes, but nor pcs
- end component mupix_serdes_new;
-
- component mupix_serdes_sim is
- generic (
- USER_CONFIG_FILE : string);
- port (
- hdinp_ch0, hdinn_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- word_align_en_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- rx_div2_mode_ch0_c : in std_logic;
- hdinp_ch1, hdinn_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- rxdata_ch1 : out std_logic_vector (7 downto 0);
- rx_k_ch1 : out std_logic;
- rx_disp_err_ch1 : out std_logic;
- rx_cv_err_ch1 : out std_logic;
- word_align_en_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- rx_div2_mode_ch1_c : in std_logic;
- hdinp_ch2, hdinn_ch2 : in std_logic;
- rxiclk_ch2 : in std_logic;
- rx_full_clk_ch2 : out std_logic;
- rx_half_clk_ch2 : out std_logic;
- fpga_rxrefclk_ch2 : in std_logic;
- rxdata_ch2 : out std_logic_vector (7 downto 0);
- rx_k_ch2 : out std_logic;
- rx_disp_err_ch2 : out std_logic;
- rx_cv_err_ch2 : out std_logic;
- word_align_en_ch2_c : in std_logic;
- rx_pwrup_ch2_c : in std_logic;
- rx_los_low_ch2_s : out std_logic;
- rx_cdr_lol_ch2_s : out std_logic;
- rx_div2_mode_ch2_c : in std_logic;
- hdinp_ch3, hdinn_ch3 : in std_logic;
- rxiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- word_align_en_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- rx_div2_mode_ch3_c : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_sync_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
- end component mupix_serdes_sim;
-
component MupixUnpacker
generic(
g_hitsize : integer := 40;
clkrx <= sysclk & sysclk & sysclk & sysclk;
end generate;
- gen_serdes_sim : if g_linkSimulation = c_Yes generate
- mupix_serdes_sim : entity work.mupix_serdes_sim
+ gen_serdes_400 : if g_clock_speed = c_40MHz generate
+ mupix_serdes : entity work.mupix_serdes_400
+ generic map (
+ USER_CONFIG_FILE => "mupix_serdes_400.txt")
+ port map (
+ hdinp_ch0 => mupix_data(0),
+ hdinn_ch0 => mupix_data(1),
+ rxiclk_ch0 => clkrx(0),
+ rx_full_clk_ch0 => rx_full_clock_i(0),
+ rx_half_clk_ch0 => open,
+ fpga_rxrefclk_ch0 => dataclk,
+ rxdata_ch0 => rx_data_i(1*8 - 1 downto 0*8),
+ rx_k_ch0 => rx_komma_i(0),
+ rx_disp_err_ch0 => rx_disp_err_i(0),
+ rx_cv_err_ch0 => rx_dataerror_i(0),
+ word_align_en_ch0_c => align_en_i(0),
+ rx_pwrup_ch0_c => ch_powerup_i(0),
+ rx_los_low_ch0_s => rx_sig_lost_i(0),
+ rx_cdr_lol_ch0_s => rx_cdr_i(0),
+ rx_div2_mode_ch0_c => ch_divmode_i(0),
+ hdinp_ch1 => mupix_data(2),
+ hdinn_ch1 => mupix_data(3),
+ rxiclk_ch1 => clkrx(1),
+ rx_full_clk_ch1 => rx_full_clock_i(1),
+ rx_half_clk_ch1 => open,
+ fpga_rxrefclk_ch1 => dataclk,
+ rxdata_ch1 => rx_data_i(2*8 - 1 downto 1*8),
+ rx_k_ch1 => rx_komma_i(1),
+ rx_disp_err_ch1 => rx_disp_err_i(1),
+ rx_cv_err_ch1 => rx_dataerror_i(1),
+ word_align_en_ch1_c => align_en_i(1),
+ rx_pwrup_ch1_c => ch_powerup_i(1),
+ rx_los_low_ch1_s => rx_sig_lost_i(1),
+ rx_cdr_lol_ch1_s => rx_cdr_i(1),
+ rx_div2_mode_ch1_c => ch_divmode_i(1),
+ hdinp_ch2 => mupix_data(4),
+ hdinn_ch2 => mupix_data(5),
+ rxiclk_ch2 => clkrx(2),
+ rx_full_clk_ch2 => rx_full_clock_i(2),
+ rx_half_clk_ch2 => open,
+ fpga_rxrefclk_ch2 => dataclk,
+ rxdata_ch2 => rx_data_i(3*8 - 1 downto 2*8),
+ rx_k_ch2 => rx_komma_i(2),
+ rx_disp_err_ch2 => rx_disp_err_i(2),
+ rx_cv_err_ch2 => rx_dataerror_i(2),
+ word_align_en_ch2_c => align_en_i(2),
+ rx_pwrup_ch2_c => ch_powerup_i(2),
+ rx_los_low_ch2_s => rx_sig_lost_i(2),
+ rx_cdr_lol_ch2_s => rx_cdr_i(2),
+ rx_div2_mode_ch2_c => ch_divmode_i(2),
+ hdinp_ch3 => mupix_data(6),
+ hdinn_ch3 => mupix_data(7),
+ rxiclk_ch3 => clkrx(3),
+ rx_full_clk_ch3 => rx_full_clock_i(3),
+ rx_half_clk_ch3 => open,
+ fpga_rxrefclk_ch3 => dataclk,
+ rxdata_ch3 => rx_data_i(4*8 - 1 downto 3*8),
+ rx_k_ch3 => rx_komma_i(3),
+ rx_disp_err_ch3 => rx_disp_err_i(3),
+ rx_cv_err_ch3 => rx_dataerror_i(3),
+ word_align_en_ch3_c => align_en_i(3),
+ rx_pwrup_ch3_c => ch_powerup_i(3),
+ rx_los_low_ch3_s => rx_sig_lost_i(3),
+ rx_cdr_lol_ch3_s => rx_cdr_i(3),
+ rx_div2_mode_ch3_c => ch_divmode_i(3),
+ fpga_txrefclk => dataclk,
+ tx_sync_qd_c => '0', -- serializer reset (not needed for receiving)
+ refclk2fpga => open,
+ rst_n => '1', -- reset all channels including PCS (active
+ -- low, not documented in maunal -> consult
+ -- vhdl code of trbnet)
+ serdes_rst_qd_c => reset_quad_i); -- reset all serdes channels but not PCS (active high)
+ end generate gen_serdes_400;
+
+ gen_serdes_600 : if g_clock_speed = c_60MHz generate
+ -- not sure about correct clock distribution
+ mupix_serdes : entity work.mupix_serdes_600
+ generic map (
+ USER_CONFIG_FILE => "mupix_serdes_600.txt")
+ port map (
+ hdinp_ch0 => mupix_data(0),
+ hdinn_ch0 => mupix_data(1),
+ rxiclk_ch0 => clkrx(0),
+ rx_full_clk_ch0 => rx_full_clock_i(0),
+ rx_half_clk_ch0 => open,
+ fpga_rxrefclk_ch0 => dataclk,
+ rxdata_ch0 => rx_data_i(1*8 - 1 downto 0*8),
+ rx_k_ch0 => rx_komma_i(0),
+ rx_disp_err_ch0 => rx_disp_err_i(0),
+ rx_cv_err_ch0 => rx_dataerror_i(0),
+ word_align_en_ch0_c => align_en_i(0),
+ rx_pwrup_ch0_c => ch_powerup_i(0),
+ rx_los_low_ch0_s => rx_sig_lost_i(0),
+ rx_cdr_lol_ch0_s => rx_cdr_i(0),
+ rx_div2_mode_ch0_c => ch_divmode_i(0),
+ hdinp_ch1 => mupix_data(2),
+ hdinn_ch1 => mupix_data(3),
+ rxiclk_ch1 => clkrx(1),
+ rx_full_clk_ch1 => rx_full_clock_i(1),
+ rx_half_clk_ch1 => open,
+ fpga_rxrefclk_ch1 => dataclk,
+ rxdata_ch1 => rx_data_i(2*8 - 1 downto 1*8),
+ rx_k_ch1 => rx_komma_i(1),
+ rx_disp_err_ch1 => rx_disp_err_i(1),
+ rx_cv_err_ch1 => rx_dataerror_i(1),
+ word_align_en_ch1_c => align_en_i(1),
+ rx_pwrup_ch1_c => ch_powerup_i(1),
+ rx_los_low_ch1_s => rx_sig_lost_i(1),
+ rx_cdr_lol_ch1_s => rx_cdr_i(1),
+ rx_div2_mode_ch1_c => ch_divmode_i(1),
+ hdinp_ch2 => mupix_data(4),
+ hdinn_ch2 => mupix_data(5),
+ rxiclk_ch2 => clkrx(2),
+ rx_full_clk_ch2 => rx_full_clock_i(2),
+ rx_half_clk_ch2 => open,
+ fpga_rxrefclk_ch2 => dataclk,
+ rxdata_ch2 => rx_data_i(3*8 - 1 downto 2*8),
+ rx_k_ch2 => rx_komma_i(2),
+ rx_disp_err_ch2 => rx_disp_err_i(2),
+ rx_cv_err_ch2 => rx_dataerror_i(2),
+ word_align_en_ch2_c => align_en_i(2),
+ rx_pwrup_ch2_c => ch_powerup_i(2),
+ rx_los_low_ch2_s => rx_sig_lost_i(2),
+ rx_cdr_lol_ch2_s => rx_cdr_i(2),
+ rx_div2_mode_ch2_c => ch_divmode_i(2),
+ hdinp_ch3 => mupix_data(6),
+ hdinn_ch3 => mupix_data(7),
+ rxiclk_ch3 => clkrx(3),
+ rx_full_clk_ch3 => rx_full_clock_i(3),
+ rx_half_clk_ch3 => open,
+ fpga_rxrefclk_ch3 => dataclk,
+ rxdata_ch3 => rx_data_i(4*8 - 1 downto 3*8),
+ rx_k_ch3 => rx_komma_i(3),
+ rx_disp_err_ch3 => rx_disp_err_i(3),
+ rx_cv_err_ch3 => rx_dataerror_i(3),
+ word_align_en_ch3_c => align_en_i(3),
+ rx_pwrup_ch3_c => ch_powerup_i(3),
+ rx_los_low_ch3_s => rx_sig_lost_i(3),
+ rx_cdr_lol_ch3_s => rx_cdr_i(3),
+ rx_div2_mode_ch3_c => ch_divmode_i(3),
+ fpga_txrefclk => dataclk,
+ tx_sync_qd_c => '0', -- serializer reset (not needed for receiving)
+ refclk2fpga => open,
+ rst_n => '1', -- reset all channels including PCS (active
+ -- low, not documented in maunal -> consult
+ -- vhdl code of trbnet)
+ serdes_rst_qd_c => reset_quad_i); -- reset all serdes channels but not PCS (active high)
+ end generate gen_serdes_600;
+
+ gen_serdes_800 : if g_clock_speed = c_80MHz generate
+ -- not sure about correct clock distribution
+ mupix_serdes : entity work.mupix_serdes_800
generic map (
- USER_CONFIG_FILE => "mupix_serdes_sim.txt")
+ USER_CONFIG_FILE => "mupix_serdes_800.txt")
port map (
hdinp_ch0 => mupix_data(0),
hdinn_ch0 => mupix_data(1),
-- low, not documented in maunal -> consult
-- vhdl code of trbnet)
serdes_rst_qd_c => reset_quad_i); -- reset all serdes channels but not PCS (active high)
- end generate gen_serdes_sim;
+ end generate gen_serdes_800;
- gen_serdes_data : if g_linkSimulation = c_No generate
+ gen_serdes_1250 : if g_clock_speed = c_125MHz generate
-- not sure about correct clock distribution
- mupix_serdes_new : entity work.mupix_serdes_new
+ mupix_serdes : entity work.mupix_serdes_1250
generic map (
- USER_CONFIG_FILE => "mupix_serdes_new.txt")
+ USER_CONFIG_FILE => "mupix_serdes_1250.txt")
port map (
hdinp_ch0 => mupix_data(0),
hdinn_ch0 => mupix_data(1),
-- low, not documented in maunal -> consult
-- vhdl code of trbnet)
serdes_rst_qd_c => reset_quad_i); -- reset all serdes channels but not PCS (active high)
- end generate gen_serdes_data;
+ end generate gen_serdes_1250;
-- synchronize rx data signals into receive clock domain (maybe not
-- necessary, but should not do any harm)
use work.Constants.all;
entity MupixBoard8 is
+ generic (
+ g_clock_speed : clk_speed_t := c_40MHz);
port(
--Clock signal
clk : in std_logic; --trb system clock for slow control
end component FrameGeneratorMux;
component MupixDataLinkWithUnpacker is
+ generic (
+ g_useRecoveredClock : integer range 0 to 1 := c_Yes;
+ g_clock_speed : clk_speed_t := c_40MHz
+ );
port(
sysclk : in std_logic;
dataclk : in std_logic;
signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links - 1 downto 0);
signal reset_reg : std_logic := '0';
-
+
begin -- Behavioral
-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------
- register_reset: process (clk) is
+ register_reset : process (clk) is
begin -- process register_reset
if rising_edge(clk) then -- rising clock edge
reset_reg <= reset;
end if;
end process register_reset;
-
+
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
PORT_NUMBER => NUM_PORTS,
boardcontrol_1 : entity work.MupixBoardDAC
generic map(
- fpga_clock_speed => fpga_clk_speed,
- spi_clock_speed => board_spi_clk_speed
- )
+ fpga_clock_speed => fpga_clk_speed,
+ spi_clock_speed => board_spi_clk_speed
+ )
port map(
clk => clk,
reset => reset_reg,
);
mupix_data_link : entity work.MupixDataLinkWithUnpacker
+ generic map (
+ g_useRecoveredClock => c_Yes,
+ g_clock_speed => g_clock_speed)
port map(
sysclk => clk,
dataclk => data_clk,
library ecp3;
use ecp3.components.all;
+use work.Constants.all;
+use work.Mupix_PLL.all;
-entity MupixClocks is
+entity MupixClocks is
+ generic (
+ g_clock_speed : clk_speed_t := c_40MHz);
port (
input_clock : in std_logic; -- input clock to pll (200 Mhz)
- clkext : out std_logic; -- external mupix clock
- clkref : out std_logic); -- mupix reference clock
+ clkext_o : out std_logic; -- external mupix clock
+ clkref_o : out std_logic; -- mupix reference clock
+ clkdata_o : out std_logic); -- clock for serdes rx
end entity MupixClocks;
architecture rtl of MupixClocks is
- component pll_mupix_main
- port (CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic);
- end component;
-
signal mupix_clk_i : std_logic;
-
+
attribute ODDRAPPS : string;
attribute ODDRAPPS of mupix_oddr_1 : label is "SCLK_ALIGNED";
attribute ODDRAPPS of mupix_oddr_2 : label is "SCLK_ALIGNED";
-
+
begin -- architecture rtl
- mupix_main_pll_1 : pll_mupix_main
- port map (
- CLK => input_clock,
- CLKOP => mupix_clk_i,
- LOCK => open);
-
- mupix_oddr_1 : ODDRXD1
- port map(
- SCLK => mupix_clk_i,
- DA => '1',
- DB => '0',
- Q => clkext);
-
- mupix_oddr_2 : ODDRXD1
- port map(
- SCLK => mupix_clk_i,
- DA => '1',
- DB => '0',
- Q => clkref);
+ gen_clk_40 : if g_clock_speed = c_40MHz generate
+ mupix_main_pll_1 : mupix_pll_main_40
+ port map (
+ CLK => input_clock,
+ CLKOP => mupix_clk_i,
+ LOCK => open);
+ end generate gen_clk_40;
+
+ gen_clk_60 : if g_clock_speed = c_60MHz generate
+ mupix_main_pll_1 : mupix_pll_main_60
+ port map (
+ CLK => input_clock,
+ CLKOP => mupix_clk_i,
+ LOCK => open);
+ end generate gen_clk_60;
+
+ gen_clk_80 : if g_clock_speed = c_80MHz generate
+ mupix_main_pll_1 : mupix_pll_main_80
+ port map (
+ CLK => input_clock,
+ CLKOP => mupix_clk_i,
+ LOCK => open);
+ end generate gen_clk_80;
+
+ gen_clk_125 : if g_clock_speed = c_125MHz generate
+ mupix_main_pll_1 : mupix_pll_main_125
+ port map (
+ CLK => input_clock,
+ CLKOP => mupix_clk_i,
+ LOCK => open);
+ end generate gen_clk_125;
+
+
+ mupix_oddr_1 : ODDRXD1
+ port map(
+ SCLK => mupix_clk_i,
+ DA => '1',
+ DB => '0',
+ Q => clkext_o);
+
+ mupix_oddr_2 : ODDRXD1
+ port map(
+ SCLK => mupix_clk_i,
+ DA => '1',
+ DB => '0',
+ Q => clkref_o);
+
+ clkdata_o <= mupix_clk_i;
end architecture rtl;
library ecp3;
use ecp3.components.all;
+use work.Constants.all;
+use work.Mupix_PLL.all;
entity LinkSimulation is
+ generic (
+ g_clock_speed : clk_speed_t := c_40MHz);
port (
trbclk : in std_logic; -- 100 MHz TRB Clock
- sendclk : in std_logic; -- 200 MHz Send Clock (from input pin)
+ pllclk : in std_logic; -- 200 MHz pll Clock (from input pin)
reset : in std_logic; -- reset
data_out : out std_logic; -- simulation data out
- simclk : out std_logic; -- simulation clock (200 MHz)
- dataclk : out std_logic); -- data clock to serdes (40 Mhz)
+ simclk : out std_logic; -- simulation clock
+ dataclk : out std_logic); -- data clock to serdes
end entity LinkSimulation;
architecture rtl of LinkSimulation is
- component mupix_sim_pll is
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- LOCK : out std_logic);
- end component mupix_sim_pll;
-
component MupixStateMachine is
port (
clk : in std_logic;
signal fifo_data_out : std_logic_vector(9 downto 0);
signal fifo_wren_i : std_logic;
signal fifo_data_in : std_logic_vector(9 downto 0);
- signal words_i : std_logic_vector(4 downto 0) := "00100";
- signal slowdown_i : std_logic_vector(15 downto 0) := x"FF0A";
+ constant words_i : std_logic_vector(4 downto 0) := "00100";
+ constant slowdown_i : std_logic_vector(15 downto 0) := x"FF0A";
- signal reset_reg : std_logic := '0';
+ signal reset_reg, reset_reg2 : std_logic := '0';
begin -- architecture rtl
- register_reset: process (trbclk) is
+ register_reset : process (trbclk) is
begin -- process register_reset
- if rising_edge(trbclk) then -- rising clock edge
+ if rising_edge(trbclk) then -- rising clock edge
reset_reg <= reset;
end if;
end process register_reset;
- mupix_sim_pll_1 : entity work.mupix_sim_pll
- port map (
- CLK => sendclk,
- CLKOP => data_clk_i,
- CLKOS => sim_clk_i,
- LOCK => open);
+ register_reset_data: process (data_clk_i) is
+ begin -- process register_reset_data
+ if rising_edge(data_clk_i) then -- rising clock edge
+ reset_reg2 <= reset_reg;
+ end if;
+ end process register_reset_data;
+
+ gen_mupix_sim_pll_40 : if g_clock_speed = c_40MHz generate
+ mupix_pll_sim_1 : mupix_pll_sim_40
+ port map (
+ CLK => pllclk, -- 200 MHz
+ CLKOP => data_clk_i, -- 40 MHz
+ CLKOS => sim_clk_i, -- 200 MHz
+ LOCK => open);
+ end generate gen_mupix_sim_pll_40;
+
+ gen_mupix_sim_pll_80 : if g_clock_speed = c_80MHz generate
+ mupix_pll_sim_1 : mupix_pll_sim_80
+ port map (
+ CLK => pllclk, -- 200 MHz
+ CLKOP => data_clk_i, -- 80 MHz
+ CLKOS => sim_clk_i, -- 200 MHz
+ LOCK => open);
+ end generate gen_mupix_sim_pll_80;
+
MupixStateMachine_1 : entity work.MupixStateMachine
port map (
clk => data_clk_i,
- reset => reset_reg,
+ reset => reset_reg2,
words => words_i,
slowdown => slowdown_i,
wr_en => fifo_wren_i,
rden => fifo_rden_i,
dataout => data_out_i);
+
simlink_oddr : ODDRXD1
port map (
SCLK => sim_clk_i,
--configuration state machine
type t_config_fsm is (idle, config, readfifo, waitfifo);
signal config_fsm : t_config_fsm := idle;
- signal config_busy : std_logic := '0';
+ signal config_busy : std_logic := '0';
--readback of configuration data
constant c_config_words_max : integer := config_bits/32 + 1;
signal mupix_ctrcl_select : std_logic;
signal mupix_ctrl_i, mupix_ctrl_ext, mupix_ctrl_sel, mupix_ctrl_reg : MupixSlowControl := c_mupix_slctrl_init;
+ signal reset_fastcontrol_i : std_logic := '0';
+ signal configure_state, sendbits_state : std_logic_vector(3 downto 0) := (others => '0');
begin -- Behavioral
sendpix_bits : process(clk) is
begin
if rising_edge(clk) then
- if reset = '1' then
+ if reset = '1' or reset_fastcontrol_i = '1' then
send_bits_fsm <= idle;
mupix_ctrl_i.clk1 <= '0';
mupix_ctrl_i.clk2 <= '0';
mupix_ctrl_i.sin <= '0';
sending <= '0';
+ bitcounter <= (others => '0');
else
mupix_ctrl_i.clk1 <= '0';
mupix_ctrl_i.clk2 <= '0';
bitcouner_word <= 0;
sending <= '0';
clk_div_cnt <= 0;
+ sendbits_state <= x"1";
send_bits_fsm <= idle;
if start_send = '1' then
sending <= '1';
end if;
when din =>
mupix_ctrl_i.sin <= DataOut(bitcouner_word);
+ sendbits_state <= x"2";
if clk_div_cnt = c_clk_div_max - 1 then
clk_div_cnt <= 0;
send_bits_fsm <= clk1high;
when clk1high =>
mupix_ctrl_i.sin <= DataOut(bitcouner_word);
mupix_ctrl_i.clk1 <= '1';
+ sendbits_state <= x"3";
if clk_div_cnt = c_clk_div_max - 1 then
clk_div_cnt <= 0;
send_bits_fsm <= clk1low;
end if;
when clk1low =>
mupix_ctrl_i.sin <= DataOut(bitcouner_word);
+ sendbits_state <= x"4";
if clk_div_cnt = c_clk_div_max - 1 then
clk_div_cnt <= 0;
send_bits_fsm <= clk2high;
when clk2high =>
mupix_ctrl_i.sin <= DataOut(bitcouner_word);
mupix_ctrl_i.clk2 <= '1';
+ sendbits_state <= x"5";
if clk_div_cnt = c_clk_div_max - 1 then
clk_div_cnt <= 0;
send_bits_fsm <= clk2low;
end if;
when clk2low =>
mupix_ctrl_i.sin <= DataOut(bitcouner_word);
+ sendbits_state <= x"6";
if clk_div_cnt = c_clk_div_max - 1 then
clk_div_cnt <= 0;
if bitcouner_word = 31 or bitcounter = bitstosend then
configure_proc : process(clk) is
begin
if rising_edge(clk) then
- if reset = '1' then
+ if reset = '1' or reset_fastcontrol_i = '1' then
mupix_ctrl_i.load <= '0';
config_fsm <= idle;
config_busy <= '0';
config_busy <= '1';
case config_fsm is
when idle =>
- config_busy <= '0';
+ config_busy <= '0';
+ configure_state <= x"1";
if Empty = '0' then
config_fsm <= readfifo;
else
config_fsm <= idle;
end if;
when readfifo =>
+ configure_state <= x"2";
if Empty = '0' then
ReadEn <= '1';
start_send <= '1';
config_fsm <= readfifo; -- wait on next config word in fifo
end if;
when waitfifo => -- wait for fifo word to be valid
- config_fsm <= config;
+ configure_state <= x"3";
+ config_fsm <= config;
when config =>
+ configure_state <= x"3";
if sending = '1' then
config_fsm <= config;
else
-- bit 4: select FPGA programming or software programming
-- bit 5: reset outgoing CRC sum
-- bit 6: reset incoming CRC sum
+ -- bit 7: readback
+ -- bit 8: reset fast slow control
-- bit 31-16: number of total bits for configuration
--x0084: reset readback process
--x0085: set readback address/data from readback memory
+ --x0086: status of fast configuration
-----------------------------------------------------------------------------
SLV_BUS : process(clk)
begin -- process SLV_BUS
reset_crc_to_mupix_ext <= '0';
reset_crc_from_mupix_ext <= '0';
reset_readback_i <= '0';
+ reset_fastcontrol_i <= '0';
slv_data_out <= (others => '0');
if SLV_WRITE_IN = '1' then
case SLV_ADDR_IN is
reset_crc_to_mupix_ext <= SLV_DATA_IN(5);
reset_crc_from_mupix_ext <= SLV_DATA_IN(6);
mupix_ctrl_ext.rb <= SLV_DATA_IN(7);
+ reset_fastcontrol_i <= SLV_DATA_IN(8);
bitstosend <= unsigned(SLV_DATA_IN(31 downto 16));
SLV_ACK_OUT <= '1';
when x"0084" =>
when x"0085" =>
slv_ack_out <= '1';
slv_data_out <= readback_data_out;
+ when x"0086" =>
+ slv_ack_out <= '1';
+ slv_data_out(3 downto 0) <= configure_state;
+ slv_data_out(7 downto 4) <= sendbits_state;
+ slv_data_out(23 downto 8) <= std_logic_vector(bitcounter);
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
constant c_Yes : integer := 1;
constant c_No : integer := 0;
+ subtype clk_speed_t is integer range 0 to 3;
+ constant c_40MHz : clk_speed_t := 0;
+ constant c_60MHz : clk_speed_t := 1;
+ constant c_80MHz : clk_speed_t := 2;
+ constant c_125MHz : clk_speed_t := 3;
+
end package Constants;
#ip cores for mupix design
add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib "work" "cores/pll_mupix_main.vhd"
-add_file -vhdl -lib "work" "cores/mupix_serdes_new.vhd"
-add_file -vhdl -lib "work" "cores/mupix_serdes_sim.vhd"
add_file -vhdl -lib "work" "cores/serdes_fifo.vhd"
-add_file -vhdl -lib "work" "cores/mupix_sim_pll.vhd"
add_file -vhdl -lib "work" "cores/fifo_sim.vhd"
add_file -vhdl -lib "work" "cores/RAM_DP_4096_32.vhd"
add_file -vhdl -lib "work" "cores/FIFO_40_512.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_main_40.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_main_60.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_main_80.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_main_125.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_sim_40.vhd"
+add_file -vhdl -lib "work" "cores/PLL/mupix_pll_sim_80.vhd"
+add_file -vhdl -lib "work" "cores/Serdes/mupix_serdes_400.vhd"
+add_file -vhdl -lib "work" "cores/Serdes/mupix_serdes_600.vhd"
+add_file -vhdl -lib "work" "cores/Serdes/mupix_serdes_800.vhd"
+add_file -vhdl -lib "work" "cores/Serdes/mupix_serdes_1250.vhd"
#MuPix Files
add_file -vhdl -lib "work" "trb3_periph.vhd"
+add_file -vhdl -lib "work" "cores/PLL/PLL_Components.vhd"
+add_file -vhdl -lib "work" "cores/Serdes/Serdes_Components.vhd"
add_file -vhdl -lib "work" "sources/StdTypes.vhd"
add_file -vhdl -lib "work" "sources/constants.vhd"
add_file -vhdl -lib "work" "sources/MupixBoard.vhd"
use work.trb_net_components.all;
use work.trb3_components.all;
use work.version.all;
+use work.Constants.all;
library ecp3;
use ecp3.components.all;
entity trb3_periph is
- generic (
- g_linksimulation : integer := c_Yes); -- do link simualtion, no for normal
- -- data taking
port(
--Clocks
- --CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- --CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- --CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
--Trigger
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
--Serdes
- --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- SERDES_INT_TX : out std_logic_vector(3 downto 0);
- SERDES_INT_RX : in std_logic_vector(3 downto 0);
- --SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- --SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
- mupix_serdes_rx : in std_logic_vector(7 downto 0);
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ mupix_serdes_rx : in std_logic_vector(7 downto 0);
--Inter-FPGA Communication
- --FPGA5_COMM : inout std_logic_vector(11 downto 0);
- FPGA5_COMM0 : inout std_logic;
- FPGA5_COMM2 : inout std_logic;
+ FPGA5_COMM0 : inout std_logic;
+ FPGA5_COMM2 : inout std_logic;
--Bit 0/1 input, serial link RX active
--Bit 2/3 output, serial link TX active
syncres : out std_logic; --reset of mupix timestamps and counters
--fast data comes in via serdes addon (see above)
--link simulation
- simlink : out std_logic; -- spare link 0
- simclk : out std_logic; -- spare link 2
+ simlink : out std_logic; -- spare link 0
+ simclk : out std_logic; -- spare link 2
---------------------------------------------------------------------------
-- END SensorBoard MuPix
attribute syn_useioff of FLASH_CS : signal is true;
attribute syn_useioff of FLASH_DIN : signal is true;
attribute syn_useioff of FLASH_DOUT : signal is true;
- --attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_useioff of FPGA5_COMM0 : signal is true;
- attribute syn_useioff of FPGA5_COMM2 : signal is true;
+ attribute syn_useioff of FPGA5_COMM0 : signal is true;
+ attribute syn_useioff of FPGA5_COMM2 : signal is true;
attribute syn_useioff of TEST_LINE : signal is true;
- --attribute syn_useioff of INP : signal is false;
- --attribute syn_useioff of DAC_SDO : signal is true;
- --attribute syn_useioff of DAC_SDI : signal is true;
- --attribute syn_useioff of DAC_SCK : signal is true;
- --attribute syn_useioff of DAC_CS : signal is true;
end entity;
architecture trb3_periph_arch of trb3_periph is
+ constant c_clock_speed : clk_speed_t := c_40MHz; -- clock speed for data taking
+ constant c_linksimulation : integer := c_YES; -- built the link simulation part
+ -- only use clock speed = 40
+ -- MHz with this option
component MupixBoard8 is
+ generic (
+ g_clock_speed : clk_speed_t := c_40MHz);
port(
--Clock signal
clk : in std_logic;
end component resethandler;
component LinkSimulation is
+ generic (
+ g_clock_speed : clk_speed_t := c_40MHz);
port (
trbclk : in std_logic;
- sendclk : in std_logic;
+ pllclk : in std_logic;
reset : in std_logic;
data_out : out std_logic;
simclk : out std_logic;
end component LinkSimulation;
component MupixClocks is
+ generic (
+ g_clock_speed : clk_speed_t);
port (
input_clock : in std_logic;
- clkext : out std_logic;
- clkref : out std_logic);
+ clkext_o : out std_logic;
+ clkref_o : out std_logic;
+ clk_data_o : out std_logic);
end component MupixClocks;
-
+
--Constants
constant REGIO_NUM_STAT_REGS : integer := 5;
constant REGIO_NUM_CTRL_REGS : integer := 3;
constant NumberFEECards : integer := 1;
--attributes for clock output ddr buffers
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-- MuPix Frontend-Board
-----------------------------------------------------------------------------
MupixBoard8_0 : MupixBoard8
+ generic map (
+ g_clock_speed => c_clock_speed)
port map (
clk => clk_100_i,
fast_clk => clk_200_i,
SLV_NO_MORE_DATA_OUT => resethandler_regio_no_more_data_out_0,
SLV_UNKNOWN_ADDR_OUT => resethandler_regio_unknown_addr_out_0);
- -- generate clocks for normal data taking
-
-- generate logic for link simulation
- gen_simulation: if g_linksimulation = c_Yes generate
- LinkSimulation_1: entity work.LinkSimulation
+ gen_simulation : if c_linksimulation = c_Yes and (c_clock_speed = c_40MHz) generate
+ LinkSimulation_1 : entity work.LinkSimulation
+ generic map (
+ g_clock_speed => c_clock_speed)
port map (
trbclk => clk_100_i,
- sendclk => CLK_PCLK_RIGHT,
+ pllclk => CLK_PCLK_RIGHT,
reset => reset_i,
data_out => simlink,
simclk => simclk,
dataclk => mupix_clk_i);
+
+ clkext <= mupix_clk_i;
+ clkref <= mupix_clk_i;
end generate gen_simulation;
- gen_data: if g_linksimulation = c_No generate
- MupixClocks_1: entity work.MupixClocks
+ -- generate clocks for normal data taking
+ gen_simulation : if c_linksimulation = c_No generate
+ MupixClocks_1 : entity work.MupixClocks
+ generic map (
+ g_clock_speed => c_clock_speed)
port map (
input_clock => CLK_PCLK_RIGHT,
- clkext => mupix_clk_i,
- clkref => clkref);
-
- clkext <= mupix_clk_i;
- end generate gen_data;
+ clkext_o => clkext,
+ clkref_o => clkref,
+ clkdata_o => mupix_clk_i);
+ end generate gen_simulation;
--dummy process to test syncres
dummy_proc : process(clk_100_i)
jspc29 / trb3.git / commitdiff