add dqs 6x5 to project file

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index ae59479a7afd0563b93e0bc50093f9f3e963eb77..40cb090e470f53be8dd27752dabef882fb4fd797 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -150,6 +150,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_80.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput_6x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_4x5.vhd"
 add_file -vhdl -lib "work" "sim/dqsinput_dummy.vhd"