--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+USE ieee.std_logic_signed.ALL;
+
+USE ieee.std_logic_arith.ALL;
+
+USE std.textio.ALL;
+USE ieee.std_logic_textio.ALL;
+
+entity trb_net_priority_arbiter_testbench is
+
+end trb_net_priority_arbiter_testbench;
+
+architecture trb_net_priority_arbiter_testbench_arch of trb_net_priority_arbiter_testbench is
+
+ signal clk : std_logic := '0';
+ signal reset : std_logic := '1';
+
+ signal read_type : std_logic_vector(2 downto 0) := (others => '0');
+ signal read_f2 : std_logic_vector(3 downto 0) := (others => '0');
+ signal read_f1 : std_logic_vector(7 downto 0) := (others => '0');
+ signal rol_mask : std_logic := '0';
+ signal ctrl: std_logic_vector(31 downto 0) := (others => '0');
+ component trb_net_priority_arbiter is
+
+ generic (WIDTH : integer := 32);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+END component;
+
+
+begin
+
+ UUT: trb_net_priority_arbiter
+ generic map (
+ WIDTH => 8
+ )
+ port map (
+ CLK =>clk,
+ RESET => reset,
+ CLK_EN => '1',
+
+ INPUT_IN => read_f1,
+
+ CTRL => ctrl
+ );
+
+ clk <= not clk after 10ns;
+ ctrl(9) <= rol_mask;
+
+ DO_RESET : process
+ begin
+ reset <= '1';
+ wait for 30ns;
+ reset <= '0';
+-- ctrl(8 downto 0) <= "100000000"; --only fixed
+-- ctrl(8 downto 0) <= "111111111"; --only rr
+ ctrl(8 downto 0) <= "101010101"; --mixed
+ wait for 20ns;
+ ctrl(8 downto 0) <= "000000000";
+ wait;
+ end process DO_RESET;
+
+ STIMULI: process (clk)
+ file protokoll : text open read_mode is "in_priority_arbiter.txt";
+ variable myoutline : line;
+ variable leer : character;
+ variable var1, var2 : std_logic;
+ variable varx1 : std_logic_vector(2 downto 0);
+ variable varx2, varx3 : std_logic_vector(7 downto 0);
+ begin
+ if falling_edge(CLK) then
+ if (not endfile(protokoll)) then
+ readline(protokoll,myoutline);
+
+ read(myoutline,varx2);
+ read_f1 <= varx2;
+ read(myoutline,leer);
+
+ read(myoutline,var1);
+ rol_mask <= var1;
+
+ end if;
+ end if;
+ end process STIMULI;
+
+
+end trb_net_priority_arbiter_testbench_arch;
+
+-- fuse -prj trb_net_priority_arbiter_testbench_beh.prj -top trb_net_priority_arbiter_testbench -o trb_net_priority_arbiter_testbench
+
+-- trb_net_priority_arbiter_testbench -tclbatch priority_arbiter_testsim.tcl
+
+-- isimwave isimwavedata.xwv
+
entity trb_net_priority_arbiter is
- generic (WIDTH : integer := 8);
+ generic (WIDTH : integer := 32);
- port(
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
+ RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0)
);
END trb_net_priority_arbiter;
END component;
signal next_fixed_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- signal next_rr_pattern, current_rr_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ signal next_rr_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal next_p1_pattern, current_p1_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal next_p2_pattern, current_p2_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
signal sampled_rr_pattern1, sampled_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ signal proposed_rr_pattern1, proposed_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ signal leading_rr_pattern1, leading_rr_pattern2: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ signal next_final_pattern, current_final_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ signal current_rr_mask, next_rr_mask: STD_LOGIC_VECTOR (7 downto 0);
+
+ signal use_rr: STD_LOGIC;
+
begin
port map(
INPUT_IN => sampled_rr_pattern1,
RESULT_OUT => proposed_rr_pattern1,
- PATTERN_OUT => leading_rr_pattern2
+ PATTERN_OUT => leading_rr_pattern1
);
ENC3: trb_net_priority_encoder
sampled_rr_pattern1 <= INPUT_IN and current_p1_pattern;
sampled_rr_pattern2 <= INPUT_IN and current_p2_pattern;
-
- comb_rr : process(CLK)
+
+ use_rr <= current_rr_mask(0) and CTRL(9); --rol_mask is on
+ RESULT_OUT <= current_final_pattern;
+
+ comb_rr : process(current_p1_pattern, current_p2_pattern,use_rr,
+ sampled_rr_pattern1, sampled_rr_pattern2, proposed_rr_pattern1,
+ proposed_rr_pattern2, leading_rr_pattern1, leading_rr_pattern2,
+ current_rr_mask, CTRL, next_fixed_pattern, next_rr_pattern)
begin
- next_rr_pattern <= current_rr_pattern;
+ next_rr_pattern <= (others => '0');
next_p1_pattern <= current_p1_pattern;
next_p2_pattern <= current_p2_pattern;
-
+ next_rr_mask <= current_rr_mask;
+ next_final_pattern <= (others => '0');
+
if use_rr = '1' then
- -- without using the rr, nothing will happen
- if or_all(sampled_rr_pattern1) then
+ -- when _using_ the rr, overwrite the current pattern with a new one (
+ -- this means do the "round" of the robin
+ if or_all(sampled_rr_pattern1) = '1' then
-- pattern 1 has higher priority
- next_rr_pattern <= proposed_rr_pattern;
- next_p1_pattern <= leading_rr_pattern1 xor proposed_rr_pattern;
- next_p2_pattern <= not leading_rr_pattern1;
- elsif or_all(sampled_rr_pattern2) then
- else
+ next_p1_pattern <= leading_rr_pattern1 xor proposed_rr_pattern1;
+ next_p2_pattern <= not leading_rr_pattern1 or proposed_rr_pattern1;
+ elsif or_all(sampled_rr_pattern2) = '1' then
+ next_p1_pattern <= leading_rr_pattern2 xor proposed_rr_pattern2;
+ next_p2_pattern <= not leading_rr_pattern2 or proposed_rr_pattern2;
end if;
end if;
+
+ if or_all(sampled_rr_pattern1) = '1' then
+ next_rr_pattern <= proposed_rr_pattern1;
+ elsif or_all(sampled_rr_pattern2) = '1' then
+ next_rr_pattern <= proposed_rr_pattern2;
+ end if;
+
+ if (CTRL(9) = '1') and (CTRL(8) = '0') then -- rol
+ next_rr_mask(6 downto 0) <= current_rr_mask(7 downto 1);
+ next_rr_mask(7) <= current_rr_mask(0);
+ elsif (CTRL(8) = '1') then --overwrite
+ next_rr_mask(7 downto 0) <= CTRL(7 downto 0);
+ end if;
+
+ -- finally make the pattern
+ if current_rr_mask(0) = '0' then
+ next_final_pattern <= next_fixed_pattern;
+ else
+ next_final_pattern <= next_rr_pattern;
+ end if;
end process;
+
+ sync_rr : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_p1_pattern <= (others => '1');
+ current_p2_pattern <= (others => '0');
+ current_rr_mask <= (others => '0');
+ current_final_pattern <= (others => '0');
+ current_rr_mask <= (others => '0');
+ elsif CLK_EN = '1' then
+ current_p1_pattern <= next_p1_pattern;
+ current_p2_pattern <= next_p2_pattern;
+ current_rr_mask <= next_rr_mask;
+ current_final_pattern <= next_final_pattern;
+ current_rr_mask <= next_rr_mask;
+ else
+ current_p1_pattern <= current_p1_pattern;
+ current_p2_pattern <= current_p2_pattern;
+ current_rr_mask <= current_rr_mask;
+ current_final_pattern <= current_final_pattern;
+ current_rr_mask <= current_rr_mask;
+ end if;
+ end if;
+ end process;
+
+
-end trb_net_riority_arbiter_arch;
+end trb_net_priority_arbiter_arch;
jspc29 / trbnet.git / commitdiff