attribute syn_keep : boolean;
attribute syn_keep of led_counter : signal is true;
+ signal tx_correct : std_logic_vector(7 downto 0);
+ signal first_idle : std_logic_vector(3 downto 0);
+
begin
--------------------------------------------------------------------------
ff_rxhalfclk_ch0 => open,
ff_xmit_ch0 => "00", -- UNKNOWN
ff_rx_even_ch0 => open, -- UNKNOWN
- ff_correct_disp_ch0 => "00",
+ ff_correct_disp_ch0 => tx_correct(1 downto 0),
ff_disp_err_ch0 => link_error(0)(9 downto 8),
ff_cv_ch0 => link_error(0)(1 downto 0),
ffc_rrst_ch0 => '0',
ff_rxhalfclk_ch1 => open,
ff_xmit_ch1 => "00", -- UNKNOWN
ff_rx_even_ch1 => open, -- UNKNOWN
- ff_correct_disp_ch1 => "00",
+ ff_correct_disp_ch1 => tx_correct(3 downto 2),
ff_disp_err_ch1 => link_error(1)(9 downto 8),
ff_cv_ch1 => link_error(1)(1 downto 0),
ffc_rrst_ch1 => '0',
ff_rxhalfclk_ch2 => open,
ff_xmit_ch2 => "00", -- UNKNOWN
ff_rx_even_ch2 => open, -- UNKNOWN
- ff_correct_disp_ch2 => "00",
+ ff_correct_disp_ch2 => tx_correct(5 downto 4),
ff_disp_err_ch2 => link_error(2)(9 downto 8),
ff_cv_ch2 => link_error(2)(1 downto 0),
ffc_rrst_ch2 => '0',
ff_rxhalfclk_ch3 => open,
ff_xmit_ch3 => "00", -- UNKNOWN
ff_rx_even_ch3 => open, -- UNKNOWN
- ff_correct_disp_ch3 => "00",
+ ff_correct_disp_ch3 => tx_correct(7 downto 6),
ff_disp_err_ch3 => link_error(3)(9 downto 8),
ff_cv_ch3 => link_error(3)(1 downto 0),
ffc_rrst_ch3 => '0',
ff_rxhalfclk_ch0 => open,
ff_xmit_ch0 => "00", -- UNKNOWN
ff_rx_even_ch0 => open, -- UNKNOWN
- ff_correct_disp_ch0 => "00",
+ ff_correct_disp_ch0 => tx_correct(7 downto 6),
ff_disp_err_ch0 => link_error(3)(9 downto 8),
ff_cv_ch0 => link_error(3)(1 downto 0),
ffc_rrst_ch0 => '0',
ff_rxhalfclk_ch1 => open,
ff_xmit_ch1 => "00", -- UNKNOWN
ff_rx_even_ch1 => open, -- UNKNOWN
- ff_correct_disp_ch1 => "00",
+ ff_correct_disp_ch1 => tx_correct(5 downto 4),
ff_disp_err_ch1 => link_error(2)(9 downto 8),
ff_cv_ch1 => link_error(2)(1 downto 0),
ffc_rrst_ch1 => '0',
ff_rxhalfclk_ch2 => open,
ff_xmit_ch2 => "00", -- UNKNOWN
ff_rx_even_ch2 => open, -- UNKNOWN
- ff_correct_disp_ch2 => "00",
+ ff_correct_disp_ch2 => tx_correct(3 downto 2),
ff_disp_err_ch2 => link_error(1)(9 downto 8),
ff_cv_ch2 => link_error(1)(1 downto 0),
ffc_rrst_ch2 => '0',
ff_rxhalfclk_ch3 => open,
ff_xmit_ch3 => "00", -- UNKNOWN
ff_rx_even_ch3 => open, -- UNKNOWN
- ff_correct_disp_ch3 => "00",
+ ff_correct_disp_ch3 => tx_correct(1 downto 0),
ff_disp_err_ch3 => link_error(0)(9 downto 8),
ff_cv_ch3 => link_error(0)(1 downto 0),
ffc_rrst_ch3 => '0',
THE_SERDES_INPUT_PROC: process( SYSCLK )
begin
if( rising_edge(SYSCLK) ) then
- last_fifo_tx_empty(i) <= fifo_tx_empty(i);
+ last_fifo_tx_empty(i) <= fifo_tx_empty(i);
+ first_idle(i) <= not last_fifo_tx_empty(i) and fifo_tx_empty(i);
if( (last_fifo_tx_empty(i) = '1') ) then -- or (tx_allow_qtx(i) = '0')
tx_data(i*16+15 downto i*16) <= x"50bc";
tx_k(i*2+1 downto i*2) <= "01";
+ tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0';
else
tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18+0);
tx_k(i*2+1 downto i*2) <= "00";
+ tx_correct(i*2+1 downto i*2) <= "00";
end if;
end if;
end process;
-
---------------------------------------------------------------------
--LED Signals
---------------------------------------------------------------------
attribute syn_sharing : string;
attribute syn_sharing of med_ecp_sfp : architecture is "off";
- component serdes_gbe_2
- port(
- core_txrefclk : IN std_logic;
- core_rxrefclk : IN std_logic;
- hdinp2 : IN std_logic;
- hdinn2 : IN std_logic;
- ff_rxiclk_ch2 : IN std_logic;
- ff_txiclk_ch2 : IN std_logic;
- ff_ebrd_clk_2 : IN std_logic;
- ff_txdata_ch2 : IN std_logic_vector(15 downto 0);
- ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0);
- ff_xmit_ch2 : IN std_logic_vector(1 downto 0);
- ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0);
- ffc_rrst_ch2 : IN std_logic;
- ffc_lane_tx_rst_ch2 : IN std_logic;
- ffc_lane_rx_rst_ch2 : IN std_logic;
- ffc_txpwdnb_ch2 : IN std_logic;
- ffc_rxpwdnb_ch2 : IN std_logic;
- ffc_macro_rst : IN std_logic;
- ffc_quad_rst : IN std_logic;
- ffc_trst : IN std_logic;
- hdoutp2 : OUT std_logic;
- hdoutn2 : OUT std_logic;
- ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0);
- ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0);
- ff_rxfullclk_ch2 : OUT std_logic;
- ff_rxhalfclk_ch2 : OUT std_logic;
- ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);
- ff_cv_ch2 : OUT std_logic_vector(1 downto 0);
- ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0);
- ffs_rlos_lo_ch2 : OUT std_logic;
- ffs_ls_sync_status_ch2 : OUT std_logic;
- ffs_cc_underrun_ch2 : OUT std_logic;
- ffs_cc_overrun_ch2 : OUT std_logic;
- ffs_txfbfifo_error_ch2 : OUT std_logic;
- ffs_rxfbfifo_error_ch2 : OUT std_logic;
- ffs_rlol_ch2 : OUT std_logic;
- oob_out_ch2 : OUT std_logic;
- ff_txfullclk : OUT std_logic;
- ff_txhalfclk : OUT std_logic;
- refck2core : OUT std_logic;
- ffs_plol : OUT std_logic
- );
- end component;
-
-
+ COMPONENT serdes_gbe_0_extclock
+ PORT(
+ refclkp : IN std_logic;
+ refclkn : IN std_logic;
+ hdinp0 : IN std_logic;
+ hdinn0 : IN std_logic;
+ ff_rxiclk_ch0 : IN std_logic;
+ ff_txiclk_ch0 : IN std_logic;
+ ff_ebrd_clk_0 : IN std_logic;
+ ff_txdata_ch0 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch0 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch0 : IN std_logic;
+ ffc_lane_tx_rst_ch0 : IN std_logic;
+ ffc_lane_rx_rst_ch0 : IN std_logic;
+ ffc_txpwdnb_ch0 : IN std_logic;
+ ffc_rxpwdnb_ch0 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp0 : OUT std_logic;
+ hdoutn0 : OUT std_logic;
+ ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch0 : OUT std_logic;
+ ff_rxhalfclk_ch0 : OUT std_logic;
+ ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch0 : OUT std_logic;
+ ffs_ls_sync_status_ch0 : OUT std_logic;
+ ffs_cc_underrun_ch0 : OUT std_logic;
+ ffs_cc_overrun_ch0 : OUT std_logic;
+ ffs_txfbfifo_error_ch0 : OUT std_logic;
+ ffs_rxfbfifo_error_ch0 : OUT std_logic;
+ ffs_rlol_ch0 : OUT std_logic;
+ oob_out_ch0 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ END COMPONENT;
+
+ component serdes_gbe_1
+ port(
+ core_txrefclk : IN std_logic;
+ core_rxrefclk : IN std_logic;
+ hdinp1 : IN std_logic;
+ hdinn1 : IN std_logic;
+ ff_rxiclk_ch1 : IN std_logic;
+ ff_txiclk_ch1 : IN std_logic;
+ ff_ebrd_clk_1 : IN std_logic;
+ ff_txdata_ch1 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch1 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch1 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch1 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch1 : IN std_logic;
+ ffc_lane_tx_rst_ch1 : IN std_logic;
+ ffc_lane_rx_rst_ch1 : IN std_logic;
+ ffc_txpwdnb_ch1 : IN std_logic;
+ ffc_rxpwdnb_ch1 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp1 : OUT std_logic;
+ hdoutn1 : OUT std_logic;
+ ff_rxdata_ch1 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch1 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch1 : OUT std_logic;
+ ff_rxhalfclk_ch1 : OUT std_logic;
+ ff_disp_err_ch1 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch1 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch1 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch1 : OUT std_logic;
+ ffs_ls_sync_status_ch1 : OUT std_logic;
+ ffs_cc_underrun_ch1 : OUT std_logic;
+ ffs_cc_overrun_ch1 : OUT std_logic;
+ ffs_txfbfifo_error_ch1 : OUT std_logic;
+ ffs_rxfbfifo_error_ch1 : OUT std_logic;
+ ffs_rlol_ch1 : OUT std_logic;
+ oob_out_ch1 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ end component;
+
+ component serdes_gbe_0
+ port(
+ core_txrefclk : IN std_logic;
+ core_rxrefclk : IN std_logic;
+ hdinp0 : IN std_logic;
+ hdinn0 : IN std_logic;
+ ff_rxiclk_ch0 : IN std_logic;
+ ff_txiclk_ch0 : IN std_logic;
+ ff_ebrd_clk_0 : IN std_logic;
+ ff_txdata_ch0 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch0 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch0 : IN std_logic;
+ ffc_lane_tx_rst_ch0 : IN std_logic;
+ ffc_lane_rx_rst_ch0 : IN std_logic;
+ ffc_txpwdnb_ch0 : IN std_logic;
+ ffc_rxpwdnb_ch0 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp0 : OUT std_logic;
+ hdoutn0 : OUT std_logic;
+ ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch0 : OUT std_logic;
+ ff_rxhalfclk_ch0 : OUT std_logic;
+ ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch0 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch0 : OUT std_logic;
+ ffs_ls_sync_status_ch0 : OUT std_logic;
+ ffs_cc_underrun_ch0 : OUT std_logic;
+ ffs_cc_overrun_ch0 : OUT std_logic;
+ ffs_txfbfifo_error_ch0 : OUT std_logic;
+ ffs_rxfbfifo_error_ch0 : OUT std_logic;
+ ffs_rlol_ch0 : OUT std_logic;
+ oob_out_ch0 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ end component;
+
+ component serdes_gbe_2
+ port(
+ core_txrefclk : IN std_logic;
+ core_rxrefclk : IN std_logic;
+ hdinp2 : IN std_logic;
+ hdinn2 : IN std_logic;
+ ff_rxiclk_ch2 : IN std_logic;
+ ff_txiclk_ch2 : IN std_logic;
+ ff_ebrd_clk_2 : IN std_logic;
+ ff_txdata_ch2 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch2 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch2 : IN std_logic;
+ ffc_lane_tx_rst_ch2 : IN std_logic;
+ ffc_lane_rx_rst_ch2 : IN std_logic;
+ ffc_txpwdnb_ch2 : IN std_logic;
+ ffc_rxpwdnb_ch2 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp2 : OUT std_logic;
+ hdoutn2 : OUT std_logic;
+ ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch2 : OUT std_logic;
+ ff_rxhalfclk_ch2 : OUT std_logic;
+ ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch2 : OUT std_logic;
+ ffs_ls_sync_status_ch2 : OUT std_logic;
+ ffs_cc_underrun_ch2 : OUT std_logic;
+ ffs_cc_overrun_ch2 : OUT std_logic;
+ ffs_txfbfifo_error_ch2 : OUT std_logic;
+ ffs_rxfbfifo_error_ch2 : OUT std_logic;
+ ffs_rlol_ch2 : OUT std_logic;
+ oob_out_ch2 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ end component;
+
+
+ component serdes_gbe_3
+ port(
+ core_txrefclk : IN std_logic;
+ core_rxrefclk : IN std_logic;
+ hdinp3 : IN std_logic;
+ hdinn3 : IN std_logic;
+ ff_rxiclk_ch3 : IN std_logic;
+ ff_txiclk_ch3 : IN std_logic;
+ ff_ebrd_clk_3 : IN std_logic;
+ ff_txdata_ch3 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch3 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch3 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch3 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch3 : IN std_logic;
+ ffc_lane_tx_rst_ch3 : IN std_logic;
+ ffc_lane_rx_rst_ch3 : IN std_logic;
+ ffc_txpwdnb_ch3 : IN std_logic;
+ ffc_rxpwdnb_ch3 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp3 : OUT std_logic;
+ hdoutn3 : OUT std_logic;
+ ff_rxdata_ch3 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch3 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch3 : OUT std_logic;
+ ff_rxhalfclk_ch3 : OUT std_logic;
+ ff_disp_err_ch3 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch3 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch3 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch3 : OUT std_logic;
+ ffs_ls_sync_status_ch3 : OUT std_logic;
+ ffs_cc_underrun_ch3 : OUT std_logic;
+ ffs_cc_overrun_ch3 : OUT std_logic;
+ ffs_txfbfifo_error_ch3 : OUT std_logic;
+ ffs_rxfbfifo_error_ch3 : OUT std_logic;
+ ffs_rlol_ch3 : OUT std_logic;
+ oob_out_ch3 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ end component;
signal refck2core : std_logic;
-- signal clock : std_logic;
attribute syn_keep : boolean;
attribute syn_keep of led_counter : signal is true;
+
+ signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+ signal first_idle : std_logic; -- tag the first IDLE2 after data
+
+
signal reset_i : std_logic;
signal pwr_up : std_logic;
begin
D_OUT(1) => sfp_los
);
--- Komma delimiter transfer for training phase
+
THE_RX_K_SYNC: signal_sync
generic map(
- DEPTH => 3,
+ DEPTH => 1,
WIDTH => 2
)
port map(
RESET => reset_i,
D_IN => comb_rx_k,
- CLK0 => ff_txhalfclk, -- CHANGED
+ CLK0 => sysclk, -- CHANGED
CLK1 => sysclk,
D_OUT => rx_k_q
);
--- delay line for RX_K and RX_DATA (directly from SFP to fabric logic)
THE_RX_DATA_DELAY: signal_sync
generic map(
DEPTH => 2,
port map(
RESET => reset_i,
D_IN => comb_rx_data,
- CLK0 => ff_txhalfclk, -- CHANGED
- CLK1 => ff_txhalfclk, -- CHANGED
+ CLK0 => sysclk,
+ CLK1 => sysclk,
D_OUT => rx_data
);
port map(
RESET => reset_i,
D_IN => comb_rx_k,
- CLK0 => ff_txhalfclk, -- CHANGED
- CLK1 => ff_txhalfclk, -- CHANGED
+ CLK0 => sysclk,
+ CLK1 => sysclk,
D_OUT => rx_k
);
--- Transfer for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync -- really needed?!?
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
generic map(
DEPTH => 2,
WIDTH => 2
CLEAR => clear,
SFP_MISSING_IN => sfp_prsnt_n,
SFP_LOS_IN => sfp_los,
- SD_LINK_OK_IN => link_ok(0),
+ SD_LINK_OK_IN => link_ok(0),
SD_LOS_IN => link_error(8),
SD_TXCLK_BAD_IN => link_error(5),
SD_RXCLK_BAD_IN => link_error(4),
refclk2core_out <= refck2core;
-- Instantiation of serdes module
+
+ gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES generate
+ THE_SERDES: serdes_gbe_0_extclock
+ port map(
+ refclkp => SD_REFCLK_P_IN,
+ refclkn => SD_REFCLK_N_IN,
+ hdinp0 => SD_RXD_P_IN,
+ hdinn0 => SD_RXD_N_IN,
+ ff_rxiclk_ch0 => sysclk,
+ ff_txiclk_ch0 => sysclk,
+ ff_ebrd_clk_0 => ff_txfullclk,
+ ff_txdata_ch0 => tx_data,
+ ff_tx_k_cntrl_ch0 => tx_k,
+ ff_xmit_ch0 => "00", -- UNKNOWN
+ ff_correct_disp_ch0 => tx_correct,
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch0 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp0 => sd_txd_p_out,
+ hdoutn0 => sd_txd_n_out,
+ ff_rxdata_ch0 => comb_rx_data,
+ ff_rx_k_cntrl_ch0 => comb_rx_k,
+ ff_rxfullclk_ch0 => open,
+ ff_rxhalfclk_ch0 => open,
+ ff_disp_err_ch0 => open,
+ ff_cv_ch0 => link_error(7 downto 6),
+ ff_rx_even_ch0 => open,
+ ffs_rlos_lo_ch0 => link_error(8),
+ ffs_ls_sync_status_ch0 => link_ok(0),
+ ffs_cc_underrun_ch0 => link_error(0),
+ ffs_cc_overrun_ch0 => link_error(1),
+ ffs_txfbfifo_error_ch0 => link_error(2),
+ ffs_rxfbfifo_error_ch0 => link_error(3),
+ ffs_rlol_ch0 => link_error(4),
+ oob_out_ch0 => open,
+ ff_txfullclk => ff_txfullclk,
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
+ gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO generate
+ THE_SERDES: serdes_gbe_0
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp0 => sd_rxd_p_in,
+ hdinn0 => sd_rxd_n_in,
+ ff_rxiclk_ch0 => sysclk,
+ ff_txiclk_ch0 => sysclk,
+ ff_ebrd_clk_0 => ff_txfullclk,
+ ff_txdata_ch0 => tx_data,
+ ff_tx_k_cntrl_ch0 => tx_k,
+ ff_xmit_ch0 => "00", -- UNKNOWN
+ ff_correct_disp_ch0 => tx_correct,
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch0 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp0 => sd_txd_p_out,
+ hdoutn0 => sd_txd_n_out,
+ ff_rxdata_ch0 => comb_rx_data,
+ ff_rx_k_cntrl_ch0 => comb_rx_k,
+ ff_rxfullclk_ch0 => open,
+ ff_rxhalfclk_ch0 => open,
+ ff_disp_err_ch0 => open,
+ ff_cv_ch0 => link_error(7 downto 6),
+ ff_rx_even_ch0 => open,
+ ffs_rlos_lo_ch0 => link_error(8),
+ ffs_ls_sync_status_ch0 => link_ok(0),
+ ffs_cc_underrun_ch0 => link_error(0),
+ ffs_cc_overrun_ch0 => link_error(1),
+ ffs_txfbfifo_error_ch0 => link_error(2),
+ ffs_rxfbfifo_error_ch0 => link_error(3),
+ ffs_rlol_ch0 => link_error(4),
+ oob_out_ch0 => open,
+ ff_txfullclk => ff_txfullclk,
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
+ gen_serdes_1 : if SERDES_NUM = 1 generate
+ THE_SERDES: serdes_gbe_1
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp1 => sd_rxd_p_in,
+ hdinn1 => sd_rxd_n_in,
+ ff_rxiclk_ch1 => sysclk,
+ ff_txiclk_ch1 => sysclk,
+ ff_ebrd_clk_1 => ff_txfullclk,
+ ff_txdata_ch1 => tx_data,
+ ff_tx_k_cntrl_ch1 => tx_k,
+ ff_xmit_ch1 => "00", -- UNKNOWN
+ ff_correct_disp_ch1 => tx_correct,
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch1 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp1 => sd_txd_p_out,
+ hdoutn1 => sd_txd_n_out,
+ ff_rxdata_ch1 => comb_rx_data,
+ ff_rx_k_cntrl_ch1 => comb_rx_k,
+ ff_rxfullclk_ch1 => open,
+ ff_rxhalfclk_ch1 => open,
+ ff_disp_err_ch1 => open,
+ ff_cv_ch1 => link_error(7 downto 6),
+ ff_rx_even_ch1 => open,
+ ffs_rlos_lo_ch1 => link_error(8),
+ ffs_ls_sync_status_ch1 => link_ok(0),
+ ffs_cc_underrun_ch1 => link_error(0),
+ ffs_cc_overrun_ch1 => link_error(1),
+ ffs_txfbfifo_error_ch1 => link_error(2),
+ ffs_rxfbfifo_error_ch1 => link_error(3),
+ ffs_rlol_ch1 => link_error(4),
+ oob_out_ch1 => open,
+ ff_txfullclk => ff_txfullclk,
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
gen_serdes_2 : if SERDES_NUM = 2 generate
- THE_SERDES: serdes_gbe_2
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
- hdinp2 => sd_rxd_p_in,
- hdinn2 => sd_rxd_n_in,
- ff_rxiclk_ch2 => ff_txhalfclk, -- CHANGED
- ff_txiclk_ch2 => ff_txhalfclk,
- ff_ebrd_clk_2 => ff_txfullclk, -- CHANGED
- ff_txdata_ch2 => tx_data,
- ff_tx_k_cntrl_ch2 => tx_k,
- ff_xmit_ch2 => "00", -- UNKNOWN
- ff_correct_disp_ch2 => "00",
- ffc_rrst_ch2 => '0',
- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
- ffc_lane_rx_rst_ch2 => ffc_lane_tx_rst,
- ffc_txpwdnb_ch2 => '1',
- ffc_rxpwdnb_ch2 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp2 => sd_txd_p_out,
- hdoutn2 => sd_txd_n_out,
- ff_rxdata_ch2 => comb_rx_data,
- ff_rx_k_cntrl_ch2 => comb_rx_k,
- ff_rxfullclk_ch2 => open,
- ff_rxhalfclk_ch2 => open, --ff_rxhalfclk,
- ff_disp_err_ch2 => open,
- ff_cv_ch2 => link_error(7 downto 6),
- ff_rx_even_ch2 => open, -- UNKNOWN
- ffs_rlos_lo_ch2 => link_error(8),
- ffs_ls_sync_status_ch2 => link_ok(0),
- ffs_cc_underrun_ch2 => link_error(0),
- ffs_cc_overrun_ch2 => link_error(1),
- ffs_txfbfifo_error_ch2 => link_error(2),
- ffs_rxfbfifo_error_ch2 => link_error(3),
- ffs_rlol_ch2 => link_error(4),
- oob_out_ch2 => open,
- ff_txfullclk => ff_txfullclk, -- CHANGED
- ff_txhalfclk => ff_txhalfclk,
- refck2core => refck2core,
- ffs_plol => link_error(5)
- );
+ THE_SERDES: serdes_gbe_2
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp2 => sd_rxd_p_in,
+ hdinn2 => sd_rxd_n_in,
+ ff_rxiclk_ch2 => sysclk,
+ ff_txiclk_ch2 => sysclk,
+ ff_ebrd_clk_2 => ff_txfullclk,
+ ff_txdata_ch2 => tx_data,
+ ff_tx_k_cntrl_ch2 => tx_k,
+ ff_xmit_ch2 => "00", -- UNKNOWN
+ ff_correct_disp_ch2 => tx_correct,
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch2 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp2 => sd_txd_p_out,
+ hdoutn2 => sd_txd_n_out,
+ ff_rxdata_ch2 => comb_rx_data,
+ ff_rx_k_cntrl_ch2 => comb_rx_k,
+ ff_rxfullclk_ch2 => open,
+ ff_rxhalfclk_ch2 => open,
+ ff_disp_err_ch2 => open,
+ ff_cv_ch2 => link_error(7 downto 6),
+ ff_rx_even_ch2 => open,
+ ffs_rlos_lo_ch2 => link_error(8),
+ ffs_ls_sync_status_ch2 => link_ok(0),
+ ffs_cc_underrun_ch2 => link_error(0),
+ ffs_cc_overrun_ch2 => link_error(1),
+ ffs_txfbfifo_error_ch2 => link_error(2),
+ ffs_rxfbfifo_error_ch2 => link_error(3),
+ ffs_rlol_ch2 => link_error(4),
+ oob_out_ch2 => open,
+ ff_txfullclk => ff_txfullclk,
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
+ gen_serdes_3 : if SERDES_NUM = 3 generate
+ THE_SERDES: serdes_gbe_3
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp3 => sd_rxd_p_in,
+ hdinn3 => sd_rxd_n_in,
+ ff_rxiclk_ch3 => sysclk,
+ ff_txiclk_ch3 => sysclk,
+ ff_ebrd_clk_3 => ff_txfullclk,
+ ff_txdata_ch3 => tx_data,
+ ff_tx_k_cntrl_ch3 => tx_k,
+ ff_xmit_ch3 => "00", -- UNKNOWN
+ ff_correct_disp_ch3 => tx_correct,
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch3 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp3 => sd_txd_p_out,
+ hdoutn3 => sd_txd_n_out,
+ ff_rxdata_ch3 => comb_rx_data,
+ ff_rx_k_cntrl_ch3 => comb_rx_k,
+ ff_rxfullclk_ch3 => open,
+ ff_rxhalfclk_ch3 => open,
+ ff_disp_err_ch3 => open,
+ ff_cv_ch3 => link_error(7 downto 6),
+ ff_rx_even_ch3 => open,
+ ffs_rlos_lo_ch3 => link_error(8),
+ ffs_ls_sync_status_ch3 => link_ok(0),
+ ffs_cc_underrun_ch3 => link_error(0),
+ ffs_cc_overrun_ch3 => link_error(1),
+ ffs_txfbfifo_error_ch3 => link_error(2),
+ ffs_rxfbfifo_error_ch3 => link_error(3),
+ ffs_rlol_ch3 => link_error(4),
+ oob_out_ch3 => open,
+ ff_txfullclk => ff_txfullclk,
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
--<-- ff_force_disp_ch2 => "00",
--<-- ff_disp_sel_ch2 => "00",
--->-- ff_xmit_ch2 => "00", -- UNKNOWN
--->-- ff_rx_even_ch2 => open, -- UNKNOWN
- end generate;
+-->-- ff_xmit_ch2 => "00", -- UNKNOWN
+-->-- ff_rx_even_ch2 => open, -- UNKNOWN
-------------------------------------------------------------------------
-- RX Fifo & Data output
USE_STATUS_FLAGS => c_NO
)
port map( read_clock_in => sysclk,
- write_clock_in => ff_txhalfclk, -- CHANGED
+ write_clock_in => sysclk, -- CHANGED
read_enable_in => fifo_rx_rd_en,
write_enable_in => fifo_rx_wr_en,
fifo_gsr_in => fifo_rx_reset,
fifo_rx_rd_en <= '1';
-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process( ff_txhalfclk ) -- CHANGED
+THE_BYTE_SWAP_PROC: process( sysclk ) -- CHANGED
begin
- if( rising_edge(ff_txhalfclk) ) then -- CHANGED
+ if( rising_edge(sysclk) ) then -- CHANGED
last_rx <= rx_k(1) & rx_data(15 downto 8);
if( swap_bytes = '0' ) then
fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
generic map(
USE_STATUS_FLAGS => c_NO
)
-port map( read_clock_in => ff_txhalfclk,
+port map( read_clock_in => sysclk,
write_clock_in => sysclk,
read_enable_in => fifo_tx_rd_en,
write_enable_in => fifo_tx_wr_en,
fifo_tx_rd_en <= tx_allow;
-THE_SERDES_INPUT_PROC: process( ff_txhalfclk )
+THE_SERDES_INPUT_PROC: process( sysclk )
begin
- if( rising_edge(ff_txhalfclk) ) then
- last_fifo_tx_empty <= fifo_tx_empty;
+ if( rising_edge(sysclk) ) then
+ last_fifo_tx_empty <= fifo_tx_empty;
+ first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
tx_data <= x"50bc";
tx_k <= "01";
+ tx_correct <= first_idle & '0';
-- elsif send_resync = '1' then
--- tx_data <= x"7F7F";
--- tx_k <= "00";
+-- tx_data <= x"FEFE";
+-- tx_k <= "11";
else
tx_data <= fifo_tx_dout(15 downto 0);
tx_k <= "00";
+ tx_correct <= "00";
end if;
end if;
end process THE_SERDES_INPUT_PROC;
---
-
--Generate LED signals
----------------------
rx_led <= '0';
end if;
- if tx_k(0) = '0' then -- tx_k clock domain crossing!
+ if tx_k(0) = '0' then
tx_led <= '1';
elsif led_counter = 0 then
tx_led <= '0';
stat_debug(19 downto 18) <= (others => '0');
stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
stat_debug(41 downto 24) <= (others => '0');
-stat_debug(42) <= ff_txhalfclk; -- CHANGED
-stat_debug(43) <= ff_txhalfclk; -- CHANGED
+stat_debug(42) <= sysclk; -- CHANGED
+stat_debug(43) <= sysclk; -- CHANGED
stat_debug(59 downto 44) <= (others => '0');
stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); --link_error(3 downto 0);
ONEWIRE : inout std_logic;
ONEWIRE_MONITOR_IN : in std_logic;
ONEWIRE_MONITOR_OUT : out std_logic;
+ COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
---------------------------------------------------------------------
--Usual common stat reg, trigger counters are not in use here
- HC_COMMON_STAT_REGS(19 downto 0) <= (others => '0');
+ HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0);
HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT;
- HC_COMMON_STAT_REGS(63 downto 32) <= (others => '0');
+ HC_COMMON_STAT_REGS(63 downto 32) <= COMMON_STAT_REGS(63 downto 32);
--Status Registers
buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked;
IOBUF_CTRL_GEN <= (others => '0');
--map regio registers to stat & ctrl outputs
- STAT_COMMON_STAT_REGS <= HC_COMMON_STAT_REGS;
- STAT_COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS;
+ COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS;
+ MY_ADDRESS_OUT <= HUB_ADDRESS;
STAT_REGS <= HC_STAT_REGS;
STAT_CTRL_REGS <= HC_CTRL_REGS;
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
ONEWIRE : inout std_logic;
ONEWIRE_MONITOR_IN : in std_logic;
ONEWIRE_MONITOR_OUT : out std_logic;
+ COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ component trb_net16_hub_streaming is
+ generic(
+ --hub control
+ HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
+ HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES)
+ );
+
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ --Media Interface
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+
+ --Data Output
+ --Event information coming from CTS
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_START_READOUT_OUT : out std_logic;
+ --Answer sent to CTS
+ APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_CTS_DATAREADY_IN : in std_logic;
+ APL_CTS_READ_OUT : out std_logic;
+ APL_CTS_SHORT_TRANSFER_IN : in std_logic;
+ APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_CTS_SEND_IN : in std_logic;
+ APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ -- Receiver port
+ APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_FEE_DATAREADY_OUT : out std_logic;
+ APL_FEE_READ_IN : in std_logic;
+ -- APL Control port
+ APL_CTS_RUN_OUT : out std_logic;
+ APL_FEE_RUN_OUT : out std_logic;
+ IPU_MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
+
+ COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+
+ --Fixed status and control ports
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ );
+ end component;
component trb_net16_hub_ipu_logic is
signal saved_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_number : std_logic_vector(POINT_NUMBER*3-1 downto 0);
+ signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal reply_reading_H0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F1 : std_logic_vector(POINT_NUMBER-1 downto 0);
end if;
end process;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if REPLY_DATAREADY_IN(i) = '1' and buf_REPLY_READ_OUT(i) = '1' then
+ last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) <= REPLY_PACKET_NUM_IN(i*3+2 downto i*3);
+ end if;
+ end if;
+ end process;
+
current_reply_packet_type((i+1)*3-1 downto i*3) <= REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH)
when (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH) = c_H0)
else saved_reply_packet_type((i+1)*3-1 downto i*3);
--Problematic stuff here... needing reply_packet_num_in to determine read_out ...
- PROC_auto_read_DHDR : process(current_reply_reading_DHDR, current_reply_reading_HDR, REPLY_PACKET_NUM_IN)
+ PROC_auto_read_DHDR : process(current_reply_reading_DHDR, current_reply_reading_HDR, last_REPLY_PACKET_NUM_IN)
begin
- if (current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0')
- or current_reply_reading_HDR(i) = '1' then
+ if (reg_current_reply_reading_DHDR(i) = '1' and
+ (last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = "100" or last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = "000"))
+ or reg_current_reply_reading_HDR(i) = '1' then
reg_current_reply_auto_reading_DHDR(i) <= '1';
else
reg_current_reply_auto_reading_DHDR(i) <= '0';
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+--the first media interface is always the uplink & stream output!
+
+entity trb_net16_hub_streaming is
+ generic(
+ --hub control
+ HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
+ HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES)
+ );
+
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ --Media Interface
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+
+ --Data Output
+ --Event information coming from CTS
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_START_READOUT_OUT : out std_logic;
+ --Answer sent to CTS
+ APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_CTS_DATAREADY_IN : in std_logic;
+ APL_CTS_READ_OUT : out std_logic;
+ APL_CTS_SHORT_TRANSFER_IN : in std_logic;
+ APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_CTS_SEND_IN : in std_logic;
+ APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ -- Receiver port
+ APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_FEE_DATAREADY_OUT : out std_logic;
+ APL_FEE_READ_IN : in std_logic;
+ -- APL Control port
+ APL_CTS_RUN_OUT : out std_logic;
+ APL_FEE_RUN_OUT : out std_logic;
+ IPU_MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
+
+ COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+
+ --Fixed status and control ports
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ );
+end entity;
+
+
+architecture trb_net16_hub_streaming_arch of trb_net16_hub_streaming is
+
+constant mii : integer := MII_NUMBER-1;
+
+signal hub_init_dataready_out : std_logic_vector(2 downto 0);
+signal hub_reply_dataready_out : std_logic_vector(2 downto 0);
+signal hub_init_dataready_in : std_logic_vector(2 downto 0);
+signal hub_reply_dataready_in : std_logic_vector(2 downto 0);
+
+signal hub_init_read_out : std_logic_vector(2 downto 0);
+signal hub_reply_read_out : std_logic_vector(2 downto 0);
+signal hub_init_read_in : std_logic_vector(2 downto 0);
+signal hub_reply_read_in : std_logic_vector(2 downto 0);
+
+signal hub_init_data_out : std_logic_vector(47 downto 0);
+signal hub_reply_data_out : std_logic_vector(47 downto 0);
+signal hub_init_data_in : std_logic_vector(47 downto 0);
+signal hub_reply_data_in : std_logic_vector(47 downto 0);
+
+signal hub_init_packet_num_out : std_logic_vector(8 downto 0);
+signal hub_reply_packet_num_out : std_logic_vector(8 downto 0);
+signal hub_init_packet_num_in : std_logic_vector(8 downto 0);
+signal hub_reply_packet_num_in : std_logic_vector(8 downto 0);
+
+signal cts_init_data_out : std_logic_vector(15 downto 0);
+signal cts_init_dataready_out : std_logic;
+signal cts_init_packet_num_out : std_logic_vector(2 downto 0);
+signal cts_init_read_in : std_logic;
+
+signal cts_reply_data_in : std_logic_vector(15 downto 0);
+signal cts_reply_dataready_in : std_logic;
+signal cts_reply_packet_num_in : std_logic_vector(2 downto 0);
+signal cts_reply_read_out : std_logic;
+
+signal common_ctrl : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+signal my_address : std_logic_vector(15 downto 0);
+
+signal io_dataready_out : std_logic_vector(7 downto 0);
+signal io_data_out : std_logic_vector(127 downto 0);
+signal io_packet_num_out : std_logic_vector(23 downto 0);
+signal io_read_in : std_logic_vector(7 downto 0);
+
+signal io_dataready_in : std_logic_vector(3 downto 0);
+signal io_read_out : std_logic_vector(3 downto 0);
+signal io_data_in : std_logic_vector(63 downto 0);
+signal io_packet_num_in : std_logic_vector(11 downto 0);
+signal io_error_in : std_logic_vector(2 downto 0);
+
+signal reset_i : std_logic;
+
+
+begin
+
+---------------------------------------------------------------------
+-- Reset
+---------------------------------------------------------------------
+
+
+ SYNC_RESET_MUX_IO : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reset_i <= MED_STAT_OP(14) or RESET;
+ end if;
+ end process;
+
+---------------------------------------------------------------------
+-- Connecting I/O
+---------------------------------------------------------------------
+
+ COMMON_CTRL_REGS <= common_ctrl;
+ common_stat <= COMMON_STAT_REGS;
+ MY_ADDRESS_OUT <= my_address;
+
+
+---------------------------------------------------------------------
+-- The Hub
+---------------------------------------------------------------------
+
+
+ THE_HUB : trb_net16_hub_base
+ generic map (
+ --hub control
+ HUB_CTRL_CHANNELNUM => HUB_CTRL_CHANNELNUM,
+ HUB_CTRL_DEPTH => HUB_CTRL_DEPTH,
+ HUB_USED_CHANNELS => HUB_USED_CHANNELS,
+ USE_CHECKSUM => USE_CHECKSUM,
+ USE_VENDOR_CORES => USE_VENDOR_CORES,
+ IBUF_SECURE_MODE => IBUF_SECURE_MODE,
+ INIT_ADDRESS => INIT_ADDRESS,
+ INIT_UNIQUE_ID => INIT_UNIQUE_ID,
+ COMPILE_TIME => COMPILE_TIME,
+ COMPILE_VERSION => COMPILE_VERSION,
+ HARDWARE_VERSION => HARDWARE_VERSION,
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ USE_ONEWIRE => USE_ONEWIRE,
+ MII_NUMBER => MII_NUMBER,
+ MII_IBUF_DEPTH => MII_IBUF_DEPTH,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ INT_NUMBER => 3,
+ INT_CHANNELS => (0=>0,1=>1,2=>3,others=>0)
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ --Media interfacces
+ MED_DATAREADY_OUT => med_dataready_out(mii downto 1),
+ MED_DATA_OUT => med_data_out(mii*16+15 downto 16),
+ MED_PACKET_NUM_OUT=> med_packet_num_out(mii*3+2 downto 3),
+ MED_READ_IN => med_read_in(mii downto 1),
+ MED_DATAREADY_IN => med_dataready_in(mii downto 1),
+ MED_DATA_IN => med_data_in(mii*16+15 downto 16),
+ MED_PACKET_NUM_IN => med_packet_num_in(mii*3+2 downto 3),
+ MED_READ_OUT => med_read_out(mii downto 1),
+ MED_STAT_OP => med_stat_op(mii*16+15 downto 16),
+ MED_CTRL_OP => med_ctrl_op(mii*16+15 downto 16),
+
+ INT_INIT_DATAREADY_OUT => hub_init_dataready_out,
+ INT_INIT_DATA_OUT => hub_init_data_out,
+ INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_out,
+ INT_INIT_READ_IN => hub_init_read_in,
+ INT_INIT_DATAREADY_IN => hub_init_dataready_in,
+ INT_INIT_DATA_IN => hub_init_data_in,
+ INT_INIT_PACKET_NUM_IN => hub_init_packet_num_in,
+ INT_INIT_READ_OUT => hub_init_read_in,
+ INT_REPLY_DATAREADY_OUT => hub_reply_dataready_out,
+ INT_REPLY_DATA_OUT => hub_reply_data_out,
+ INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_out,
+ INT_REPLY_READ_IN => hub_reply_read_in,
+ INT_REPLY_DATAREADY_IN => hub_reply_dataready_in,
+ INT_REPLY_DATA_IN => hub_reply_data_in,
+ INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_in,
+ INT_REPLY_READ_OUT => hub_reply_read_out,
+
+ ONEWIRE => ONEWIRE,
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
+ MY_ADDRESS_OUT => my_address,
+ COMMON_CTRL_REGS => common_ctrl,
+ COMMON_STAT_REGS => common_stat,
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------
+-- I/O Buffers
+---------------------------------------------------------------------
+
+ THE_IOBUF_0 : trb_net16_iobuf
+ generic map(
+ IBUF_DEPTH => 6,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(0),
+ USE_CHECKSUM => cfg_USE_CHECKSUM(0),
+ INIT_CAN_SEND_DATA => c_NO,
+ INIT_CAN_RECEIVE_DATA => c_YES,
+ REPLY_CAN_SEND_DATA => c_YES,
+ REPLY_CAN_RECEIVE_DATA => c_NO
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => io_dataready_out(0),
+ MED_INIT_DATA_OUT => io_data_out(15 downto 0),
+ MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0),
+ MED_INIT_READ_IN => io_read_in(0),
+
+ MED_REPLY_DATAREADY_OUT => io_dataready_out(1),
+ MED_REPLY_DATA_OUT => io_data_out(31 downto 16),
+ MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(5 downto 3),
+ MED_REPLY_READ_IN => io_read_in(1),
+
+ MED_DATAREADY_IN => io_dataready_in(0),
+ MED_DATA_IN => io_data_in(15 downto 0),
+ MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0),
+ MED_READ_OUT => io_read_out(0),
+ MED_ERROR_IN => io_error_in,
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => hub_init_dataready_in(0),
+ INT_INIT_DATA_OUT => hub_init_data_in(15 downto 0),
+ INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(2 downto 0),
+ INT_INIT_READ_IN => hub_init_read_out(0),
+
+ INT_INIT_DATAREADY_IN => hub_init_dataready_out(0),
+ INT_INIT_DATA_IN => hub_init_data_out(15 downto 0),
+ INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(2 downto 0),
+ INT_INIT_READ_OUT => hub_init_read_in(0),
+
+ INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(0),
+ INT_REPLY_DATA_OUT => hub_reply_data_in(15 downto 0),
+ INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(2 downto 0),
+ INT_REPLY_READ_IN => hub_reply_read_out(0),
+
+ INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(0),
+ INT_REPLY_DATA_IN => hub_reply_data_out(15 downto 0),
+ INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(2 downto 0),
+ INT_REPLY_READ_OUT => hub_reply_read_in(0),
+
+ -- Status and control port
+ STAT_GEN => open,
+ STAT_IBUF_BUFFER => open,
+ CTRL_GEN => (others => '0'),
+ STAT_INIT_OBUF_DEBUG => open,
+ STAT_REPLY_OBUF_DEBUG => open
+ );
+
+
+ THE_IOBUF_1 : trb_net16_iobuf
+ generic map(
+ IBUF_DEPTH => 6,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
+ USE_CHECKSUM => cfg_USE_CHECKSUM(1),
+ INIT_CAN_SEND_DATA => c_NO,
+ INIT_CAN_RECEIVE_DATA => c_YES,
+ REPLY_CAN_SEND_DATA => c_YES,
+ REPLY_CAN_RECEIVE_DATA => c_NO
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => io_dataready_out(4),
+ MED_INIT_DATA_OUT => io_data_out(47 downto 32),
+ MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
+ MED_INIT_READ_IN => io_read_in(4),
+
+ MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
+ MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
+ MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9),
+ MED_REPLY_READ_IN => io_read_in(3),
+
+ MED_DATAREADY_IN => io_dataready_in(1),
+ MED_DATA_IN => io_data_in(31 downto 16),
+ MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
+ MED_READ_OUT => io_read_out(1),
+ MED_ERROR_IN => io_error_in,
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => cts_init_dataready_out,
+ INT_INIT_DATA_OUT => cts_init_data_out,
+ INT_INIT_PACKET_NUM_OUT => cts_init_packet_num_out,
+ INT_INIT_READ_IN => cts_init_read_in,
+
+ INT_INIT_DATAREADY_IN => '0',
+ INT_INIT_DATA_IN => (others => '0'),
+ INT_INIT_PACKET_NUM_IN => (others => '0'),
+ INT_INIT_READ_OUT => open,
+
+ INT_REPLY_DATAREADY_OUT => open,
+ INT_REPLY_DATA_OUT => open,
+ INT_REPLY_PACKET_NUM_OUT => open,
+ INT_REPLY_READ_IN => '1',
+
+ INT_REPLY_DATAREADY_IN => cts_reply_dataready_in,
+ INT_REPLY_DATA_IN => cts_reply_data_in,
+ INT_REPLY_PACKET_NUM_IN => cts_reply_packet_num_in,
+ INT_REPLY_READ_OUT => cts_reply_read_out,
+
+ -- Status and control port
+ STAT_GEN => open,
+ STAT_IBUF_BUFFER => open,
+ CTRL_GEN => (others => '0'),
+ STAT_INIT_OBUF_DEBUG => open,
+ STAT_REPLY_OBUF_DEBUG => open
+ );
+
+ THE_IOBUF_2 : trb_net16_term_buf
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => io_dataready_out(4),
+ MED_INIT_DATA_OUT => io_data_out(79 downto 64),
+ MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12),
+ MED_INIT_READ_IN => io_read_in(4),
+ MED_REPLY_DATAREADY_OUT => io_dataready_out(5),
+ MED_REPLY_DATA_OUT => io_data_out(95 downto 80),
+ MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15),
+ MED_REPLY_READ_IN => io_read_in(5),
+ MED_DATAREADY_IN => io_dataready_in(2),
+ MED_DATA_IN => io_dataready_in(47 downto 31),
+ MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6),
+ MED_READ_OUT => io_read_out(2)
+ );
+
+ THE_IOBUF_3 : trb_net16_iobuf
+ generic map(
+ IBUF_DEPTH => 6,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3),
+ USE_CHECKSUM => cfg_USE_CHECKSUM(3),
+ INIT_CAN_SEND_DATA => c_NO,
+ INIT_CAN_RECEIVE_DATA => c_YES,
+ REPLY_CAN_SEND_DATA => c_YES,
+ REPLY_CAN_RECEIVE_DATA => c_NO
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => io_dataready_out(6),
+ MED_INIT_DATA_OUT => io_data_out(111 downto 96),
+ MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18),
+ MED_INIT_READ_IN => io_read_in(6),
+
+ MED_REPLY_DATAREADY_OUT => io_dataready_out(7),
+ MED_REPLY_DATA_OUT => io_data_out(127 downto 112),
+ MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21),
+ MED_REPLY_READ_IN => io_read_in(7),
+
+ MED_DATAREADY_IN => io_dataready_in(3),
+ MED_DATA_IN => io_data_in(63 downto 48),
+ MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9),
+ MED_READ_OUT => io_read_out(3),
+ MED_ERROR_IN => io_error_in,
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => hub_init_dataready_in(2),
+ INT_INIT_DATA_OUT => hub_init_data_in(47 downto 32),
+ INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(8 downto 6),
+ INT_INIT_READ_IN => hub_init_read_out(2),
+
+ INT_INIT_DATAREADY_IN => hub_init_dataready_out(2),
+ INT_INIT_DATA_IN => hub_init_data_out(47 downto 32),
+ INT_INIT_PACKET_NUM_IN => hub_init_packet_num_out(8 downto 6),
+ INT_INIT_READ_OUT => hub_init_read_in(2),
+
+ INT_REPLY_DATAREADY_OUT => hub_reply_dataready_in(2),
+ INT_REPLY_DATA_OUT => hub_reply_data_in(47 downto 32),
+ INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_in(8 downto 6),
+ INT_REPLY_READ_IN => hub_reply_read_out(2),
+
+ INT_REPLY_DATAREADY_IN => hub_reply_dataready_out(2),
+ INT_REPLY_DATA_IN => hub_reply_data_out(47 downto 32),
+ INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(8 downto 6),
+ INT_REPLY_READ_OUT => hub_reply_read_in(2),
+
+ -- Status and control port
+ STAT_GEN => open,
+ STAT_IBUF_BUFFER => open,
+ CTRL_GEN => (others => '0'),
+ STAT_INIT_OBUF_DEBUG => open,
+ STAT_REPLY_OBUF_DEBUG => open
+ );
+
+---------------------------------------------------------------------
+-- Multiplexer
+---------------------------------------------------------------------
+ MPLEX: trb_net16_io_multiplexer
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN(0),
+ MED_DATA_IN => MED_DATA_IN(15 downto 0),
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(2 downto 0),
+ MED_READ_OUT => MED_READ_OUT(0),
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT(0),
+ MED_DATA_OUT => MED_DATA_OUT(15 downto 0),
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(2 downto 0),
+ MED_READ_IN => MED_READ_IN(0),
+ INT_DATAREADY_OUT => io_dataready_in,
+ INT_DATA_OUT => io_data_in,
+ INT_PACKET_NUM_OUT => io_packet_num_in,
+ INT_READ_IN => io_read_out,
+ INT_DATAREADY_IN => io_dataready_out,
+ INT_DATA_IN => io_data_out,
+ INT_PACKET_NUM_IN => io_packet_num_out,
+ INT_READ_OUT => io_read_out,
+ CTRL => (others => '0'),
+ STAT => open
+ );
+ io_error_in <= MED_STAT_OP(2 downto 0);
+
+---------------------------------------------------------------------
+-- IPU Channel
+---------------------------------------------------------------------
+
+ hub_reply_data_in(31 downto 16) <= (others => '0');
+ hub_reply_packet_num_in(5 downto 3) <= (others => '0');
+ hub_reply_dataready_in(1) <= '0';
+ hub_init_read_in(1) <= '1';
+
+ THE_STREAMING : trb_net16_api_ipu_streaming
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+
+ -- Internal direction port
+
+ FEE_INIT_DATA_OUT => hub_init_data_in(31 downto 16),
+ FEE_INIT_DATAREADY_OUT => hub_init_dataready_in(1),
+ FEE_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(5 downto 3),
+ FEE_INIT_READ_IN => hub_init_read_out(1),
+
+ FEE_REPLY_DATA_IN => hub_reply_data_out(31 downto 16),
+ FEE_REPLY_DATAREADY_IN => hub_reply_dataready_out(1),
+ FEE_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(5 downto 3),
+ FEE_REPLY_READ_OUT => hub_reply_read_in(1),
+
+ CTS_INIT_DATA_IN => cts_init_data_out,
+ CTS_INIT_DATAREADY_IN => cts_init_dataready_out,
+ CTS_INIT_PACKET_NUM_IN => cts_init_packet_num_out,
+ CTS_INIT_READ_OUT => cts_init_read_in,
+
+ CTS_REPLY_DATA_OUT => cts_reply_data_in,
+ CTS_REPLY_DATAREADY_OUT => cts_reply_dataready_in,
+ CTS_REPLY_PACKET_NUM_OUT => cts_reply_packet_num_in,
+ CTS_REPLY_READ_IN => cts_reply_read_out,
+
+ --Event information coming from CTS
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_CODE_OUT => IPU_CODE_OUT,
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+
+ --Answer sent to CTS
+ APL_CTS_DATA_IN => APL_CTS_DATA_IN,
+ APL_CTS_PACKET_NUM_IN => APL_CTS_PACKET_NUM_IN,
+ APL_CTS_DATAREADY_IN => APL_CTS_DATAREADY_IN,
+ APL_CTS_READ_OUT => APL_CTS_READ_OUT,
+ APL_CTS_SHORT_TRANSFER_IN => APL_CTS_SHORT_TRANSFER_IN,
+ APL_CTS_DTYPE_IN => APL_CTS_DTYPE_IN,
+ APL_CTS_ERROR_PATTERN_IN => APL_CTS_ERROR_PATTERN_IN,
+ APL_CTS_SEND_IN => APL_CTS_SEND_IN,
+ APL_CTS_LENGTH_IN => APL_CTS_LENGTH_IN,
+
+ -- Receiver port
+ APL_FEE_DATA_OUT => APL_FEE_DATA_OUT,
+ APL_FEE_PACKET_NUM_OUT => APL_FEE_PACKET_NUM_OUT,
+ APL_FEE_TYP_OUT => APL_FEE_TYP_OUT,
+ APL_FEE_DATAREADY_OUT => APL_FEE_DATAREADY_OUT,
+ APL_FEE_READ_IN => APL_FEE_READ_IN,
+
+ -- APL Control port
+ APL_CTS_RUN_OUT => APL_CTS_RUN_OUT,
+ APL_FEE_RUN_OUT => APL_FEE_RUN_OUT,
+
+ MY_ADDRESS_IN => IPU_MY_ADDRESS_IN,
+ CTRL_SEQNR_RESET => common_ctrl(10)
+
+ );
+
+
+
+
+end architecture;
\ No newline at end of file
------------------------
--the input fifo
------------------------
- FIFO: trb_net16_fifo
+ THE_FIFO: trb_net16_fifo
generic map (
DEPTH => DEPTH
)
+ component trb_net16_api_ipu_streaming is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Internal direction port
+
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ FEE_INIT_DATAREADY_OUT : out std_logic;
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ FEE_INIT_READ_IN : in std_logic;
+
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ FEE_REPLY_DATAREADY_IN : in std_logic;
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ FEE_REPLY_READ_OUT : out std_logic;
+
+ CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ CTS_INIT_DATAREADY_IN : in std_logic;
+ CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ CTS_INIT_READ_OUT : out std_logic;
+
+ CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ CTS_REPLY_DATAREADY_OUT : out std_logic;
+ CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ CTS_REPLY_READ_IN : in std_logic;
+
+ --Event information coming from CTS
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_START_READOUT_OUT : out std_logic;
+
+ --Answer sent to CTS
+ APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_CTS_DATAREADY_IN : in std_logic;
+ APL_CTS_READ_OUT : out std_logic;
+ APL_CTS_SHORT_TRANSFER_IN : in std_logic;
+ APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_CTS_SEND_IN : in std_logic;
+ APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+
+ -- Receiver port
+ APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_FEE_DATAREADY_OUT : out std_logic;
+ APL_FEE_READ_IN : in std_logic;
+
+ -- APL Control port
+ APL_CTS_RUN_OUT : out std_logic;
+ APL_FEE_RUN_OUT : out std_logic;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic
+
+ );
+ end component;
+
+
when READ_READ_ROM =>
inc_bitcounter <= '1';
if bitcounter_vector(6) = '1' then --read 64 bit
- next_state <= START;
+ next_state <= IDLE;
if USE_TEMPERATURE_READOUT = 1 then
next_send_rom <= '0';
next_conv_temp <= '1';
next_strong_pullup <= '1';
end if;
if is_time_reached(timecounter,130000000,CLK_PERIOD) = '1' then
- next_state <= START;
+ next_state <= IDLE;
if USE_TEMPERATURE_READOUT = 1 then
next_conv_temp <= '0';
next_reading_temp <= '1';
i := 0;
if period = 10 then
case time is
- when 130000000 => if t(27) = '1' then i := 1; end if;
+ when 1300000000 => if t(27) = '1' then i := 1; end if;
when 640000 => if t(16) = '1' then i := 1; end if;
when 80000 => if t(13) = '1' then i := 1; end if;
when 10000 => if t(10) = '1' then i := 1; end if;
when 1200 => if t(7) = '1' then i := 1; end if;
- when others => if timer = time/period then i := 1; end if;
+ when others => if timer >= time/period then i := 1; end if;
end case;
else
if timer = time/period then i := 1; end if;
jspc29 / trbnet.git / commitdiff