APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
APL_READ_IN : in std_logic; -- Read data word
-
+
-- APL Control port
APL_RUN_OUT : out std_logic; -- Data transfer is running
APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
+
-- Internal direction port
-- the ports with master or slave in their name are to be mapped by the active api
-- to the init respectivly the reply path and vice versa in the passive api.
signal fifo_to_int_read : std_logic;
signal fifo_to_int_full : std_logic;
signal fifo_to_int_empty : std_logic;
-
+
-- signals for the INT to APL:
signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal fifo_to_apl_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0);
-
+
type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB);
signal out_select: OUTPUT_SELECT;
signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT,
INT_DATA_OUT => INT_SLAVE_DATA_OUT,
INT_PACKET_NUM_OUT=> INT_SLAVE_PACKET_NUM_OUT,
- INT_READ_IN => INT_SLAVE_READ_IN,
+ INT_READ_IN => INT_SLAVE_READ_IN,
INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN,
INT_DATA_IN => INT_MASTER_DATA_IN,
INT_PACKET_NUM_IN => INT_MASTER_PACKET_NUM_IN,
EMPTY_OUT => fifo_to_int_empty
);
end generate;
-
+
CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate
FIFO_TO_INT: trb_net16_dummy_fifo
port map (
SYN_PACKET_NUM_OUT => buf_INT_MASTER_PACKET_NUM_OUT,
SYN_READ_IN => INT_MASTER_READ_IN
);
-
+
process(CLK)
begin
if rising_edge(CLK) then
---------------------------------------
---state machine for direction to APL
+--state machine for direction to APL
---------------------------------------
to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty,
fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT,
next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter));
if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer
update_registered_trailer <= '1';
- if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then
+ if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then
next_state_to_int <= SEND_TRAILER; -- immediate stop
else
next_state_to_int <= SHUTDOWN; -- send rest of data / padding
---------------------------------------
---
+--
---------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if slave_start = '1' then
endpoint_reached <= '1';
- elsif master_end = '1' then
+ elsif master_end = '1' or RESET = '1' then
endpoint_reached <= '0';
end if;
end if;
combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR
combined_header_F3(3 downto 0) <= APL_DTYPE_IN;
combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16);
- combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached;
+ combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else
+ APL_ERROR_PATTERN_IN(15 downto 0);
combined_trailer_F3(15 downto 14) <= (others => '0'); -- res.
combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS
combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR
--set to 0 for each unused bit in a register
SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
--no data / address out?
- SCTR_USE_DATA_PORT : std_logic := '0';
+ SCTR_USE_DATA_PORT : integer := c_NO;
SCTR_USE_1WIRE_INTERFACE : integer := c_YES;
SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
CLK_EN : in std_logic;
-- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);
+ MED_STAT_OP : in std_logic_vector (15 downto 0);
+ MED_CTRL_OP : out std_logic_vector (15 downto 0);
-- LVL1 trigger APL
LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
LVL1_RELEASE_IN : in std_logic;
-- IPU-Data Channel APL
- IPUD_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- IPUD_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- IPUD_APL_DATAREADY_IN: in std_logic;
- IPUD_APL_READ_OUT: out std_logic;
+ IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ IPUD_APL_DATAREADY_IN : in std_logic;
+ IPUD_APL_READ_OUT : out std_logic;
IPUD_APL_SHORT_TRANSFER_IN: in std_logic;
- IPUD_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
- IPUD_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0);
- IPUD_APL_SEND_IN: in std_logic;
+ IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ IPUD_APL_SEND_IN : in std_logic;
IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0);
- IPUD_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- IPUD_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- IPUD_APL_TYP_OUT: out std_logic_vector (2 downto 0);
- IPUD_APL_DATAREADY_OUT: out std_logic;
- IPUD_APL_READ_IN: in std_logic;
- IPUD_APL_RUN_OUT: out std_logic;
- IPUD_APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- IPU-Data Channel APL
- LVL2_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_DATAREADY_IN: in std_logic;
- LVL2_APL_READ_OUT: out std_logic;
+ IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ IPUD_APL_DATAREADY_OUT : out std_logic;
+ IPUD_APL_READ_IN : in std_logic;
+ IPUD_APL_RUN_OUT : out std_logic;
+ IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- LVL2-Data Channel APL
+ LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ LVL2_APL_DATAREADY_IN : in std_logic;
+ LVL2_APL_READ_OUT : out std_logic;
LVL2_APL_SHORT_TRANSFER_IN: in std_logic;
- LVL2_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
- LVL2_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0);
- LVL2_APL_SEND_IN: in std_logic;
+ LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ LVL2_APL_SEND_IN : in std_logic;
LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0);
- LVL2_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_TYP_OUT: out std_logic_vector (2 downto 0);
- LVL2_APL_DATAREADY_OUT: out std_logic;
- LVL2_APL_READ_IN: in std_logic;
- LVL2_APL_RUN_OUT: out std_logic;
- LVL2_APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ LVL2_APL_DATAREADY_OUT : out std_logic;
+ LVL2_APL_READ_IN : in std_logic;
+ LVL2_APL_RUN_OUT : out std_logic;
+ LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-- Slow Control Data Port
SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
SCTR_IDRAM_WR_IN : in std_logic;
SCTR_ONEWIRE_INOUT : inout std_logic;
-
+ --Additional r/w access to ctrl registers
+ SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ SCTR_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ SCTR_EXT_REG_WRITE_IN : in std_logic := '0';
+ SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0');
-- Status
- STAT_GEN_1: out std_logic_vector (31 downto 0); -- General Status
- STAT_GEN_2: out std_logic_vector (31 downto 0) -- General Status
+ MPLEX_CTRL : in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0);
+ STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0);
+ STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status
+ STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN : in std_logic_vector (4*32-1 downto 0)
);
end entity;
+
+
+
+
architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is
component trb_net_onewire is
generic (
REGISTER_WIDTH : integer range 32 to 32 := 32;
ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
+ NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
--standard values for output registers
INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
--set to 0 for each unused bit in a register
USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
(others => '1');
- --no data / address out?
- NO_DAT_PORT : std_logic := '0';
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
API_SEND_OUT : out std_logic;
API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ -- Receiver port
API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
API_TYP_IN : in std_logic_vector (2 downto 0);
API_DATAREADY_IN : in std_logic;
API_READ_OUT : out std_logic;
+ -- APL Control port
API_RUN_IN : in std_logic;
API_SEQNR_IN : in std_logic_vector (7 downto 0);
- --Port to write Unique ID
+
+ --Port to write Unique ID
IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
IDRAM_WR_IN : in std_logic;
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
--Custom Register in / out
REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when no internal register is accessed
+ --Internal Data Port
DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
DAT_READ_ENABLE_OUT : out std_logic;
DAT_WRITE_ENABLE_OUT: out std_logic;
DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ --Data input can only be used as reaction on read or write access. write operation should return data
+ --if successful
DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
DAT_DATAREADY_IN : in std_logic;
DAT_NO_MORE_DATA_IN : in std_logic;
+ --finish transmission, when reading from a fifo and it got empty
+ --Additional write access to ctrl registers
+ EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
+ EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXT_REG_WRITE_IN : in std_logic;
+ EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
STAT : out std_logic_vector(31 downto 0)
);
end component;
signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal MPLEX_CTRL : std_logic_vector(31 downto 0);
signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0);
signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
);
end generate;
gentrgapi : if i = 0 generate
+ apl_to_buf_INIT_DATAREADY(0) <= '0';
+ apl_to_buf_INIT_DATA(15 downto 0) <= (others => '0');
+ apl_to_buf_INIT_PACKET_NUM(1 downto 0) <= "00";
+ buf_to_apl_REPLY_READ(0) <= '1';
trglvl1 : trb_net16_term
generic map(
USE_APL_PORT => c_YES,
LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1);
buf_APL_READ_IN(0) <= IPUD_APL_READ_IN;
buf_APL_READ_IN(1) <= LVL2_APL_READ_IN;
+ IPUD_APL_TYP_OUT <= buf_APL_TYP_OUT(2 downto 0);
+ LVL2_APL_TYP_OUT <= buf_APL_TYP_OUT(5 downto 3);
buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN;
buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN;
--set to 0 for each unused bit in a register
USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK,
--no data / address out?
- NO_DAT_PORT => SCTR_USE_DATA_PORT,
+ USE_DAT_PORT => SCTR_USE_DATA_PORT,
INIT_ADDRESS => SCTR_INIT_ADDRESS,
INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID,
COMPILE_TIME => SCTR_COMPILE_TIME,
DAT_DATA_IN => SCTR_DATA_IN,
DAT_DATAREADY_IN => SCTR_DATAREADY_IN,
DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN,
+ EXT_REG_DATA_IN => SCTR_EXT_REG_DATA_IN,
+ EXT_REG_DATA_OUT => SCTR_EXT_REG_DATA_OUT,
+ EXT_REG_WRITE_IN => SCTR_EXT_REG_WRITE_IN,
+ EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN,
STAT => SCTR_REGIO_STAT
);
buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0);
buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32);
+ SCTR_IDRAM_DATA_OUT <= (others => '0');
+
onewire_interface : trb_net_onewire
generic map(
USE_TEMPERATURE_READOUT => c_YES,
CTRL => MPLEX_CTRL
);
+
+buf_STAT_CTRL_INIT_BUFFER <= STAT_CTRL_INIT_BUFFER;
+buf_CTRL_GEN <= CTRL_GEN;
+STAT_GEN_1 <= (others => '0');
+STAT_GEN_2 <= (others => '0');
+
end architecture;
MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
--API: interfaces
- APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
- APL_DATAREADY_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_READ_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
+ APL_DATAREADY_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_READ_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
APL_SHORT_TRANSFER_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_DTYPE_IN : in std_logic_vector (VAL(API_NUMBER*4) downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (VAL(API_NUMBER*32) downto 0);
- APL_SEND_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_DTYPE_IN : in std_logic_vector (VAL(API_NUMBER*4) downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (VAL(API_NUMBER*32) downto 0);
+ APL_SEND_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
APL_TARGET_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
- APL_DATA_OUT : out std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
- APL_PACKET_NUM_OUT: out std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
- APL_TYP_OUT : out std_logic_vector (VAL(API_NUMBER*3) downto 0);
- APL_DATAREADY_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_READ_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_RUN_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
- APL_MY_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
- APL_SEQNR_OUT : out std_logic_vector (VAL(API_NUMBER*8) downto 0);
+ APL_DATA_OUT : out std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
+ APL_TYP_OUT : out std_logic_vector (VAL(API_NUMBER*3) downto 0);
+ APL_DATAREADY_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_READ_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_RUN_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_MY_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (VAL(API_NUMBER*8) downto 0);
--TRG interfaces
TRG_GOT_TRIGGER_OUT : out std_logic_vector (VAL(TRG_NUMBER) downto 0);
TRG_ERROR_PATTERN_OUT : out std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ --Additional access to registers
+ REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0);
+ REGIO_EXT_REG_WRITE_IN: in std_logic;
+ REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
--Debugging registers
STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
end component;
component trb_net16_regIO is
- generic (
- REGISTER_WIDTH : integer range 32 to 32 := 32;
- ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
- --no data / address out?
- NO_DAT_PORT : std_logic := '0';
-
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- --Port to write Unique ID
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
-
-
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
-
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
-
- --following ports only used when no internal register is accessed
- DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
- --Data input can only be used as reaction on read or write access. write operation should return data
- --if successful
- DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- --To finish transmission, when reading from a fifo and it got empty
- STAT : out std_logic_vector(31 downto 0)
- );
+ generic (
+ REGISTER_WIDTH : integer range 32 to 32 := 32;
+ ADDRESS_WIDTH : integer range 8 to 16 := 16;
+ NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
+ NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
+ --standard values for output registers
+ INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
+ (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ --set to 0 for each unused bit in a register
+ USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
+ (others => '1');
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Port to API
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ API_DATAREADY_OUT : out std_logic;
+ API_READ_IN : in std_logic;
+ API_SHORT_TRANSFER_OUT : out std_logic;
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ API_SEND_OUT : out std_logic;
+ API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ -- Receiver port
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ API_TYP_IN : in std_logic_vector (2 downto 0);
+ API_DATAREADY_IN : in std_logic;
+ API_READ_OUT : out std_logic;
+ -- APL Control port
+ API_RUN_IN : in std_logic;
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);
+
+ --Port to write Unique ID
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
+ IDRAM_WR_IN : in std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+
+ --Common Register in / out
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ --Custom Register in / out
+ REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
+ REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+ --Internal Data Port
+ DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+ DAT_READ_ENABLE_OUT : out std_logic;
+ DAT_WRITE_ENABLE_OUT: out std_logic;
+ DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ --Data input can only be used as reaction on read or write access. write operation should return data
+ --if successful
+ DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ DAT_DATAREADY_IN : in std_logic;
+ DAT_NO_MORE_DATA_IN : in std_logic;
+ --finish transmission, when reading from a fifo and it got empty
+ --Additional write access to ctrl registers
+ EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
+ EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXT_REG_WRITE_IN : in std_logic;
+ EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+
end component;
component trb_net16_term_buf is
USED_CTRL_REGS => "01111111",
USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
- NO_DAT_PORT => '1',
+ USE_DAT_PORT => c_NO,
INIT_ADDRESS => INIT_ADDRESS,
INIT_UNIQUE_ID => INIT_UNIQUE_ID,
COMPILE_TIME => COMPILE_TIME,
DAT_DATA_OUT => open,
DAT_DATA_IN => x"00000000",
DAT_DATAREADY_IN => '0',
- DAT_NO_MORE_DATA_IN => '0'
+ DAT_NO_MORE_DATA_IN => '0',
+ EXT_REG_DATA_IN => REGIO_EXT_REG_DATA_IN,
+ EXT_REG_WRITE_IN => REGIO_EXT_REG_WRITE_IN,
+ EXT_REG_ADDR_IN => REGIO_EXT_REG_ADDR_IN,
+ EXT_REG_DATA_OUT => REGIO_EXT_REG_DATA_OUT
);
onewire_interface : trb_net_onewire
MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
MED_DATA_OUT <= buf_MED_DATA_OUT;
- process(current_NOP_word, SEND_ACK, current_ACK_word, transfer_counter, MED_READ_IN)
+ process(current_NOP_word, SEND_ACK, current_ACK_word, transfer_counter, MED_READ_IN,reg_SEND_ACK_IN)
begin
next_MED_DATA_OUT <= current_NOP_word;
next_MED_DATAREADY_OUT <= '0';
generic (
REGISTER_WIDTH : integer range 32 to 32 := 32;
ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
+ NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
--standard values for output registers
INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
--set to 0 for each unused bit in a register
USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
(others => '1');
- --no data / address out?
- NO_DAT_PORT : std_logic := '0';
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
IDRAM_WR_IN : in std_logic;
-
-
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
--Common Register in / out
COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-
--Custom Register in / out
REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when no internal register is accessed
+ --Internal Data Port
DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
DAT_READ_ENABLE_OUT : out std_logic;
DAT_WRITE_ENABLE_OUT: out std_logic;
DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
DAT_DATAREADY_IN : in std_logic;
DAT_NO_MORE_DATA_IN : in std_logic;
- --To finish transmission, when reading from a fifo and it got empty
+ --finish transmission, when reading from a fifo and it got empty
+ --Additional write access to ctrl registers
+ EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
+ EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXT_REG_WRITE_IN : in std_logic;
+ EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
STAT : out std_logic_vector(31 downto 0)
);
end entity;
);
end component;
- type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER,
- MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV);
+ type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE,
+ MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,MEM_START_READ);
signal current_state, next_state : fsm_state_t;
signal HDR_F1, HDR_F2, HDR_F3 : std_logic_vector(15 downto 0);
signal next_HDR_F1, next_HDR_F2, next_HDR_F3 : std_logic_vector(15 downto 0);
signal next_address, address : std_logic_vector(15 downto 0) := x"0000";
signal next_operation, saved_operation : std_logic_vector(3 downto 0);
- signal buf_API_READ_OUT, next_API_READ_OUT : std_logic;
- signal buf_API_SEND_OUT, next_API_SEND_OUT : std_logic;
- signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
- signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_API_READ_OUT : std_logic;
+ signal buf_API_SEND_OUT, next_API_SEND_OUT : std_logic;
+ signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(15 downto 0);
signal buf_API_SHORT_TRANSFER_OUT, next_API_SHORT_TRANSFER_OUT : std_logic;
- signal buf_API_DATAREADY_OUT, next_API_DATAREADY_OUT : std_logic;
+ signal buf_API_DATAREADY_OUT, next_API_DATAREADY_OUT : std_logic;
signal buf_DAT_DATA_OUT : std_logic_vector(REGISTER_WIDTH-1 downto 0);
+ signal buf_DAT_DATA_IN : std_logic_vector(REGISTER_WIDTH-1 downto 0);
+
signal buf_DAT_READ_ENABLE_OUT, next_DAT_READ_ENABLE_OUT : std_logic;
signal buf_DAT_WRITE_ENABLE_OUT, next_DAT_WRITE_ENABLE_OUT : std_logic;
signal buf_DAT_ADDR_OUT : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal next_COMMON_REGISTERS_OUT_write_enable: std_logic_vector(std_COMCTRLREG - 1 downto 0);
signal COMMON_REGISTERS_OUT_write_enable : std_logic_vector(std_COMCTRLREG - 1 downto 0);
signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(REGISTER_WIDTH*std_COMCTRLREG-1 downto 0);
- signal state_bits : std_logic_vector(2 downto 0);
+ signal state_bits : std_logic_vector(3 downto 0);
signal ADR_SEND_OUT : std_logic;
signal ADR_DATAREADY_IN : std_logic;
signal ADR_DATAREADY_OUT : std_logic;
signal ADR_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
signal ADR_REJECTED : std_logic;
- signal next_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
signal buf_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
signal rom_read_addr,buf_rom_read_addr : std_logic_vector(2 downto 0);
signal rom_read_dout : std_logic_vector(15 downto 0);
+ signal length, next_length : std_logic_vector(15 downto 0);
+ signal dont_understand, next_dont_understand : std_logic;
+
begin
pattern_gen_inst : trb_net_pattern_gen
HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation,
buf_API_SEND_OUT, buf_API_PACKET_NUM_OUT, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN,
- buf_DAT_DATA_OUT, buf_DAT_ADDR_OUT, DAT_DATAREADY_IN, DAT_DATA_IN, ADR_REJECTED,
- ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT,
+ buf_DAT_DATA_OUT, buf_DAT_ADDR_OUT, DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED,
+ ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT, length, dont_understand,
buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT
)
variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
next_DAT_READ_ENABLE_OUT <= '0';
next_DAT_WRITE_ENABLE_OUT <= '0';
rom_read_addr <= buf_rom_read_addr;
-
+ next_length <= length;
regnum_STAT := conv_integer(address(NUM_STAT_REGS-1 downto 0));
regnum_CTRL := conv_integer(address(NUM_CTRL_REGS-1 downto 0));
regnum_cSTAT := conv_integer(address(std_COMneededwidth-1 downto 0));
regnum_cCTRL := conv_integer(address(std_COMneededwidth-1 downto 0));
-
+ next_dont_understand <= dont_understand;
case current_state is
when IDLE =>
+ next_dont_understand <= '0';
next_API_SEND_OUT <= '0';
next_API_SHORT_TRANSFER_OUT <= '0';
if API_TYP_IN = TYPE_HDR then
case API_DATA_IN(3 downto 0) is
when c_read_register_type => next_state <= ONE_READ;
when c_write_register_type => next_state <= ONE_WRITE;
- when c_read_multiple_type => next_state <= MEM_READ;
- when c_write_multiple_type => next_state <= MEM_WRITE;
+ when c_read_multiple_type => next_state <= MEM_START_READ;
+ when c_write_multiple_type => next_state <= MEM_START_WRITE;
when c_network_control_type => next_state <= ADDRESS_RECV;
- when others => next_state <= SEND_REPLY_SHORT_TRANSFER;
+ when others =>
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
end case;
next_operation <= API_DATA_IN(3 downto 0);
end if;
next_address <= API_DATA_IN;
rom_read_addr <= API_DATA_IN(1 downto 0) & '1';
if or_all(API_DATA_IN(ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address
- if NO_DAT_PORT = '0' then
+ if USE_DAT_PORT = c_YES then
next_DAT_READ_ENABLE_OUT <= '1';
next_state <= DAT_READ;
else
next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
end if;
else
next_state <= REG_READ;
if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then
next_address <= API_DATA_IN;
if or_all(API_DATA_IN(ADDRESS_WIDTH-1 downto 8)) = '1' then --data port address
- if NO_DAT_PORT = '0' then
+ if USE_DAT_PORT = c_YES then
next_state <= REG_WRITE;
else
next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
end if;
elsif API_DATA_IN(7 downto 5) = "001" or API_DATA_IN(7 downto 6) = "11" then --ctrl address
next_state <= REG_WRITE; --ctrl register
when SEND_REPLY_DATA_finish =>
next_API_SEND_OUT <= '0';
+ next_API_SHORT_TRANSFER_OUT <= '0';
next_state <= IDLE;
when SEND_REPLY_SHORT_TRANSFER =>
next_state <= SEND_REPLY_DATA_finish;
end if;
end if;
-
+ when MEM_START_READ =>
+ if USE_DAT_PORT = c_NO then
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
+ else
+ if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "10" and API_DATAREADY_IN = '1' then
+ next_length <= API_DATA_IN;
+ next_state <= MEM_READ;
+ elsif API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = "01" and API_DATAREADY_IN = '1' then
+ next_address <= API_DATA_IN;
+ if API_DATA_IN(15 downto 8) = 0 then
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
+ end if;
+ end if;
+ end if;
when MEM_READ =>
- next_state <= SEND_REPLY_SHORT_TRANSFER;
+ if buf_API_PACKET_NUM_OUT = "11" and API_READ_IN = '1' then
+ if length = 0 then
+ next_state <= SEND_REPLY_DATA_finish;
+ else
+ next_DAT_READ_ENABLE_OUT <= '1';
+ next_API_SEND_OUT <= '1';
+ next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
+ end if;
+ elsif buf_API_PACKET_NUM_OUT = "00" then
+ if DAT_DATAREADY_IN = '1' then
+ next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
+ next_API_DATA_OUT <= address;
+ next_API_DATAREADY_OUT <= '1';
+ elsif DAT_NO_MORE_DATA_IN = '1' then
+ next_state <= SEND_REPLY_DATA_finish;
+ end if;
+ elsif buf_API_PACKET_NUM_OUT = "01" and API_READ_IN = '1' then
+ next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
+ next_API_DATAREADY_OUT <= '1';
+ elsif buf_API_PACKET_NUM_OUT = "10" and API_READ_IN = '1' then
+ next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
+ next_API_DATAREADY_OUT <= '1';
+ next_length <= length-1;
+ end if;
+
+
+ when MEM_START_WRITE =>
+ if API_PACKET_NUM_IN = "01" and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then
+ next_address <= API_DATA_IN;
+ next_state <= MEM_WRITE;
+ end if;
when MEM_WRITE =>
- next_state <= SEND_REPLY_SHORT_TRANSFER;
+ if USE_DAT_PORT = c_NO then
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
+ elsif API_DATAREADY_IN = '1' then
+ case API_PACKET_NUM_IN is
+ when "10" => next_Reg_high <= API_DATA_IN;
+ when "11" =>
+ next_Reg_low <= API_DATA_IN;
+ next_DAT_WRITE_ENABLE_OUT <= '1';
+ when others => null;
+ end case;
+ if API_TYP_IN = TYPE_TRM then
+ next_state <= DAT_START_READ;
+ end if;
+ end if;
when DAT_START_READ =>
next_DAT_READ_ENABLE_OUT <= '1';
next_state <= DAT_READ;
when DAT_READ =>
- if DAT_DATAREADY_IN = '1' then
+ if DAT_DATAREADY_IN = '1' and API_READ_IN = '1' then
next_API_PACKET_NUM_OUT <= "01";
next_API_DATA_OUT <= address;
next_API_SEND_OUT <= '1';
next_API_DATAREADY_OUT <= '1';
end if;
- if buf_API_PACKET_NUM_OUT = "01" then
+ if buf_API_PACKET_NUM_OUT = "01" and API_READ_IN = '1' then
next_API_PACKET_NUM_OUT <= "10";
- next_API_DATA_OUT <= DAT_DATA_IN(31 downto 16);
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
next_API_DATAREADY_OUT <= '1';
- elsif buf_API_PACKET_NUM_OUT = "10" then
+ elsif buf_API_PACKET_NUM_OUT = "10" and API_READ_IN = '1' then
next_API_PACKET_NUM_OUT <= "11";
- next_API_DATA_OUT <= DAT_DATA_IN(15 downto 0);
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
next_API_DATAREADY_OUT <= '1';
next_state <= SEND_REPLY_DATA_finish;
end if;
-
-
-
when others =>
next_state <= IDLE;
end case;
saved_Reg_high <= (others => '0');
saved_Reg_low <= (others => '0');
buf_rom_read_addr <= "000";
+ length <= (others => '0');
+ dont_understand <= '0';
else
current_state <= next_state;
HDR_F1 <= next_HDR_F1;
REGISTERS_OUT_write_enable <= next_REGISTERS_OUT_write_enable;
COMMON_REGISTERS_OUT_write_enable <= next_COMMON_REGISTERS_OUT_write_enable;
buf_rom_read_addr <= rom_read_addr;
+ length <= next_length;
+ dont_understand <= next_dont_understand;
end if;
end if;
end process;
elsif REGISTERS_OUT_write_enable(i) = '1' then
tmp := saved_Reg_high & saved_Reg_low;
buf_REGISTERS_OUT(j) <= tmp(j-i*REGISTER_WIDTH);
+ elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"D0") then
+ buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*REGISTER_WIDTH);
end if;
end if;
end process;
elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then
tmp := saved_Reg_high & saved_Reg_low;
buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*REGISTER_WIDTH);
+ elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"20") then
+ buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*REGISTER_WIDTH);
end if;
end if;
end process;
end generate;
end generate;
+
+ ext_data_output : process(CLK)
+ variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
+ variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1;
+ variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1;
+ variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1;
+ begin
+ regnum_STAT := conv_integer(EXT_REG_ADDR_IN(NUM_STAT_REGS-1 downto 0));
+ regnum_CTRL := conv_integer(EXT_REG_ADDR_IN(NUM_CTRL_REGS-1 downto 0));
+ regnum_cSTAT := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
+ regnum_cCTRL := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0));
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ EXT_REG_DATA_OUT <= (others => '0');
+ elsif EXT_REG_ADDR_IN(7 downto 6) = "01" then
+ EXT_REG_DATA_OUT <= (others => '0');
+ elsif EXT_REG_ADDR_IN(7 downto 6) = "10" then
+ EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+31 downto regnum_STAT*REGISTER_WIDTH);
+ elsif EXT_REG_ADDR_IN(7 downto 6) = "11" then
+ EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+31 downto regnum_CTRL*REGISTER_WIDTH);
+ elsif EXT_REG_ADDR_IN(5) = '0' then
+ EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+31 downto regnum_cSTAT*REGISTER_WIDTH);
+ else --if EXT_CTRL_ADDR_IN(5) = '1' then
+ EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+31 downto regnum_cCTRL*REGISTER_WIDTH);
+ end if;
+ end if;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if DAT_DATAREADY_IN = '1' then
+ buf_DAT_DATA_IN <= DAT_DATA_IN;
+ end if;
+ end if;
+ end process;
+
+
board_rom : trb_net_rom_16x8
generic map(
INIT0 => COMPILE_TIME(15 downto 0),
);
- buf_API_ERROR_PATTERN_OUT(31 downto 0) <= (others => '0');
+ buf_API_ERROR_PATTERN_OUT(31 downto 5) <= (others => '0');
+ buf_API_ERROR_PATTERN_OUT(4) <= dont_understand;
+ buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0');
API_READ_OUT <= buf_API_READ_OUT;
API_SEND_OUT <= buf_API_SEND_OUT;
REGISTERS_OUT <= buf_REGISTERS_OUT;
COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
- STAT(2 downto 0) <= state_bits;
- STAT(4 downto 3) <= next_API_PACKET_NUM_OUT;
- STAT(5) <= next_API_DATAREADY_OUT;
- STAT(14 downto 6) <= next_API_DATA_OUT(8 downto 0);
+ STAT(3 downto 0) <= state_bits;
+ STAT(5 downto 4) <= next_API_PACKET_NUM_OUT;
+ STAT(6) <= next_API_DATAREADY_OUT;
+ STAT(14 downto 7) <= next_API_DATA_OUT(7 downto 0);
STAT(31 downto 15) <= (others => '0');
process(current_state)
begin
case current_state is
- when IDLE => state_bits <= "000";
- when HEADER_RECV => state_bits <= "001";
- when REG_READ => state_bits <= "010";
- when REG_WRITE => state_bits <= "011";
- when SEND_REPLY_DATA_finish => state_bits <= "100";
- when SEND_REPLY_SHORT_TRANSFER => state_bits <= "101";
- when ONE_READ => state_bits <= "110";
- when others => state_bits <= "111";
+ when IDLE => state_bits <= "0000";
+ when HEADER_RECV => state_bits <= "0001";
+ when REG_READ => state_bits <= "0010";
+ when REG_WRITE => state_bits <= "0011";
+ when SEND_REPLY_DATA_finish => state_bits <= "0100";
+ when SEND_REPLY_SHORT_TRANSFER => state_bits <= "0101";
+ when ONE_READ => state_bits <= "0110";
+ when ONE_WRITE => state_bits <= "0111";
+ when MEM_START_WRITE => state_bits <= "1000";
+ when MEM_READ => state_bits <= "1001";
+ when MEM_WRITE => state_bits <= "1010";
+ when DAT_START_READ => state_bits <= "1011";
+ when DAT_READ => state_bits <= "1100";
+ when ADDRESS_ACK => state_bits <= "1101";
+ when ADDRESS_RECV => state_bits <= "1110";
+ when others => state_bits <= "1111";
end case;
end process;
+
+
end architecture;
next_send_bit <= not bitcounter_vector(1); --this is x33, lsb first
else
next_send_bit <= bitcounter_vector(1); --this is xCC, lsb first
- end if;
+ end if;
if bitcounter_vector(3) = '1' then --send 8 bit
if send_rom = '1' then
next_recv_bit_ready <= '1';
next_state <= READ_WAIT;
end if;
- when READ_WAIT =>
+ when READ_WAIT =>
if is_time_reached(timecounter,80000,CLK_PERIOD) = '1' then
reset_timecounter <= '1';
next_output_tmp <= '0';
--saving received data
process(CLK)
- begin
+ begin
if rising_edge(CLK) then
- ram_wr <= '0';
- if recv_bit_ready = '1' and (send_rom = '1' or reading_temp = '1') then
- buf_STAT <= not buf_STAT;
- ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
- ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
- word(14 downto 0) <= word(15 downto 1);
- word(15) <= recv_bit;
- if bitcounter_vector(3 downto 0) = "0000" and send_rom = '1' then
- ram_wr <= '1';
- end if;
- if bitcounter_vector(3 downto 0) = "1100" and reading_temp = '1' then
- buf_TEMP_OUT <= recv_bit & word(15 downto 5);
+ if RESET = '1' then
+ buf_TEMP_OUT <= (others => '0');
+ ram_addr <= (others => '0');
+ buf_STAT <= '0';
+ word <= (others => '0');
+ else
+ ram_wr <= '0';
+ if recv_bit_ready = '1' and (send_rom = '1' or reading_temp = '1') then
+ buf_STAT <= not buf_STAT;
+ ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
+ ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
+ word(14 downto 0) <= word(15 downto 1);
+ word(15) <= recv_bit;
+ if bitcounter_vector(3 downto 0) = "0000" and send_rom = '1' then
+ ram_wr <= '1';
+ end if;
+ if bitcounter_vector(3 downto 0) = "1100" and reading_temp = '1' then
+ buf_TEMP_OUT <= recv_bit & word(15 downto 5);
+ end if;
end if;
end if;
end if;
TEMP_OUT <= buf_TEMP_OUT;
STAT(0) <= '0';
- STAT(1) <= input;
+ STAT(1) <= '0' when input = '0' else '1';
STAT(2) <= output;
STAT(3) <= send_rom;
STAT(4) <= skip_rom;
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