]> jspc29.x-matter.uni-frankfurt.de Git - mvdelectronics.git/commitdiff
git-svn-id: file:///d/jspc55.1/Elektronik/repo@23 44570794-fe78-5344-a7c8-9252e64eda2e
authoradmin <admin@44570794-fe78-5344-a7c8-9252e64eda2e>
Fri, 6 Sep 2013 11:53:48 +0000 (11:53 +0000)
committeradmin <admin@44570794-fe78-5344-a7c8-9252e64eda2e>
Fri, 6 Sep 2013 11:53:48 +0000 (11:53 +0000)
CB2013/CB13_ADC.SchDoc
CB2013/CB2013.PcbDoc
CB2013/CB2013.PrjPCB
CB2013/CB2013.SCHLIB
CB2013/FEB2013.PrjPCB
CB2013/FrontEndBoard2013_ChipBlock.SchDoc

index 5f97b2dbe2fb7413c148150ffb7690eb1f5ba4f3..35535e073db68fa389fb946cd3465a29d3251f16 100644 (file)
Binary files a/CB2013/CB13_ADC.SchDoc and b/CB2013/CB13_ADC.SchDoc differ
index 7b8bf7f266428356592d92b3cee177f534f567d8..8d211d7f201d9f6297eb9f3ec4059d4958f3203b 100644 (file)
Binary files a/CB2013/CB2013.PcbDoc and b/CB2013/CB2013.PcbDoc differ
index 0a971c5526ba942a4e919860e6529457d1b041f5..86f74cdbecc81499ce70fd2c9bd364c2193fbd06 100644 (file)
@@ -29,7 +29,7 @@ PowerPortNamesTakePriority=0
 PushECOToAnnotationFile=1\r
 DItemRevisionGUID=\r
 ReportSuppressedErrorsInMessages=0\r
-OutputPath=\r
+OutputPath=Project Outputs for CB2013\r
 \r
 [Document1]\r
 DocumentPath=CB13_ADC.SchDoc\r
@@ -446,14 +446,14 @@ AutoOpenFile=0
 AutoOpenOutJob=-1\r
 \r
 [Generic_SmartPDFSettings]\r
-ProjectMode=-1\r
+ProjectMode=0\r
 ZoomPrecision=50\r
 AddNetsInformation=-1\r
-AddNetPins=-1\r
-AddNetNetLabels=-1\r
-AddNetPorts=-1\r
-ShowComponentParameters=-1\r
-ExportBOM=-1\r
+AddNetPins=0\r
+AddNetNetLabels=0\r
+AddNetPorts=0\r
+ShowComponentParameters=0\r
+ExportBOM=0\r
 TemplateFilename=BOM Default Template 95.xlt\r
 TemplateStoreRelative=-1\r
 PCB_PrintColor=0\r
@@ -476,7 +476,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
 SaveSettingsToOutJob=-1\r
 \r
 [Generic_EDE]\r
-OutputDir=\r
+OutputDir=Project Outputs for CB2013\r
 \r
 [OutputGroup1]\r
 Name=Netlist Outputs\r
index 1a1d0f187bfa8293ebfcc871e9728f4ff03199b6..90d7de9034c1dbf5ce07376072afa6f7520478c3 100644 (file)
Binary files a/CB2013/CB2013.SCHLIB and b/CB2013/CB2013.SCHLIB differ
index 1f9360e08badce55834e31ec11eac0278ba90979..0b7b5876250b4104723ee6b3ae2bcd3cb74da49e 100644 (file)
@@ -29,7 +29,7 @@ PowerPortNamesTakePriority=0
 PushECOToAnnotationFile=1\r
 DItemRevisionGUID=\r
 ReportSuppressedErrorsInMessages=0\r
-OutputPath=\r
+OutputPath=Project Outputs for FEB2013\r
 \r
 [Document1]\r
 DocumentPath=CB2013.SCHLIB\r
@@ -95,6 +95,22 @@ ClassGenNCAutoScope=None
 DItemRevisionGUID=\r
 GenerateClassCluster=0\r
 \r
+[Document5]\r
+DocumentPath=FEB2013.OutJob\r
+AnnotationEnabled=1\r
+AnnotateStartValue=1\r
+AnnotationIndexControlEnabled=0\r
+AnnotateSuffix=\r
+AnnotateScope=All\r
+AnnotateOrder=-1\r
+DoLibraryUpdate=1\r
+DoDatabaseUpdate=1\r
+ClassGenCCAutoEnabled=1\r
+ClassGenCCAutoRoomEnabled=1\r
+ClassGenNCAutoScope=None\r
+DItemRevisionGUID=\r
+GenerateClassCluster=0\r
+\r
 [Configuration1]\r
 Name=Default Configuration\r
 ParameterCount=0\r
@@ -105,6 +121,43 @@ Variant=[No Variations]
 GenerateBOM=1\r
 OutputJobsCount=0\r
 \r
+[Generic_SmartPDF]\r
+AutoOpenFile=0\r
+AutoOpenOutJob=0\r
+\r
+[Generic_SmartPDFSettings]\r
+ProjectMode=-1\r
+ZoomPrecision=50\r
+AddNetsInformation=-1\r
+AddNetPins=-1\r
+AddNetNetLabels=-1\r
+AddNetPorts=-1\r
+ShowComponentParameters=-1\r
+ExportBOM=0\r
+TemplateFilename=\r
+TemplateStoreRelative=-1\r
+PCB_PrintColor=0\r
+SCH_PrintColor=0\r
+SCH_ShowNoErc=-1\r
+SCH_ShowParameter=-1\r
+SCH_ShowProbes=-1\r
+SCH_ShowBlankets=-1\r
+SCH_NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle\r
+SCH_ShowNote=-1\r
+SCH_ShowNoteCollapsed=-1\r
+SCH_ExpandLogicalToPhysical=-1\r
+SCH_VariantName=[No Variations]\r
+SCH_ExpandComponentDesignators=-1\r
+SCH_ExpandNetlabels=0\r
+SCH_ExpandPorts=0\r
+SCH_ExpandSheetNumber=0\r
+SCH_ExpandDocumentNumber=0\r
+SCH_HasExpandLogicalToPhysicalSheets=-1\r
+SaveSettingsToOutJob=-1\r
+\r
+[Generic_EDE]\r
+OutputDir=Project Outputs for FEB2013\r
+\r
 [OutputGroup1]\r
 Name=Netlist Outputs\r
 Description=\r
index 92f385a1f88632c43e4c42eabda62b896222a899..a1245beb3ec0505b643d8a6b43b8525e7c2da134 100644 (file)
Binary files a/CB2013/FrontEndBoard2013_ChipBlock.SchDoc and b/CB2013/FrontEndBoard2013_ChipBlock.SchDoc differ