my $lm_license_file_for_synplify = "27020\@jspc29"; #"27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-my $lattice_path = '/d/jspc29/lattice/diamond/3.7_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/K-2015.09/';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.8_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/L-2016.09-1/';
###################################################################################
constant INCLUDE_CTS : integer range c_NO to c_YES := c_YES;
constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_NO;
constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
+ constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_YES;
--include TDC for all four trigger input lines
constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_YES;
--Which external trigger module (ETM) to use?
- constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
+ constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO;
type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
constant ETM_ID : std_logic_vector(7 downto 0);
--output busy signal on pair 4 of Trigger RJ45?
- constant GEN_BUSY_OUTPUT : integer := c_YES;
+ constant GEN_BUSY_OUTPUT : integer := c_NO;
- constant TRIGGER_COIN_COUNT : integer := 4;
+ constant TRIGGER_COIN_COUNT : integer := 3;
constant TRIGGER_PULSER_COUNT : integer := 2;
constant TRIGGER_RAND_PULSER : integer := 1;
- constant TRIGGER_ADDON_COUNT : integer := 6;
+ constant TRIGGER_ADDON_COUNT : integer := 8;
constant PERIPH_TRIGGER_COUNT : integer := 2;
------------------------------------------------------------------------------
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.All;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity timestamp_generator is
+ port(
+ CLK : in std_logic; -- system clk 100 MHz!
+ RESET_IN : in std_logic; -- system reset
+
+ TIMER_CLOCK_IN : in std_logic;
+ TIMER_RESET_IN : in std_logic;
+
+ --data output for read-out
+ TRIGGER_IN : in std_logic;
+ TRIGGER_NUMBER_IN : in std_logic_vector(15 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WRITE_OUT : out std_logic;
+ FINISHED_OUT : out std_logic;
+ STATUSBIT_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+
+architecture arch1 of timestamp_generator is
+
+
+ type state_readout is (RDO_IDLE, RDO_WRITE1, RDO_WRITE2, RDO_WRITE3, RDO_FINISH);
+ signal rdostate : state_readout := RDO_IDLE;
+
+ signal last_TRIGGER_IN : std_logic;
+
+ signal timestamp_counter : unsigned (47 downto 0);
+ signal timer_clock_reg, timer_reset_reg : std_logic;
+ signal last_timer_clock_reg, last_timer_reset_reg : std_logic;
+ signal clock_tick : std_logic;
+ signal finetime_counter : unsigned(23 downto 0);
+
+begin
+
+
+last_TRIGGER_IN <= TRIGGER_IN when rising_edge(CLK);
+
+timer_clock_reg <= TIMER_CLOCK_IN when rising_edge(CLK);
+timer_reset_reg <= TIMER_RESET_IN when rising_edge(CLK);
+last_timer_clock_reg <= timer_clock_reg when rising_edge(CLK);
+last_timer_reset_reg <= timer_reset_reg when rising_edge(CLK);
+
+clock_tick <= not last_timer_clock_reg and timer_clock_reg when rising_edge(CLK);
+
+ PROC_FSM : process
+ begin
+ wait until rising_edge(CLK);
+ if RESET_IN = '1' then
+ timestamp_counter <= (others => '0');
+ finetime_counter <= (others => '0');
+ else
+ if last_timer_reset_reg = '0' and timer_reset_reg = '1' then
+ timestamp_counter <= (others => '0');
+ finetime_counter <= (others => '0');
+ elsif clock_tick = '1' then
+ timestamp_counter <= timestamp_counter + 1;
+ finetime_counter <= (others => '0');
+ else
+ finetime_counter <= finetime_counter + 1;
+ end if;
+ end if;
+ end process;
+
+
+
+ PROC_RDO : process
+ begin
+ wait until rising_edge(CLK);
+ WRITE_OUT <= '0';
+ FINISHED_OUT <= '0';
+ STATUSBIT_OUT <= (others => '0');
+ DATA_OUT <= x"00000000";
+ case rdostate is
+ when RDO_IDLE =>
+ if TRIGGER_IN = '1' and last_TRIGGER_IN = '0' then
+ rdostate <= RDO_WRITE1;
+ end if;
+ when RDO_WRITE1 =>
+ rdostate <= RDO_WRITE2;
+ DATA_OUT <= x"75" & std_logic_vector(timestamp_counter(47 downto 24));
+ WRITE_OUT <= '1';
+ when RDO_WRITE2 =>
+ rdostate <= RDO_WRITE3;
+ DATA_OUT <= x"75" & std_logic_vector(timestamp_counter(23 downto 0));
+ WRITE_OUT <= '1';
+ when RDO_WRITE3 =>
+ rdostate <= RDO_FINISH;
+ DATA_OUT <= x"75" & std_logic_vector(finetime_counter);
+ WRITE_OUT <= '1';
+ when RDO_FINISH =>
+ FINISHED_OUT <= '1';
+ rdostate <= RDO_IDLE;
+ end case;
+ if RESET_IN = '1' then
+ rdostate <= RDO_IDLE;
+ end if;
+ end process;
+
+end architecture;
add_file -vhdl -lib work "source/cbmnet_dlm_etm.vhd"
add_file -vhdl -lib work "source/m26_sensor_etm.vhd"
add_file -vhdl -lib work "source/mbs_master.vhd"
+add_file -vhdl -lib work "source/timestamp_generator.vhd"
if {$INCLUDE_CTS == 1} {
add_file -vhdl -lib work "source/cts_fifo.vhd"
-- CBMNet ETM
- gen_cbmnet_etm : if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) or INCLUDE_ETM = c_NO generate
+ gen_cbmnet_etm : if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) or (INCLUDE_ETM = c_NO and INCLUDE_MBS_MASTER = c_NO and INCLUDE_TIMESTAMP_GENERATOR = c_NO) generate
cts_ext_trigger <= cbm_etm_trigger_i;
cts_rdo_additional(0).data_finished <= '1';
cts_ext_header <= "00";
CLK_TEST_OUT(1) <= mbs_clock_i;
end generate;
+ GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES generate
+ THE_TIMESTAMP : entity work.timestamp_generator
+ port map(
+ CLK => clk_100_i,
+ RESET_IN => reset_i,
+
+ TIMER_CLOCK_IN => CLK_EXT(3),
+ TIMER_RESET_IN => CLK_EXT(4),
+
+ TRIGGER_IN => cts_rdo_trg_data_valid,
+ TRIGGER_NUMBER_IN => cts_rdo_trg_number,
+ DATA_OUT => cts_rdo_additional(INCLUDE_ETM).data,
+ WRITE_OUT => cts_rdo_additional(INCLUDE_ETM).data_write,
+ FINISHED_OUT => cts_rdo_additional(INCLUDE_ETM).data_finished,
+ STATUSBIT_OUT => cts_rdo_additional(INCLUDE_ETM).statusbits
+ );
+ end generate;
+
-------------------------------------------------------------------------------
-- SFP POWER Entity
-------------------------------------------------------------------------------
jspc29 / trb3.git / commitdiff