--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_components.all;
+ use work.trb_net_std.all;
+ use work.trb3_components.all;
+ use work.config.all;
+
+entity clock_reset_handler is
+ port (
+ CLOCK_IN : in std_logic; -- oscillator
+ RESET_FROM_NET : in std_logic;
+ CLOCK_SELECT_IN : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ RESET_OUT : out std_logic;
+ CLEAR_OUT : out std_logic;
+ GSR_OUT : out std_logic;
+
+ RAW_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric
+ SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric
+ REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture clock_reset_handler_arch of clock_reset_handler is
+
+attribute syn_keep : boolean;
+attribute syn_preserve : boolean;
+signal clock_100, clock_120, clock_200, clock_240: std_logic;
+signal sys_clk_i : std_logic;
+signal timer : unsigned(16 downto 0) := (others => '0');
+signal clear_n_i : std_logic := '0';
+signal reset_i : std_logic;
+
+signal pll_lock : std_logic;
+
+attribute syn_keep of clear_n_i : signal is true;
+attribute syn_preserve of clear_n_i : signal is true;
+
+begin
+
+
+SYS_CLK_OUT <= sys_clk_i;
+GSR_OUT <= not pll_lock or clear_n_i;
+
+ THE_INT_PLL : entity work.pll_200_100
+ port map(
+ CLK => CLOCK_IN,
+ CLKOP => clock_100,
+ CLKOS => clock_200,
+ LOCK => pll_lock
+ );
+
+--
+--
+-- THE_PLL : entity work.pll_240_100
+-- port map(
+-- CLKI => CLOCK_IN,
+-- CLKOP => clock_200,
+-- CLKOS => clock_100,
+-- CLKOS2 => clock_240,
+-- CLKOS3 => clock_120,
+-- LOCK => pll_lock
+-- );
+
+gen_slow_clock : if USE_120_MHZ = 0 generate
+ RAW_CLK_OUT <= CLOCK_IN;
+ sys_clk_i <= clock_100;
+ REF_CLK_OUT <= clock_200;
+end generate;
+-- gen_fast_clock : if USE_120_MHZ = 1 generate
+-- RAW_CLK_OUT <= clock_240;
+-- sys_clk_i <= clock_120;
+-- REF_CLK_OUT <= clock_240;
+-- end generate;
+
+
+clear_n_i <= timer(16) when rising_edge(CLOCK_IN);
+
+process begin
+ wait until rising_edge(sys_clk_i);
+ if timer(16) = '1' then
+ timer <= timer;
+ else
+ timer <= timer + 1;
+ end if;
+end process;
+
+
+---------------------------------------------------------------------------
+-- Reset generation
+---------------------------------------------------------------------------
+THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => clear_n_i, -- reset input (low active, async)
+ CLK_IN => CLOCK_IN, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+RESET_OUT <= reset_i;
+
+
+---------------------------------------------------------------------------
+-- Slow clock for DCDC converters
+---------------------------------------------------------------------------
+DEBUG_OUT(0) <= pll_lock;
+DEBUG_OUT(1) <= clear_n_i;
+DEBUG_OUT(31 downto 2) <= (others => '0');
+
+
+THE_REG : process begin
+ wait until rising_edge(sys_clk_i);
+ BUS_TX.unknown <= '0';
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ if BUS_RX.read = '1' then
+ BUS_TX.data <= (others => '0');
+ BUS_TX.data(0) <= CLOCK_SELECT_IN;
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.write = '1' then
+ BUS_TX.unknown <= '1';
+ end if;
+
+end process;
+
+
+
+
+
+
+end architecture;
\ No newline at end of file
-LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ;
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
-REGION "MEDIA_DOWN1" "R102C40D" 13 100;
-LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ;
+SYSCONFIG MCCLK_FREQ = 20;
-LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+FREQUENCY PORT CLOCK_PLL 200 MHz;
+FREQUENCY PORT CLOCK_PCLK 200 MHz;
+FREQUENCY NET "THE_MEDIA*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
+FREQUENCY NET "THE_MEDIA*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
-MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
-BLOCK PATH TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
-MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i" 15 ns;
-MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns;
+LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSC" ;
+LOCATE COMP "THE_MEDIA_4_DOWN_A/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_4_DOWN_B/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+LOCATE COMP "THE_MEDIA_4_DOWN_D/THE_SERDES/PCSD_INST" SITE "PCSD" ;
-MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns;
-MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
-MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns;
+
+
+REGION "MEDIA_DOWN1" "R95C30D" 20 140;
+LOCATE UGROUP "THE_MEDIA_4_DOWN_A/media_interface_group" REGION "MEDIA_DOWN1" ;
+LOCATE UGROUP "THE_MEDIA_4_DOWN_B/media_interface_group" REGION "MEDIA_DOWN1" ;
+LOCATE UGROUP "THE_MEDIA_4_DOWN_D/media_interface_group" REGION "MEDIA_DOWN1" ;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_DOWN1" ;
+
+
+
+
+MULTICYCLE TO CELL "THE_MEDIA*/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA*/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_MEDIA*/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO CLKNET "THE_MEDIA*/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA*/sci_write_i";
+BLOCK PATH TO CLKNET "THE_MEDIA*/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA*/sci_read_i";
+MULTICYCLE TO CLKNET "THE_MEDIA*/sci_read_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA*/sci_read_i" 15 ns;
+MULTICYCLE TO CLKNET "THE_MEDIA*/sci_write_i" 15 ns;
+MULTICYCLE FROM CLKNET "THE_MEDIA*/sci_write_i" 15 ns;
+
+MULTICYCLE FROM CELL "THE_MEDIA*/gen_control.*.gen_used_control.THE_MED_CONTROL/THE_RX_FSM/cs*" TO CELL "THE_MEDIA*/THE_SCI_READER/*" 20 ns;
MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
-#
-# #GbE Part
-# UGROUP "tsmac"
-# BLKNAME GBE/imp_gen.MAC
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS
-# BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER
-# BLKNAME GBE/FRAME_TRANSMITTER;
-# UGROUP "controllers"
-# BLKNAME GBE/main_gen.MAIN_CONTROL
-# BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER
-# BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER;
-# UGROUP "gbe_rx_tx"
-# BLKNAME GBE/FRAME_CONSTRUCTOR
-# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
-# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR
-# BLKNAME GBE/setup_imp_gen.SETUP;
-#
-# #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE;
-# #REGION "MED0" "R81C30D" 34 40 DEVSIZE;
-# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
-# #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE;
-# #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
-# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;
-#
-# UGROUP "sd_tx_to_pcs"
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
-# UGROUP "sd_rx_to_pcs"
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7]
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
-# UGROUP "pcs_tx_to_mac"
-# BLKNAME GBE/pcs_tx_en_q
-# BLKNAME GBE/pcs_tx_en_qq
-# BLKNAME GBE/pcs_tx_er_q
-# BLKNAME GBE/pcs_tx_er_qq
-# BLKNAME GBE/pcs_txd_q[0]
-# BLKNAME GBE/pcs_txd_q[1]
-# BLKNAME GBE/pcs_txd_q[2]
-# BLKNAME GBE/pcs_txd_q[3]
-# BLKNAME GBE/pcs_txd_q[4]
-# BLKNAME GBE/pcs_txd_q[5]
-# BLKNAME GBE/pcs_txd_q[6]
-# BLKNAME GBE/pcs_txd_q[7]
-# BLKNAME GBE/pcs_txd_qq[0]
-# BLKNAME GBE/pcs_txd_qq[1]
-# BLKNAME GBE/pcs_txd_qq[2]
-# BLKNAME GBE/pcs_txd_qq[3]
-# BLKNAME GBE/pcs_txd_qq[4]
-# BLKNAME GBE/pcs_txd_qq[5]
-# BLKNAME GBE/pcs_txd_qq[6]
-# BLKNAME GBE/pcs_txd_qq[7];
-# UGROUP "pcs_rx_to_mac"
-# BLKNAME GBE/pcs_rx_en_q
-# BLKNAME GBE/pcs_rx_en_qq
-# BLKNAME GBE/pcs_rx_er_q
-# BLKNAME GBE/pcs_rx_er_qq
-# BLKNAME GBE/pcs_rxd_q[0]
-# BLKNAME GBE/pcs_rxd_q[1]
-# BLKNAME GBE/pcs_rxd_q[2]
-# BLKNAME GBE/pcs_rxd_q[3]
-# BLKNAME GBE/pcs_rxd_q[4]
-# BLKNAME GBE/pcs_rxd_q[5]
-# BLKNAME GBE/pcs_rxd_q[6]
-# BLKNAME GBE/pcs_rxd_q[7]
-# BLKNAME GBE/pcs_rxd_qq[0]
-# BLKNAME GBE/pcs_rxd_qq[1]
-# BLKNAME GBE/pcs_rxd_qq[2]
-# BLKNAME GBE/pcs_rxd_qq[3]
-# BLKNAME GBE/pcs_rxd_qq[4]
-# BLKNAME GBE/pcs_rxd_qq[5]
-# BLKNAME GBE/pcs_rxd_qq[6]
-# BLKNAME GBE/pcs_rxd_qq[7];
-#
-# UGROUP "GBE_SERDES_group" BBOX 10 67
-# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES;
-# LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ;
-#
-# MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ;
-# MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ;
-#
-# DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
-# "GBE/pcs_rx_er_q"
-# "GBE/pcs_rxd_q*";
-# INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;
-#
-# PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ;
-# PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
-# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ;
\ No newline at end of file
+
+#If these signals do not exist, somebody messed around with the design...
+MULTICYCLE TO CELL "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio[*]" 20 ns;
+MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns;
+# # # # MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns;
+MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+# # # # MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+GSR_NET NET "GSR_N";
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "SFP*";
+BLOCK PATH FROM PORT "SFP*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMPSENS";
+BLOCK PATH FROM PORT "TEMPSENS";
+BLOCK PATH TO PORT "TEST_LINE";
+
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
#Basic Infrastructure
-add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../cores/pll_200_100.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../code/clock_reset_handler_combiner.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
-#
-##GbE
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
-#add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v"
-#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v"
-#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
-#add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
-#add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
-#
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
-#
-
add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
add_file -vhdl -lib work "./combiner.vhd"
-#add_file -fpga_constraint "./synplify.fdc"
+add_file -fpga_constraint "./synplify.fdc"
use work.trb_net_gbe_components.all;
use work.med_sync_define.all;
+
entity combiner is
port(
CLOCK_PCLK : in std_logic;
TRIGGER_TO_CTS : out std_logic;
--Additional IO
- HDR_IO : inout std_logic_vector(10 downto 1);
RJ_CLOCK : inout std_logic_vector( 3 downto 0); --1 not available here
RJ_TRIG : inout std_logic_vector( 2 downto 1); --0,3 not available here
POWER_BOARD_IO : inout std_logic_vector( 3 downto 0);
+ RJ45_SIG : in std_logic_vector( 5 downto 1);
--Lines to slaves
- BACK_MASTER_READY : out std_logic_vector(11 downto 0); --sig_1
- BACK_SLAVE_READY : in std_logic_vector(11 downto 0); --sig_2
- BACK_TRIG1 : in std_logic_vector(11 downto 0); --sig_3
- BACK_TRIG2 : in std_logic_vector(11 downto 0); --sig_4
- BACK_LDO_EN : out std_logic_vector(11 downto 0); --en_ldo
- BACK_SPARE : inout std_logic_vector(11 downto 0); --sig_5
+ BACK_MASTER_READY : out std_logic_vector(12 downto 1); --sig_1
+ BACK_SLAVE_READY : in std_logic_vector(12 downto 1); --sig_2
+ BACK_TRIG1 : in std_logic_vector(12 downto 1); --sig_3
+ BACK_TRIG2 : in std_logic_vector(12 downto 1); --sig_4
+ BACK_LDO_EN : out std_logic_vector(12 downto 1); --en_ldo
+ BACK_SPARE : inout std_logic_vector(12 downto 1); --sig_5
--LED
LED_GREEN : out std_logic;
--Switch
CLOCK_SELECT_IN : in std_logic;
- TRIGG_SEL_OUT : out std_logic_vector( 1 downto 0);
-
+ TRIGGER_SEL_OUT : out std_logic_vector( 2 downto 1); --1 to FPGA, 2 to Backplane,
+ --'0' from FPGA, '1' from connector
--ADC
ADC_CLK : out std_logic;
ADC_CS : out std_logic;
POWER_GOOD : in std_logic;
--Test Connectors
- TEST_LINE : out std_logic_vector(32 downto 0)
+ TEST_LINE : inout std_logic_vector(18 downto 1);
+ TEST_JTAG : out std_logic_vector(20 downto 7)
);
attribute syn_useioff : boolean;
signal time_counter : unsigned(31 downto 0) := (others => '0');
signal led : std_logic_vector(1 downto 0);
signal debug_clock_reset : std_logic_vector(31 downto 0);
+ signal trigger_select_i : std_logic_vector(1 downto 0);
+ signal select_i : std_logic_vector(1 downto 0);
+ signal led_off_i : std_logic;
+ signal enable_ldo_i : std_logic_vector(11 downto 0);
--Media Interface
signal med2int : med2int_array_t(0 to INTERFACE_NUM-1);
signal timer : TIMERS;
signal lcd_data : std_logic_vector(511 downto 0);
+ signal header_io : std_logic_vector(10 downto 1);
signal trig_gen_out_i : std_logic_vector(1 downto 0);
signal monitor_inputs_i : std_logic_vector(25 downto 0);
---------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
- INT_CLK_IN => CLOCK_PCLK,
- EXT_CLK_IN => '0',
- NET_CLK_FULL_IN => med2int(0).clk_full,
- NET_CLK_HALF_IN => med2int(0).clk_half,
+ CLOCK_IN => CLOCK_PCLK,
RESET_FROM_NET => med2int(0).stat_op(13),
+ CLOCK_SELECT_IN => CLOCK_SELECT_IN,
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
CLEAR_OUT => clear_i,
GSR_OUT => GSR_N,
- FULL_CLK_OUT => clk_full,
+ RAW_CLK_OUT => open,
SYS_CLK_OUT => clk_sys,
REF_CLK_OUT => clk_full_osc,
- ENPIRION_CLOCK => open,
- LED_RED_OUT => open,
- LED_GREEN_OUT => open,
DEBUG_OUT => debug_clock_reset
);
SD_LOS_IN => SFP_LOS,
SD_TXDIS_OUT => SFP_TX_DIS,
--Control Interface
- BUS_RX => bussci_rx(0),
- BUS_TX => bussci_tx(0),
+ BUS_RX => bussci_rx(2),
+ BUS_TX => bussci_tx(2),
-- Status and control port
STAT_DEBUG => med_stat_debug(63 downto 0),
CTRL_DEBUG => open
-- TrbNet Downlink
---------------------------------------------------------------------------
-gen_media_interfaces : for i in 0 to 2 generate
- THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
- generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES,c_YES,c_YES)
- )
- port map(
- CLK_REF_FULL => med2int(0).clk_full,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
-
- --Internal Connection
- MEDIA_MED2INT => med2int(i*4+1 to i*4+4),
- MEDIA_INT2MED => int2med(i*4+1 to i*4+4),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
- --SFP Connection
- SD_PRSNT_N_IN => BACK_SLAVE_READY(i*4+3 downto i*4),
- SD_LOS_IN => BACK_SLAVE_READY(i*4+3 downto i*4),
- SD_TXDIS_OUT => BACK_MASTER_READY(i*4+3 downto i*4),
-
- --Control Interface
- BUS_RX => bussci_rx(i+1),
- BUS_TX => bussci_tx(i+1),
+THE_MEDIA_4_DOWN_A : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES,c_YES,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(7),
+ MEDIA_MED2INT(1) => med2int(8),
+ MEDIA_MED2INT(2) => med2int(11),
+ MEDIA_MED2INT(3) => med2int(12),
+ MEDIA_INT2MED(0) => int2med(7),
+ MEDIA_INT2MED(1) => int2med(8),
+ MEDIA_INT2MED(2) => int2med(11),
+ MEDIA_INT2MED(3) => int2med(12),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => BACK_SLAVE_READY(7),
+ SD_PRSNT_N_IN(1) => BACK_SLAVE_READY(8),
+ SD_PRSNT_N_IN(2) => BACK_SLAVE_READY(11),
+ SD_PRSNT_N_IN(3) => BACK_SLAVE_READY(12),
+ SD_LOS_IN(0) => BACK_SLAVE_READY(7),
+ SD_LOS_IN(1) => BACK_SLAVE_READY(8),
+ SD_LOS_IN(2) => BACK_SLAVE_READY(11),
+ SD_LOS_IN(3) => BACK_SLAVE_READY(12),
+ SD_TXDIS_OUT(0) => BACK_MASTER_READY(7),
+ SD_TXDIS_OUT(1) => BACK_MASTER_READY(8),
+ SD_TXDIS_OUT(2) => BACK_MASTER_READY(11),
+ SD_TXDIS_OUT(3) => BACK_MASTER_READY(12),
+
+ --Control Interface
+ BUS_RX => bussci_rx(0),
+ BUS_TX => bussci_tx(0),
+
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+
+THE_MEDIA_4_DOWN_B : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES,c_YES,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(9),
+ MEDIA_MED2INT(1) => med2int(10),
+ MEDIA_MED2INT(2) => med2int(3),
+ MEDIA_MED2INT(3) => med2int(4),
+ MEDIA_INT2MED(0) => int2med(9),
+ MEDIA_INT2MED(1) => int2med(10),
+ MEDIA_INT2MED(2) => int2med(3),
+ MEDIA_INT2MED(3) => int2med(4),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => BACK_SLAVE_READY(9),
+ SD_PRSNT_N_IN(1) => BACK_SLAVE_READY(10),
+ SD_PRSNT_N_IN(2) => BACK_SLAVE_READY(3),
+ SD_PRSNT_N_IN(3) => BACK_SLAVE_READY(4),
+ SD_LOS_IN(0) => BACK_SLAVE_READY(9),
+ SD_LOS_IN(1) => BACK_SLAVE_READY(10),
+ SD_LOS_IN(2) => BACK_SLAVE_READY(3),
+ SD_LOS_IN(3) => BACK_SLAVE_READY(4),
+ SD_TXDIS_OUT(0) => BACK_MASTER_READY(9),
+ SD_TXDIS_OUT(1) => BACK_MASTER_READY(10),
+ SD_TXDIS_OUT(2) => BACK_MASTER_READY(3),
+ SD_TXDIS_OUT(3) => BACK_MASTER_READY(4),
+
+ --Control Interface
+ BUS_RX => bussci_rx(1),
+ BUS_TX => bussci_tx(1),
+
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+
+THE_MEDIA_4_DOWN_D : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES,c_YES,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(6),
+ MEDIA_MED2INT(1) => med2int(5),
+ MEDIA_MED2INT(2) => med2int(2),
+ MEDIA_MED2INT(3) => med2int(1),
+ MEDIA_INT2MED(0) => int2med(6),
+ MEDIA_INT2MED(1) => int2med(5),
+ MEDIA_INT2MED(2) => int2med(2),
+ MEDIA_INT2MED(3) => int2med(1),
- -- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
- );
-end generate;
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => BACK_SLAVE_READY(6),
+ SD_PRSNT_N_IN(1) => BACK_SLAVE_READY(5),
+ SD_PRSNT_N_IN(2) => BACK_SLAVE_READY(2),
+ SD_PRSNT_N_IN(3) => BACK_SLAVE_READY(1),
+ SD_LOS_IN(0) => BACK_SLAVE_READY(6),
+ SD_LOS_IN(1) => BACK_SLAVE_READY(5),
+ SD_LOS_IN(2) => BACK_SLAVE_READY(2),
+ SD_LOS_IN(3) => BACK_SLAVE_READY(1),
+ SD_TXDIS_OUT(0) => BACK_MASTER_READY(6),
+ SD_TXDIS_OUT(1) => BACK_MASTER_READY(5),
+ SD_TXDIS_OUT(2) => BACK_MASTER_READY(2),
+ SD_TXDIS_OUT(3) => BACK_MASTER_READY(1),
+
+ --Control Interface
+ BUS_RX => bussci_rx(3),
+ BUS_TX => bussci_tx(3),
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
---------------------------------------------------------------------------
-- Hub
---------------------------------------------------------------------------
STAT_DEBUG => open
);
-
+rdack <= ctrlbus_tx.rack or ctrlbus_tx.ack;
+wrack <= ctrlbus_tx.wack or ctrlbus_tx.ack;
+
gen_media_record : for i in 0 to INTERFACE_NUM-1 generate
med_data_in(i*16+15 downto i*16) <= med2int(i).data;
med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num;
SPI_MISO_IN => open,
SPI_CLK_OUT => open,
--Header
- HEADER_IO => HDR_IO,
+ HEADER_IO => header_io,
+ ADDITIONAL_REG(0) => led_off_i,
+ ADDITIONAL_REG(2 downto 1) => trigger_select_i,
+ ADDITIONAL_REG(27 downto 16)=> enable_ldo_i,
--LCD
LCD_DATA_IN => lcd_data,
--ADC
-- LED
---------------------------------------------------------------------------
--LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
- LED_GREEN <= debug_clock_reset(0);
- LED_ORANGE <= debug_clock_reset(1);
- LED_RED <= not sed_error_i;
- LED_YELLOW <= debug_clock_reset(2);
+ LED_GREEN <= debug_clock_reset(0) or led_off_i;
+ LED_ORANGE <= debug_clock_reset(1) or led_off_i;
+ LED_RED <= not sed_error_i or led_off_i;
+ LED_YELLOW <= debug_clock_reset(2) or led_off_i;
- LED_SFP_GREEN <= not med2int(0).stat_op(9); --SFP Link Status
- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); --SFP RX/TX
+ LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off_i; --SFP Link Status
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off_i; --SFP RX/TX
- LED_RJ_GREEN <= CLOCK_SELECT_IN & TRIGG_SEL_OUT(0);
- LED_RJ_RED <= reset_i & TRIGG_SEL_OUT(1);
+ LED_RJ_GREEN <= (CLOCK_SELECT_IN or led_off_i) & (trigger_select_i(0) or led_off_i);
+ LED_RJ_RED <= (not reset_i or led_off_i) & (trigger_select_i(1) or led_off_i);
+
+
+ TRIGGER_SEL_OUT <= trigger_select_i;
+ BACK_LDO_EN <= enable_ldo_i;
---------------------------------------------------------------------------
-- LCD Data to display
-- Monitoring & Trigger
---------------------------------------------------------------------------
- TRIGGER_OUT <= trig_gen_out_i(0);
+ TRIGGER_TO_CTS <= trig_gen_out_i(0);
monitor_inputs_i(11 downto 0) <= BACK_TRIG1;
monitor_inputs_i(23 downto 12) <= BACK_TRIG2;
end process;
--- TEST_LINE <= med_stat_debug(15 downto 0);
-
+ TEST_LINE(10 downto 1) <= header_io;
+ TEST_LINE(18 downto 11) <= (others => '0');
+
+ TEST_JTAG(20 downto 7) <= (others => '0');
+
end architecture;
TOPNAME => "combiner",
lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@jspc29",
-lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+lattice_path => '/d/jspc29/lattice/diamond/3.7_x64',
+synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+synplify_command => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
nodelist_file => 'nodelist_frankfurt.txt',
--- /dev/null
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /d/jspc22/trb/git/trb3sc/template/synplify.fdc
+# Written on Thu Jun 18 11:51:05 2015
+# by Synplify Pro, I-2014.03L-SP1 FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+create_clock -name {clk240} {p:CLOCK_PCLK} -period {5}
+create_clock -name {clkfull} {n:THE_CLOCK_RESET.THE_INT_PLL.CLKOS} -period {5}
+create_clock -name {clksys} {n:THE_CLOCK_RESET.THE_INT_PLL.CLKOP} -period {10}
+create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs0\.THE_SERDES.rx_full_clk_ch0} -period {5}
+
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+###==== END "Compile Points"
+
+
+
+
+
+
+
+
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_200_100" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 03 18 14:09:58.338" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_200_100.lpc" type="lpc" modified="2016 03 18 14:09:53.000"/>
+ <File name="pll_200_100.vhd" type="top_level_vhdl" modified="2016 03 18 14:09:53.000"/>
+ <File name="pll_200_100_tmpl.vhd" type="template_vhdl" modified="2016 03 18 14:09:53.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LAE3-17EA
+PartName=LAE3-17EA-6FN484E
+SpeedGrade=6
+Package=FPBGA484
+OperatingCondition=AUTO
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_200_100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/18/2016
+Time=14:09:53
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=2
+ClkOPBp=0
+Post=8
+U_OFrq=100
+OP_Tol=0.0
+OFrq=100.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_200_100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_200_100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
+
+-- Fri Mar 18 14:09:53 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_200_100 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ LOCK: out std_logic);
+end pll_200_100;
+
+architecture Structure of pll_200_100 is
+
+ -- internal signal declarations
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP",
+ DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0,
+ CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 2,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>CLKFB_t);
+
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_200_100 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
+SYSCONFIG MCCLK_FREQ=20 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
+BANK 0 VCCIO 3.3 V;
+BANK 1 VCCIO 2.5 V;
+BANK 2 VCCIO 2.5 V;
+BANK 3 VCCIO 2.5 V;
+BANK 6 VCCIO 2.5 V;
+BANK 7 VCCIO 2.5 V;
+BANK 8 VCCIO 3.3 V;
+
+
+
+LOCATE COMP "CLOCK_PCLK" SITE "U9";
+LOCATE COMP "CLOCK_PLL" SITE "U6";
+DEFINE PORT GROUP "CLK_group" "CL*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+LOCATE COMP "TRIGGER_OUT" SITE "F3";
+LOCATE COMP "TRIGGER_TO_CTS" SITE "M8";
+LOCATE COMP "TRIGGER_IN" SITE "F2";
+IOBUF PORT "TRIGGER_OUT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_TO_CTS" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;
+
+LOCATE COMP "ADC_CS" SITE "AA3";
+LOCATE COMP "ADC_DIN" SITE "AB3";
+LOCATE COMP "ADC_DOUT" SITE "AB4";
+LOCATE COMP "ADC_SCLK" SITE "AA4";
+IOBUF PORT "ADC_CS" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT "ADC_DIN" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT "ADC_DOUT" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5;
+IOBUF PORT "ADC_SCLK" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "POWER_BOARD_IO_1" SITE "AE3";
+LOCATE COMP "POWER_BOARD_IO_2" SITE "AE4";
+LOCATE COMP "POWER_BOARD_IO_3" SITE "AC8";
+LOCATE COMP "POWER_BOARD_IO_4" SITE "AC9";
+DEFINE PORT GROUP "POWER_group" "POWER*" ;
+IOBUF GROUP "POWER_group" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "LED_RJ_GREEN_0" SITE "C25";
+LOCATE COMP "LED_RJ_RED_0" SITE "D25";
+LOCATE COMP "LED_GREEN" SITE "D24";
+LOCATE COMP "LED_ORANGE" SITE "E24";
+LOCATE COMP "LED_RED" SITE "K23";
+LOCATE COMP "LED_SFP_GREEN" SITE "C26";
+LOCATE COMP "LED_SFP_RED" SITE "D26";
+LOCATE COMP "LED_RJ_GREEN_1" SITE "G26";
+LOCATE COMP "LED_RJ_RED_1" SITE "G25";
+LOCATE COMP "LED_YELLOW" SITE "K24";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=3.3;
+
+
+LOCATE COMP "POWER_GOOD" SITE "C9";
+IOBUF PORT "POWER_GOOD" IO_TYPE=LVTTL33;
+
+LOCATE COMP "SELECT_CLOCK_INPUT" SITE "M2";
+IOBUF PORT "SELECT_CLOCK_INPUT" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5;
+
+LOCATE COMP "TEMPSENS" SITE "J13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+
+LOCATE COMP "TRIGGER_SEL_OUT_1" SITE "C8";
+LOCATE COMP "TRIGGER_SEL_OUT_2" SITE "B8";
+IOBUF PORT "TRIGGER_SEL_OUT_1" IO_TYPE=LVTTL33;
+IOBUF PORT "TRIGGER_SEL_OUT_2" IO_TYPE=LVTTL33;
+
+
+
+LOCATE COMP "FLASH_CLK" SITE "F34";
+LOCATE COMP "FLASH_CS" SITE "D34";
+LOCATE COMP "FLASH_IN" SITE "F33";
+LOCATE COMP "FLASH_OUT" SITE "F32";
+LOCATE COMP "PROGRAMN" SITE "C31";
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
+
+
+
+LOCATE COMP "RJ45_SIG_1" SITE "K2";
+LOCATE COMP "RJ45_SIG_2" SITE "J3";
+LOCATE COMP "RJ45_SIG_3" SITE "G2";
+LOCATE COMP "RJ45_SIG_4" SITE "K6";
+LOCATE COMP "RJ45_SIG_5" SITE "K7";
+DEFINE PORT GROUP "RJ45_SIG_group" "RJ45_SIG*" ;
+IOBUF GROUP "RJ45_SIG_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+
+
+LOCATE COMP "SFP_LOS" SITE "B4";
+LOCATE COMP "SFP_MOD0" SITE "D6";
+LOCATE COMP "SFP_MOD1" SITE "C5";
+LOCATE COMP "SFP_MOD2" SITE "A4";
+LOCATE COMP "SFP_RATE_SEL" SITE "A5";
+LOCATE COMP "SFP_TX_DIS" SITE "B7";
+LOCATE COMP "SFP_TX_FAULT" SITE "A3";
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ;
+
+
+LOCATE COMP "TEST_JTAG_7" SITE "J17";
+LOCATE COMP "TEST_JTAG_8" SITE "H17";
+LOCATE COMP "TEST_JTAG_9" SITE "D17";
+LOCATE COMP "TEST_JTAG_10" SITE "C17";
+LOCATE COMP "TEST_JTAG_11" SITE "B16";
+LOCATE COMP "TEST_JTAG_12" SITE "A16";
+LOCATE COMP "TEST_JTAG_13" SITE "B15";
+LOCATE COMP "TEST_JTAG_14" SITE "A15";
+LOCATE COMP "TEST_JTAG_15" SITE "C14";
+LOCATE COMP "TEST_JTAG_16" SITE "D14";
+LOCATE COMP "TEST_JTAG_17" SITE "A12";
+LOCATE COMP "TEST_JTAG_18" SITE "B12";
+LOCATE COMP "TEST_JTAG_19" SITE "C10";
+LOCATE COMP "TEST_JTAG_20" SITE "D10";
+DEFINE PORT GROUP "TEST_JTAG_group" "TEST_JTAG*" ;
+IOBUF GROUP "TEST_JTAG_group" IO_TYPE=LVTTL33 PULLMODE=NONE;
+
+LOCATE COMP "TEST_LINE_1" SITE "M26";
+LOCATE COMP "TEST_LINE_2" SITE "M25";
+LOCATE COMP "TEST_LINE_3" SITE "L26";
+LOCATE COMP "TEST_LINE_4" SITE "M27";
+LOCATE COMP "TEST_LINE_5" SITE "L28";
+LOCATE COMP "TEST_LINE_6" SITE "M28";
+LOCATE COMP "TEST_LINE_7" SITE "K29";
+LOCATE COMP "TEST_LINE_8" SITE "K30";
+LOCATE COMP "TEST_LINE_9" SITE "M31";
+LOCATE COMP "TEST_LINE_10" SITE "M30";
+LOCATE COMP "TEST_LINE_11" SITE "L32";
+LOCATE COMP "TEST_LINE_12" SITE "M34";
+LOCATE COMP "TEST_LINE_13" SITE "L34";
+LOCATE COMP "TEST_LINE_14" SITE "M33";
+LOCATE COMP "TEST_LINE_15" SITE "K34";
+LOCATE COMP "TEST_LINE_16" SITE "K33";
+LOCATE COMP "TEST_LINE_17" SITE "L31";
+LOCATE COMP "TEST_LINE_18" SITE "L33";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+
+LOCATE COMP "BACK_LDO_EN_1" SITE "AJ2"; #"PMT1_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_1" SITE "AA2"; #"PMT1_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_1" SITE "Y2"; #"PMT1_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_1" SITE "W2"; #"PMT1_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_1" SITE "V2"; #"PMT1_C1_SIG4"
+LOCATE COMP "BACK_SPARE_1" SITE "U2"; #"PMT1_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_2" SITE "AJ3"; #"PMT1_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_2" SITE "AA1"; #"PMT1_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_2" SITE "Y1"; #"PMT1_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_2" SITE "W1"; #"PMT1_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_2" SITE "V1"; #"PMT1_C2_SIG4"
+LOCATE COMP "BACK_SPARE_2" SITE "U1"; #"PMT1_C2_SIG5"
+LOCATE COMP "BACK_LDO_EN_3" SITE "AP5"; #"PMT2_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_3" SITE "AJ4"; #"PMT2_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_3" SITE "AL4"; #"PMT2_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_3" SITE "AN3"; #"PMT2_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_3" SITE "AN1"; #"PMT2_C1_SIG4"
+LOCATE COMP "BACK_SPARE_3" SITE "AP2"; #"PMT2_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_4" SITE "AP6"; #"PMT2_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_4" SITE "AK4"; #"PMT2_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_4" SITE "AM4"; #"PMT2_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_4" SITE "AM3"; #"PMT2_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_4" SITE "AN2"; #"PMT2_C2_SIG4"
+LOCATE COMP "BACK_SPARE_4" SITE "AP3"; #"PMT2_C2_SIG5"
+LOCATE COMP "BACK_LDO_EN_5" SITE "AL5"; #"PMT3_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_5" SITE "AB2"; #"PMT3_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_5" SITE "AC2"; #"PMT3_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_5" SITE "AD2"; #"PMT3_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_5" SITE "AE2"; #"PMT3_C1_SIG4"
+LOCATE COMP "BACK_SPARE_5" SITE "AJ1"; #"PMT3_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_6" SITE "AM5"; #"PMT3_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_6" SITE "AB1"; #"PMT3_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_6" SITE "AC1"; #"PMT3_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_6" SITE "AD1"; #"PMT3_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_6" SITE "AE1"; #"PMT3_C2_SIG4"
+LOCATE COMP "BACK_SPARE_6" SITE "AK1"; #"PMT3_C2_SIG5"
+LOCATE COMP "BACK_LDO_EN_7" SITE "AE30"; #"PMT4_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_7" SITE "AB34"; #"PMT4_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_7" SITE "AA31"; #"PMT4_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_7" SITE "Y34"; #"PMT4_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_7" SITE "W34"; #"PMT4_C1_SIG4"
+LOCATE COMP "BACK_SPARE_7" SITE "V31"; #"PMT4_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_8" SITE "AE29"; #"PMT4_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_8" SITE "AB33"; #"PMT4_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_8" SITE "AA30"; #"PMT4_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_8" SITE "Y33"; #"PMT4_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_8" SITE "W33"; #"PMT4_C2_SIG4"
+LOCATE COMP "BACK_SPARE_8" SITE "V30"; #"PMT4_C2_SIG5"
+LOCATE COMP "BACK_LDO_EN_9" SITE "AP31"; #"PMT5_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_9" SITE "AP33"; #"PMT5_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_9" SITE "AN34"; #"PMT5_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_9" SITE "AN32"; #"PMT5_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_9" SITE "AL34"; #"PMT5_C1_SIG4"
+LOCATE COMP "BACK_SPARE_9" SITE "AL32"; #"PMT5_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_10" SITE "AN31"; #"PMT5_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_10" SITE "AP32"; #"PMT5_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_10" SITE "AN33"; #"PMT5_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_10" SITE "AM32"; #"PMT5_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_10" SITE "AL33"; #"PMT5_C2_SIG4"
+LOCATE COMP "BACK_SPARE_10" SITE "AK32"; #"PMT5_C2_SIG5"
+LOCATE COMP "BACK_LDO_EN_11" SITE "AJ31"; #"PMT6_C1_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_11" SITE "AH33"; #"PMT6_C1_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_11" SITE "AF32"; #"PMT6_C1_SIG2"
+LOCATE COMP "BACK_TRIG1_11" SITE "AF34"; #"PMT6_C1_SIG3"
+LOCATE COMP "BACK_TRIG2_11" SITE "AE34"; #"PMT6_C1_SIG4"
+LOCATE COMP "BACK_SPARE_11" SITE "AC34"; #"PMT6_C1_SIG5"
+LOCATE COMP "BACK_LDO_EN_12" SITE "AK31"; #"PMT6_C2_EN_LDO"
+LOCATE COMP "BACK_MASTER_READY_12" SITE "AJ33"; #"PMT6_C2_SIG1"
+LOCATE COMP "BACK_SLAVE_READY_12" SITE "AF31"; #"PMT6_C2_SIG2"
+LOCATE COMP "BACK_TRIG1_12" SITE "AG34"; #"PMT6_C2_SIG3"
+LOCATE COMP "BACK_TRIG2_12" SITE "AE33"; #"PMT6_C2_SIG4"
+LOCATE COMP "BACK_SPARE_12" SITE "AC33"; #"PMT6_C2_SIG5"
+
+DEFINE PORT GROUP "BACK_LDO_EN_group" "BACK_LDO_EN*" ;
+IOBUF GROUP "BACK_LDO_EN_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+DEFINE PORT GROUP "BACK_MASTER_group" "BACK_MASTER*" ;
+IOBUF GROUP "BACK_MASTER_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+DEFINE PORT GROUP "BACK_SLAVE_group" "BACK_SLAVE*" ;
+IOBUF GROUP "BACK_SLAVE_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+DEFINE PORT GROUP "BACK_TRIG_group" "BACK_TRIG*" ;
+IOBUF GROUP "BACK_TRIG_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+DEFINE PORT GROUP "BACK_SPARE_group" "BACK_SPARE*" ;
+IOBUF GROUP "BACK_SPARE_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+
+
jspc29 / dirich.git / commitdiff