multicycle constraint for clock domain crossings

diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf
index 1fb3d5a47e57a5ed2bf98d2ce9d092ee341a5841..9a94475c193d00107c382206cce30fd984c878cf 100644 (file)
--- a/base/trb3_periph_32PinAddOn.lpf
+++ b/base/trb3_periph_32PinAddOn.lpf
@@ -14,6 +14,9 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf
index 56c8eace6f272b6fa8ed9303d734e7883ce89919..caeaf6cd12ea5b9f87ba99b95c812bbd80218d1e 100644 (file)
--- a/base/trb3_periph_ADA.lpf
+++ b/base/trb3_periph_ADA.lpf
@@ -14,6 +14,9 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf
index efeac68d128494cf5b6c9fd1f7c2b0852a79953b..7d2e6ca9f83c386ae6d9360809ddd33ac97936dd 100644 (file)
--- a/base/trb3_periph_ada.lpf
+++ b/base/trb3_periph_ada.lpf
@@ -94,6 +94,9 @@ BLOCK RD_DURING_WR_PATHS ;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
   FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_gpin.lpf b/base/trb3_periph_gpin.lpf
index 50999ca907be204052839b8cf90c70427e694528..96e89d14525f4497c39a321535dd9be50f63fa3b 100644 (file)
--- a/base/trb3_periph_gpin.lpf
+++ b/base/trb3_periph_gpin.lpf
@@ -12,6 +12,9 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index 41b07c924b1d2d90d4c310d9455bd44412a9736c..d6144d405ee98350b82e39b23970e981088dcdc2 100644 (file)
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -12,6 +12,9 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
+MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+
 #################################################################
 # Clock I/O
 #################################################################