]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
pending
authorLudwig Maier <lmaier@brett.e12.ph.tum.de>
Wed, 2 Oct 2013 20:30:53 +0000 (22:30 +0200)
committerLudwig Maier <lmaier@brett.e12.ph.tum.de>
Wed, 2 Oct 2013 20:30:53 +0000 (22:30 +0200)
nxyter/compile_munich20.pl [new file with mode: 0755]
nxyter/compile_munich20.sh [new file with mode: 0755]
nxyter/cores/pll_adc_clk.ipx [new file with mode: 0644]
nxyter/cores/pll_adc_clk.lpc [new file with mode: 0644]
nxyter/cores/pll_adc_clk.vhd [new file with mode: 0644]
nxyter/todo.txt [new file with mode: 0644]
nxyter/wichtigedateien.txt [new file with mode: 0644]

diff --git a/nxyter/compile_munich20.pl b/nxyter/compile_munich20.pl
new file mode 100755 (executable)
index 0000000..cfa5edb
--- /dev/null
@@ -0,0 +1,155 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
+my $lattice_path                 = '/usr/local/opt/lattice_diamond/diamond/2.0';
+my $synplify_path                = '/usr/local/opt/synplify/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+
+
+
+
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+       print "\n";
+       $c="cat $TOPNAME.srr | grep \"\@E\"";
+       system($c);
+        print "\n\n";
+       exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+       print "$!";
+       if($op ne "do_not_exit") {
+           exit;
+       }
+    }
+
+    return $r;
+
+}
diff --git a/nxyter/compile_munich20.sh b/nxyter/compile_munich20.sh
new file mode 100755 (executable)
index 0000000..bed8cfa
--- /dev/null
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+. /usr/local/opt/lattice_diamond/diamond/2.0/bin/lin/diamond_env
+
+exec ./compile_munich20.pl
diff --git a/nxyter/cores/pll_adc_clk.ipx b/nxyter/cores/pll_adc_clk.ipx
new file mode 100644 (file)
index 0000000..0b8e765
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc_clk" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 22:15:00.057" version="5.3" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="pll_adc_clk.lpc" type="lpc" modified="2013 10 02 22:14:51.000"/>
+               <File name="pll_adc_clk.vhd" type="top_level_vhdl" modified="2013 10 02 22:14:51.000"/>
+               <File name="pll_adc_clk_tmpl.vhd" type="template_vhdl" modified="2013 10 02 22:14:51.000"/>
+  </Package>
+</DiamondModule>
diff --git a/nxyter/cores/pll_adc_clk.lpc b/nxyter/cores/pll_adc_clk.lpc
new file mode 100644 (file)
index 0000000..73a8e23
--- /dev/null
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_adc_clk
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=10/02/2013
+Time=22:14:51
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=16
+ClkOPBp=0
+Post=4
+U_OFrq=187.5
+OP_Tol=0.0
+OFrq=187.500000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=15
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.826303
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/nxyter/cores/pll_adc_clk.vhd b/nxyter/cores/pll_adc_clk.vhd
new file mode 100644 (file)
index 0000000..c4b0100
--- /dev/null
@@ -0,0 +1,99 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 187.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Wed Oct  2 22:14:51 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc_clk is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc_clk : entity is true;
+end pll_adc_clk;
+
+architecture Structure of pll_adc_clk is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "187.500000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  15, CLKI_DIV=>  16, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc_clk is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/nxyter/todo.txt b/nxyter/todo.txt
new file mode 100644 (file)
index 0000000..dba365c
--- /dev/null
@@ -0,0 +1,11 @@
+
+
+
+- change compile_munich.pl to contain correct paths to tools
+- link ../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt to ./workdir
+
+- change ../base/trb3_periph_nxyter.lpf to the pin names used for the nxyter addon (starting from line 92), remove all DQ* signals
+- add the signal names for the nxyter addon in the entity declaration of the top-level trb3_periph.vhd
+
+- add your vhdl files to trb3_periph.prj
+- Edit trb3_periph_constraints.lpf to contain the correct names of clock nets & pins - see the two comments in the second block.
diff --git a/nxyter/wichtigedateien.txt b/nxyter/wichtigedateien.txt
new file mode 100644 (file)
index 0000000..6be4a26
--- /dev/null
@@ -0,0 +1,13 @@
+Zum Kompilieren:
+das in workdir aufrufen falls die links weg sind:
+/home/rich/TRB/nXyter/trb3/base/linkdesignfiles.sh
+
+
+
+Zum debuggen: see workdir/*
+.srr
+.mrp
+.par
+.twr.setup
+
+dateien