added generic flash ctrl, IF

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index b59dea1266c29bd4fb6e8d1ac26b75c7af54136e..bfe059bf2623bd53bffabd48f71b39a6553050ac 100644 (file)
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -41,6 +41,13 @@ architecture arch of logicbox is
  \r
   --UART\r
   -------------------------------------\r
+  signal uart_data_out : std_logic_vector(31 downto 0);\r
+  signal uart_data_in  : std_logic_vector(31 downto 0);\r
+  signal uart_addr_out : std_logic_vector(7 downto 0);\r
+  signal uart_read_out  : std_logic := '0';\r
+  signal uart_write_out : std_logic := '0';\r
+  signal uart_ready_in  : std_logic;\r
+  \r
   signal uart_rx_data : std_logic_vector(31 downto 0);\r
   signal uart_tx_data : std_logic_vector(31 downto 0);\r
   signal uart_addr    : std_logic_vector(7 downto 0);\r
@@ -72,14 +79,14 @@ architecture arch of logicbox is
 \r
   --UFM\r
   -------------------------------------\r
-  signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write\r
-  signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup \r
-  signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA\r
-  signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB\r
-  signal ufm_databyte_counter : unsigned(14 downto 0);\r
-  signal ufm_bus_ready_out : std_logic;\r
-  signal ufm_bus_ready_in : std_logic;\r
-  signal ufm_busy : std_logic;\r
+  --signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write\r
+  --signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup \r
+  --signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA\r
+  --signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB\r
+  --signal ufm_databyte_counter : unsigned(14 downto 0);\r
+  --signal ufm_bus_ready_out : std_logic;\r
+  --signal ufm_bus_ready_in : std_logic;\r
+  --signal ufm_busy : std_logic;\r
 \r
   \r
   component OSCH\r
@@ -268,12 +275,13 @@ THE_UART : entity work.uart_sctrl
     UART_RX => TX_IN,\r
     UART_TX => RX_OUT,\r
     \r
-    DATA_OUT  => uart_rx_data,\r
-    DATA_IN   => uart_tx_data,\r
-    ADDR_OUT  => uart_addr,       \r
-    WRITE_OUT => bus_write,\r
-    READ_OUT  => bus_read,\r
-    READY_IN  => bus_ready,\r
+    DATA_OUT  => uart_data_out,\r
+    DATA_IN   => uart_data_in,\r
+    ADDR_OUT  => uart_addr_out,       \r
+    WRITE_OUT => uart_write_out,\r
+    READ_OUT  => uart_read_out,\r
+    READY_IN  => uart_ready_in,\r
+    --READY_IN  => '1',\r
     \r
     DEBUG     => open\r
     );\r
@@ -281,30 +289,53 @@ THE_UART : entity work.uart_sctrl
 ---------------------------------------------------------------------------\r
 -- UFM (FLASH) CONTROLLER\r
 ---------------------------------------------------------------------------      \r
-THE_UFM : entity UFM_control\r
+--THE_UFM : entity UFM_control\r
+--  generic map(\r
+--    NO_DATAPAGES => 1,\r
+--    UFM_STARTPAGE => "00"&x"00"\r
+--    )\r
+--  port map(\r
+--    CLK => clk_33,\r
+--    CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write\r
+--    GO => ufm_go,\r
+--    BUSY => ufm_busy,\r
+--    RESET => '0',  \r
+--    DATA_IN => ufm_data_in, \r
+--    DATA_OUT => ufm_data_out,\r
+--    DATABYTE_COUNTER => ufm_databyte_counter,\r
+--    BUS_READY_IN => ufm_bus_ready_in,\r
+--    BUS_READY_OUT  => ufm_bus_ready_out,\r
+--    FLASH_ERROR => open--ufmflasherror\r
+--    );\r
+\r
+THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
   generic map(\r
-    NO_DATAPAGES => 1,\r
-    UFM_STARTPAGE => "00"&x"00"\r
+    DATA_BUS_WIDTH => 32\r
     )\r
   port map(\r
-    CLK => clk_33,\r
 \r
-    CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write\r
-    GO => ufm_go,\r
-    BUSY => ufm_busy,\r
+    CLK => clk_33,\r
     RESET => '0',\r
-    \r
-    DATA_IN => ufm_data_in, \r
-    DATA_OUT => ufm_data_out,\r
-    DATABYTE_COUNTER => ufm_databyte_counter,\r
-    BUS_READY_IN => ufm_bus_ready_in,\r
-    BUS_READY_OUT  => ufm_bus_ready_out,\r
 \r
-    FLASH_ERROR => open--ufmflasherror\r
-    );\r
-    \r
+    SPI_DATA_IN   => uart_data_out,\r
+    SPI_DATA_OUT  => uart_data_in,\r
+    SPI_ADDR_IN   => uart_addr_out,\r
+    SPI_WRITE_IN  => uart_write_out,\r
+    SPI_READ_IN   => uart_read_out,\r
+    SPI_READY_OUT => uart_ready_in,\r
+\r
+    LOC_DATA_OUT  => uart_rx_data,\r
+    LOC_DATA_IN   => uart_tx_data,\r
+    LOC_ADDR_OUT  => uart_addr,\r
+    LOC_WRITE_OUT => bus_write,\r
+    LOC_READ_OUT  => bus_read,\r
+    LOC_READY_IN  => bus_ready\r
+\r
+  );\r
+\r
+\r
 ---------------------------------------------------------------------------\r
--- READ/WRITE REGISTERS VIA UART/FLASH\r
+-- Read/WRITE REGISTERS VIA UART/FLASH\r
 ---------------------------------------------------------------------------\r
 PROC_REGS : process begin\r
   wait until rising_edge(clk_33);\r
@@ -312,7 +343,7 @@ PROC_REGS : process begin
   --register <=> UART datatransfer\r
   -------------------------------------------------------------------\r
   bus_ready <= '0';\r
-  ufm_go <= '0'; --for operating UFM_control\r
+--  ufm_go <= '0'; --for operating UFM_control\r
     \r
   if bus_read = '1' then\r
   --send out data from registers over RS232\r
@@ -331,15 +362,15 @@ PROC_REGS : process begin
   elsif bus_write = '1' then\r
   --write registers with data from received from RS232\r
     case uart_addr is\r
-      when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then \r
+--      when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then \r
                     --initiate load from UFM\r
-                      ufm_cmd <= '0';\r
-                      ufm_go <= '1';\r
-                    elsif uart_rx_data  = x"FFFFFFFF" and ufm_busy = '0' then\r
-                    --initiate write to UFM\r
-                      ufm_cmd <= '1';\r
-                      ufm_go <= '1';\r
-                    end if; \r
+--                      ufm_cmd <= '0';\r
+--                      ufm_go <= '1';-\r
+--                    elsif uart_rx_data  = x"FFFFFFFF" and ufm_busy = '0' then\r
+--                    --initiate write to UFM\r
+--                      ufm_cmd <= '1';\r
+--                      ufm_go <= '1';\r
+--                    end if; \r
     \r
       when x"10" => reg <= uart_rx_data;\r
 \r
@@ -359,53 +390,53 @@ PROC_REGS : process begin
   \r
   --register <=> UFM datatransfer\r
   -------------------------------------------------------------------\r
-  ufm_bus_ready_in <= '0'; \r
+--  ufm_bus_ready_in <= '0'; \r
 \r
-  if ufm_cmd = '0' and ufm_bus_ready_out = '1' then\r
+--  if ufm_cmd = '0' and ufm_bus_ready_out = '1' then\r
   --copy data from UFM to registers\r
-    ufm_bus_ready_in <= '1';\r
-    case to_integer(ufm_databyte_counter) is\r
-      when 0 =>   reg(7 downto 0) <= ufm_data_out;\r
-      when 1 =>   reg(15 downto 8) <= ufm_data_out;\r
-      when 2 =>   reg(23 downto 16) <= ufm_data_out;\r
-      when 3 =>   reg(31 downto 24) <= ufm_data_out;\r
+--    ufm_bus_ready_in <= '1';\r
+--    case to_integer(ufm_databyte_counter) is\r
+--      when 0 =>   reg(7 downto 0) <= ufm_data_out;\r
+--      when 1 =>   reg(15 downto 8) <= ufm_data_out;\r
+--      when 2 =>   reg(23 downto 16) <= ufm_data_out;\r
+--      when 3 =>   reg(31 downto 24) <= ufm_data_out;\r
       \r
-      when 4 =>   pulser_periodlength(7 downto 0) <= ufm_data_out;\r
-      when 5 =>   pulser_periodlength(15 downto 8) <= ufm_data_out;\r
-      when 6 =>   pulser_periodlength(23 downto 16) <= ufm_data_out;\r
-      when 7 =>   pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);\r
+--      when 4 =>   pulser_periodlength(7 downto 0) <= ufm_data_out;\r
+--      when 5 =>   pulser_periodlength(15 downto 8) <= ufm_data_out;\r
+--      when 6 =>   pulser_periodlength(23 downto 16) <= ufm_data_out;\r
+--      when 7 =>   pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);\r
       \r
-      when 8 =>   pulser_pulslength(7 downto 0) <= ufm_data_out;\r
-      when 9 =>   pulser_pulslength(15 downto 8) <= ufm_data_out;\r
-      when 10 =>  pulser_pulslength(23 downto 16) <= ufm_data_out;\r
-      when 11 =>  pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);\r
+--      when 8 =>   pulser_pulslength(7 downto 0) <= ufm_data_out;\r
+--      when 9 =>   pulser_pulslength(15 downto 8) <= ufm_data_out;\r
+--      when 10 =>  pulser_pulslength(23 downto 16) <= ufm_data_out;\r
+--      when 11 =>  pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);\r
       \r
-      when others =>null;\r
-    end case;\r
+--      when others =>null;\r
+--    end case;\r
       \r
-  elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then\r
+--  elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then\r
   --save data from registers to UFM\r
-    ufm_bus_ready_in <= '1';\r
-    case to_integer(ufm_databyte_counter) is\r
-      when 0 =>   ufm_data_in <= reg(7 downto 0);\r
-      when 1 =>   ufm_data_in <= reg(15 downto 8);\r
-      when 2 =>   ufm_data_in <= reg(23 downto 16);\r
-      when 3 =>   ufm_data_in <= reg(31 downto 24);\r
-\r
-      when 4 =>   ufm_data_in <= pulser_periodlength(7 downto 0);\r
-      when 5 =>   ufm_data_in <= pulser_periodlength(15 downto 8);\r
-      when 6 =>   ufm_data_in <= pulser_periodlength(23 downto 16);\r
-      when 7 =>   ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));\r
+--    ufm_bus_ready_in <= '1';\r
+--    case to_integer(ufm_databyte_counter) is\r
+--      when 0 =>   ufm_data_in <= reg(7 downto 0);\r
+--      when 1 =>   ufm_data_in <= reg(15 downto 8);\r
+--      when 2 =>   ufm_data_in <= reg(23 downto 16);\r
+--      when 3 =>   ufm_data_in <= reg(31 downto 24);\r
+\r
+--      when 4 =>   ufm_data_in <= pulser_periodlength(7 downto 0);\r
+--      when 5 =>   ufm_data_in <= pulser_periodlength(15 downto 8);\r
+--      when 6 =>   ufm_data_in <= pulser_periodlength(23 downto 16);\r
+--      when 7 =>   ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));\r
       \r
-      when 8 =>   ufm_data_in <= pulser_pulslength(7 downto 0);\r
-      when 9 =>   ufm_data_in <= pulser_pulslength(15 downto 8);\r
-      when 10 =>  ufm_data_in <= pulser_pulslength(23 downto 16);\r
-      when 11 =>  ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));\r
+--      when 8 =>   ufm_data_in <= pulser_pulslength(7 downto 0);\r
+--      when 9 =>   ufm_data_in <= pulser_pulslength(15 downto 8);\r
+--      when 10 =>  ufm_data_in <= pulser_pulslength(23 downto 16);\r
+--      when 11 =>  ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));\r
       \r
-      when others =>null;\r
-    end case;\r
+--      when others =>null;\r
+--    end case;\r
       \r
-  end if;\r
+--  end if;\r
 end process;\r
 \r
 \r