--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.4
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e
+
+-- Fri Jul 23 21:15:52 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_32kx16x8_mb2 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ AmEmptyThresh: in std_logic_vector(15 downto 0);
+ AmFullThresh: in std_logic_vector(14 downto 0);
+ Q: out std_logic_vector(8 downto 0);
+ WCNT: out std_logic_vector(15 downto 0);
+ RCNT: out std_logic_vector(16 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_32kx16x8_mb2;
+
+architecture Structure of fifo_32kx16x8_mb2 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal func_and_inet: std_logic;
+ signal func_and_inet_1: std_logic;
+ signal func_and_inet_2: std_logic;
+ signal func_and_inet_3: std_logic;
+ signal func_and_inet_4: std_logic;
+ signal func_and_inet_5: std_logic;
+ signal func_and_inet_6: std_logic;
+ signal func_and_inet_7: std_logic;
+ signal func_and_inet_8: std_logic;
+ signal func_and_inet_9: std_logic;
+ signal func_and_inet_10: std_logic;
+ signal func_and_inet_11: std_logic;
+ signal func_and_inet_12: std_logic;
+ signal func_and_inet_13: std_logic;
+ signal func_and_inet_14: std_logic;
+ signal func_and_inet_15: std_logic;
+ signal func_and_inet_16: std_logic;
+ signal func_and_inet_17: std_logic;
+ signal func_and_inet_18: std_logic;
+ signal func_and_inet_19: std_logic;
+ signal func_and_inet_20: std_logic;
+ signal func_and_inet_21: std_logic;
+ signal func_and_inet_22: std_logic;
+ signal func_and_inet_23: std_logic;
+ signal func_and_inet_24: std_logic;
+ signal func_and_inet_25: std_logic;
+ signal func_and_inet_26: std_logic;
+ signal func_and_inet_27: std_logic;
+ signal func_and_inet_28: std_logic;
+ signal func_and_inet_29: std_logic;
+ signal wptr_14_inv: std_logic;
+ signal func_and_inet_30: std_logic;
+ signal rptr_15_inv: std_logic;
+ signal func_and_inet_31: std_logic;
+ signal func_and_inet_32: std_logic;
+ signal func_and_inet_33: std_logic;
+ signal func_and_inet_34: std_logic;
+ signal func_and_inet_35: std_logic;
+ signal func_and_inet_36: std_logic;
+ signal func_and_inet_37: std_logic;
+ signal func_and_inet_38: std_logic;
+ signal func_and_inet_39: std_logic;
+ signal func_and_inet_40: std_logic;
+ signal func_and_inet_41: std_logic;
+ signal func_and_inet_42: std_logic;
+ signal func_and_inet_43: std_logic;
+ signal func_and_inet_44: std_logic;
+ signal func_and_inet_45: std_logic;
+ signal wptr_13_inv: std_logic;
+ signal func_and_inet_46: std_logic;
+ signal rptr_14_inv: std_logic;
+ signal func_and_inet_47: std_logic;
+ signal func_and_inet_48: std_logic;
+ signal func_and_inet_49: std_logic;
+ signal func_and_inet_50: std_logic;
+ signal func_and_inet_51: std_logic;
+ signal func_and_inet_52: std_logic;
+ signal func_and_inet_53: std_logic;
+ signal wptr_12_inv: std_logic;
+ signal func_and_inet_54: std_logic;
+ signal rptr_13_inv: std_logic;
+ signal func_and_inet_55: std_logic;
+ signal func_and_inet_56: std_logic;
+ signal func_and_inet_57: std_logic;
+ signal wptr_11_inv: std_logic;
+ signal func_and_inet_58: std_logic;
+ signal rptr_12_inv: std_logic;
+ signal func_and_inet_59: std_logic;
+ signal wptr_10_inv: std_logic;
+ signal func_and_inet_60: std_logic;
+ signal rptr_11_inv: std_logic;
+ signal func_and_inet_61: std_logic;
+ signal func_and_inet_62: std_logic;
+ signal func_and_inet_63: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal w_g2b_xor_cluster_3_1: std_logic;
+ signal w_g2b_xor_cluster_3_2: std_logic;
+ signal w_g2b_xor_cluster_3: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_2_1: std_logic;
+ signal r_g2b_xor_cluster_3_1: std_logic;
+ signal r_g2b_xor_cluster_3_2: std_logic;
+ signal r_g2b_xor_cluster_3: std_logic;
+ signal r_g2b_xor_cluster_2: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal func_xor_inet_3: std_logic;
+ signal func_xor_inet_2: std_logic;
+ signal func_xor_inet_1: std_logic;
+ signal func_xor_inet: std_logic;
+ signal rcount_w0: std_logic;
+ signal func_xor_inet_4: std_logic;
+ signal func_xor_inet_5: std_logic;
+ signal rcnt_reg_15_inv: std_logic;
+ signal dec1_r10: std_logic;
+ signal dec0_p00: std_logic;
+ signal dec3_r11: std_logic;
+ signal dec2_p01: std_logic;
+ signal dec5_r12: std_logic;
+ signal dec4_p02: std_logic;
+ signal dec7_r13: std_logic;
+ signal dec6_p03: std_logic;
+ signal dec9_r14: std_logic;
+ signal dec8_p04: std_logic;
+ signal dec11_r15: std_logic;
+ signal dec10_p05: std_logic;
+ signal dec13_r16: std_logic;
+ signal dec12_p06: std_logic;
+ signal dec15_r17: std_logic;
+ signal dec14_p07: std_logic;
+ signal dec17_r18: std_logic;
+ signal dec16_p08: std_logic;
+ signal dec19_r19: std_logic;
+ signal dec18_p09: std_logic;
+ signal dec21_r110: std_logic;
+ signal dec20_p010: std_logic;
+ signal dec23_r111: std_logic;
+ signal dec22_p011: std_logic;
+ signal dec25_r112: std_logic;
+ signal dec24_p012: std_logic;
+ signal dec27_r113: std_logic;
+ signal dec26_p013: std_logic;
+ signal dec29_r114: std_logic;
+ signal dec28_p014: std_logic;
+ signal dec31_r115: std_logic;
+ signal dec30_p015: std_logic;
+ signal dec33_r116: std_logic;
+ signal dec32_p016: std_logic;
+ signal dec35_r117: std_logic;
+ signal dec34_p017: std_logic;
+ signal dec37_r118: std_logic;
+ signal dec36_p018: std_logic;
+ signal dec39_r119: std_logic;
+ signal dec38_p019: std_logic;
+ signal dec41_r120: std_logic;
+ signal dec40_p020: std_logic;
+ signal dec43_r121: std_logic;
+ signal dec42_p021: std_logic;
+ signal dec45_r122: std_logic;
+ signal dec44_p022: std_logic;
+ signal dec47_r123: std_logic;
+ signal dec46_p023: std_logic;
+ signal dec49_r124: std_logic;
+ signal dec48_p024: std_logic;
+ signal dec51_r125: std_logic;
+ signal dec50_p025: std_logic;
+ signal dec53_r126: std_logic;
+ signal dec52_p026: std_logic;
+ signal dec55_r127: std_logic;
+ signal dec54_p027: std_logic;
+ signal dec57_r128: std_logic;
+ signal dec56_p028: std_logic;
+ signal dec59_r129: std_logic;
+ signal dec58_p029: std_logic;
+ signal dec61_r130: std_logic;
+ signal dec60_p030: std_logic;
+ signal dec63_r131: std_logic;
+ signal dec62_p031: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal w_gdata_12: std_logic;
+ signal w_gdata_13: std_logic;
+ signal w_gdata_14: std_logic;
+ signal wptr_15: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal r_gdata_9: std_logic;
+ signal r_gdata_10: std_logic;
+ signal r_gdata_11: std_logic;
+ signal r_gdata_12: std_logic;
+ signal r_gdata_13: std_logic;
+ signal r_gdata_14: std_logic;
+ signal r_gdata_15: std_logic;
+ signal rptr_16: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal w_gcount_13: std_logic;
+ signal w_gcount_14: std_logic;
+ signal w_gcount_15: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal r_gcount_10: std_logic;
+ signal r_gcount_11: std_logic;
+ signal r_gcount_12: std_logic;
+ signal r_gcount_13: std_logic;
+ signal r_gcount_14: std_logic;
+ signal r_gcount_15: std_logic;
+ signal r_gcount_16: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal w_gcount_r213: std_logic;
+ signal w_gcount_r13: std_logic;
+ signal w_gcount_r214: std_logic;
+ signal w_gcount_r14: std_logic;
+ signal w_gcount_r215: std_logic;
+ signal w_gcount_r15: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal r_gcount_w210: std_logic;
+ signal r_gcount_w10: std_logic;
+ signal r_gcount_w211: std_logic;
+ signal r_gcount_w11: std_logic;
+ signal r_gcount_w212: std_logic;
+ signal r_gcount_w12: std_logic;
+ signal r_gcount_w213: std_logic;
+ signal r_gcount_w13: std_logic;
+ signal r_gcount_w214: std_logic;
+ signal r_gcount_w14: std_logic;
+ signal r_gcount_w215: std_logic;
+ signal r_gcount_w15: std_logic;
+ signal r_gcount_w216: std_logic;
+ signal r_gcount_w16: std_logic;
+ signal rcnt_reg_16: std_logic;
+ signal empty_i: std_logic;
+ signal full_i: std_logic;
+ signal rRst: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5: std_logic;
+ signal iwcount_14: std_logic;
+ signal iwcount_15: std_logic;
+ signal co7: std_logic;
+ signal wcount_15: std_logic;
+ signal co6: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_1: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_1: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co5_1: std_logic;
+ signal ircount_14: std_logic;
+ signal ircount_15: std_logic;
+ signal co6_1: std_logic;
+ signal ircount_16: std_logic;
+ signal co8: std_logic;
+ signal rcount_16: std_logic;
+ signal co7_1: std_logic;
+ signal mdout1_31_0: std_logic;
+ signal mdout1_30_0: std_logic;
+ signal mdout1_29_0: std_logic;
+ signal mdout1_28_0: std_logic;
+ signal mdout1_27_0: std_logic;
+ signal mdout1_26_0: std_logic;
+ signal mdout1_25_0: std_logic;
+ signal mdout1_24_0: std_logic;
+ signal mdout1_23_0: std_logic;
+ signal mdout1_22_0: std_logic;
+ signal mdout1_21_0: std_logic;
+ signal mdout1_20_0: std_logic;
+ signal mdout1_19_0: std_logic;
+ signal mdout1_18_0: std_logic;
+ signal mdout1_17_0: std_logic;
+ signal mdout1_16_0: std_logic;
+ signal mdout1_15_0: std_logic;
+ signal mdout1_14_0: std_logic;
+ signal mdout1_13_0: std_logic;
+ signal mdout1_12_0: std_logic;
+ signal mdout1_11_0: std_logic;
+ signal mdout1_10_0: std_logic;
+ signal mdout1_9_0: std_logic;
+ signal mdout1_8_0: std_logic;
+ signal mdout1_7_0: std_logic;
+ signal mdout1_6_0: std_logic;
+ signal mdout1_5_0: std_logic;
+ signal mdout1_4_0: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_31_1: std_logic;
+ signal mdout1_30_1: std_logic;
+ signal mdout1_29_1: std_logic;
+ signal mdout1_28_1: std_logic;
+ signal mdout1_27_1: std_logic;
+ signal mdout1_26_1: std_logic;
+ signal mdout1_25_1: std_logic;
+ signal mdout1_24_1: std_logic;
+ signal mdout1_23_1: std_logic;
+ signal mdout1_22_1: std_logic;
+ signal mdout1_21_1: std_logic;
+ signal mdout1_20_1: std_logic;
+ signal mdout1_19_1: std_logic;
+ signal mdout1_18_1: std_logic;
+ signal mdout1_17_1: std_logic;
+ signal mdout1_16_1: std_logic;
+ signal mdout1_15_1: std_logic;
+ signal mdout1_14_1: std_logic;
+ signal mdout1_13_1: std_logic;
+ signal mdout1_12_1: std_logic;
+ signal mdout1_11_1: std_logic;
+ signal mdout1_10_1: std_logic;
+ signal mdout1_9_1: std_logic;
+ signal mdout1_8_1: std_logic;
+ signal mdout1_7_1: std_logic;
+ signal mdout1_6_1: std_logic;
+ signal mdout1_5_1: std_logic;
+ signal mdout1_4_1: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_31_2: std_logic;
+ signal mdout1_30_2: std_logic;
+ signal mdout1_29_2: std_logic;
+ signal mdout1_28_2: std_logic;
+ signal mdout1_27_2: std_logic;
+ signal mdout1_26_2: std_logic;
+ signal mdout1_25_2: std_logic;
+ signal mdout1_24_2: std_logic;
+ signal mdout1_23_2: std_logic;
+ signal mdout1_22_2: std_logic;
+ signal mdout1_21_2: std_logic;
+ signal mdout1_20_2: std_logic;
+ signal mdout1_19_2: std_logic;
+ signal mdout1_18_2: std_logic;
+ signal mdout1_17_2: std_logic;
+ signal mdout1_16_2: std_logic;
+ signal mdout1_15_2: std_logic;
+ signal mdout1_14_2: std_logic;
+ signal mdout1_13_2: std_logic;
+ signal mdout1_12_2: std_logic;
+ signal mdout1_11_2: std_logic;
+ signal mdout1_10_2: std_logic;
+ signal mdout1_9_2: std_logic;
+ signal mdout1_8_2: std_logic;
+ signal mdout1_7_2: std_logic;
+ signal mdout1_6_2: std_logic;
+ signal mdout1_5_2: std_logic;
+ signal mdout1_4_2: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_31_3: std_logic;
+ signal mdout1_30_3: std_logic;
+ signal mdout1_29_3: std_logic;
+ signal mdout1_28_3: std_logic;
+ signal mdout1_27_3: std_logic;
+ signal mdout1_26_3: std_logic;
+ signal mdout1_25_3: std_logic;
+ signal mdout1_24_3: std_logic;
+ signal mdout1_23_3: std_logic;
+ signal mdout1_22_3: std_logic;
+ signal mdout1_21_3: std_logic;
+ signal mdout1_20_3: std_logic;
+ signal mdout1_19_3: std_logic;
+ signal mdout1_18_3: std_logic;
+ signal mdout1_17_3: std_logic;
+ signal mdout1_16_3: std_logic;
+ signal mdout1_15_3: std_logic;
+ signal mdout1_14_3: std_logic;
+ signal mdout1_13_3: std_logic;
+ signal mdout1_12_3: std_logic;
+ signal mdout1_11_3: std_logic;
+ signal mdout1_10_3: std_logic;
+ signal mdout1_9_3: std_logic;
+ signal mdout1_8_3: std_logic;
+ signal mdout1_7_3: std_logic;
+ signal mdout1_6_3: std_logic;
+ signal mdout1_5_3: std_logic;
+ signal mdout1_4_3: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_31_4: std_logic;
+ signal mdout1_30_4: std_logic;
+ signal mdout1_29_4: std_logic;
+ signal mdout1_28_4: std_logic;
+ signal mdout1_27_4: std_logic;
+ signal mdout1_26_4: std_logic;
+ signal mdout1_25_4: std_logic;
+ signal mdout1_24_4: std_logic;
+ signal mdout1_23_4: std_logic;
+ signal mdout1_22_4: std_logic;
+ signal mdout1_21_4: std_logic;
+ signal mdout1_20_4: std_logic;
+ signal mdout1_19_4: std_logic;
+ signal mdout1_18_4: std_logic;
+ signal mdout1_17_4: std_logic;
+ signal mdout1_16_4: std_logic;
+ signal mdout1_15_4: std_logic;
+ signal mdout1_14_4: std_logic;
+ signal mdout1_13_4: std_logic;
+ signal mdout1_12_4: std_logic;
+ signal mdout1_11_4: std_logic;
+ signal mdout1_10_4: std_logic;
+ signal mdout1_9_4: std_logic;
+ signal mdout1_8_4: std_logic;
+ signal mdout1_7_4: std_logic;
+ signal mdout1_6_4: std_logic;
+ signal mdout1_5_4: std_logic;
+ signal mdout1_4_4: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_31_5: std_logic;
+ signal mdout1_30_5: std_logic;
+ signal mdout1_29_5: std_logic;
+ signal mdout1_28_5: std_logic;
+ signal mdout1_27_5: std_logic;
+ signal mdout1_26_5: std_logic;
+ signal mdout1_25_5: std_logic;
+ signal mdout1_24_5: std_logic;
+ signal mdout1_23_5: std_logic;
+ signal mdout1_22_5: std_logic;
+ signal mdout1_21_5: std_logic;
+ signal mdout1_20_5: std_logic;
+ signal mdout1_19_5: std_logic;
+ signal mdout1_18_5: std_logic;
+ signal mdout1_17_5: std_logic;
+ signal mdout1_16_5: std_logic;
+ signal mdout1_15_5: std_logic;
+ signal mdout1_14_5: std_logic;
+ signal mdout1_13_5: std_logic;
+ signal mdout1_12_5: std_logic;
+ signal mdout1_11_5: std_logic;
+ signal mdout1_10_5: std_logic;
+ signal mdout1_9_5: std_logic;
+ signal mdout1_8_5: std_logic;
+ signal mdout1_7_5: std_logic;
+ signal mdout1_6_5: std_logic;
+ signal mdout1_5_5: std_logic;
+ signal mdout1_4_5: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_31_6: std_logic;
+ signal mdout1_30_6: std_logic;
+ signal mdout1_29_6: std_logic;
+ signal mdout1_28_6: std_logic;
+ signal mdout1_27_6: std_logic;
+ signal mdout1_26_6: std_logic;
+ signal mdout1_25_6: std_logic;
+ signal mdout1_24_6: std_logic;
+ signal mdout1_23_6: std_logic;
+ signal mdout1_22_6: std_logic;
+ signal mdout1_21_6: std_logic;
+ signal mdout1_20_6: std_logic;
+ signal mdout1_19_6: std_logic;
+ signal mdout1_18_6: std_logic;
+ signal mdout1_17_6: std_logic;
+ signal mdout1_16_6: std_logic;
+ signal mdout1_15_6: std_logic;
+ signal mdout1_14_6: std_logic;
+ signal mdout1_13_6: std_logic;
+ signal mdout1_12_6: std_logic;
+ signal mdout1_11_6: std_logic;
+ signal mdout1_10_6: std_logic;
+ signal mdout1_9_6: std_logic;
+ signal mdout1_8_6: std_logic;
+ signal mdout1_7_6: std_logic;
+ signal mdout1_6_6: std_logic;
+ signal mdout1_5_6: std_logic;
+ signal mdout1_4_6: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_31_7: std_logic;
+ signal mdout1_30_7: std_logic;
+ signal mdout1_29_7: std_logic;
+ signal mdout1_28_7: std_logic;
+ signal mdout1_27_7: std_logic;
+ signal mdout1_26_7: std_logic;
+ signal mdout1_25_7: std_logic;
+ signal mdout1_24_7: std_logic;
+ signal mdout1_23_7: std_logic;
+ signal mdout1_22_7: std_logic;
+ signal mdout1_21_7: std_logic;
+ signal mdout1_20_7: std_logic;
+ signal mdout1_19_7: std_logic;
+ signal mdout1_18_7: std_logic;
+ signal mdout1_17_7: std_logic;
+ signal mdout1_16_7: std_logic;
+ signal mdout1_15_7: std_logic;
+ signal mdout1_14_7: std_logic;
+ signal mdout1_13_7: std_logic;
+ signal mdout1_12_7: std_logic;
+ signal mdout1_11_7: std_logic;
+ signal mdout1_10_7: std_logic;
+ signal mdout1_9_7: std_logic;
+ signal mdout1_8_7: std_logic;
+ signal mdout1_7_7: std_logic;
+ signal mdout1_6_7: std_logic;
+ signal mdout1_5_7: std_logic;
+ signal mdout1_4_7: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal rptr_15_ff: std_logic;
+ signal rptr_14_ff: std_logic;
+ signal rptr_13_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal mdout1_31_8: std_logic;
+ signal mdout1_30_8: std_logic;
+ signal mdout1_29_8: std_logic;
+ signal mdout1_28_8: std_logic;
+ signal mdout1_27_8: std_logic;
+ signal mdout1_26_8: std_logic;
+ signal mdout1_25_8: std_logic;
+ signal mdout1_24_8: std_logic;
+ signal mdout1_23_8: std_logic;
+ signal mdout1_22_8: std_logic;
+ signal mdout1_21_8: std_logic;
+ signal mdout1_20_8: std_logic;
+ signal mdout1_19_8: std_logic;
+ signal mdout1_18_8: std_logic;
+ signal mdout1_17_8: std_logic;
+ signal mdout1_16_8: std_logic;
+ signal mdout1_15_8: std_logic;
+ signal mdout1_14_8: std_logic;
+ signal mdout1_13_8: std_logic;
+ signal mdout1_12_8: std_logic;
+ signal mdout1_11_8: std_logic;
+ signal mdout1_10_8: std_logic;
+ signal mdout1_9_8: std_logic;
+ signal mdout1_8_8: std_logic;
+ signal mdout1_7_8: std_logic;
+ signal mdout1_6_8: std_logic;
+ signal mdout1_5_8: std_logic;
+ signal mdout1_4_8: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal co4_2: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal co5_2: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal wcnt_sub_14: std_logic;
+ signal co6_2: std_logic;
+ signal wcnt_sub_15: std_logic;
+ signal co7_2: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal rcnt_sub_0: std_logic;
+ signal rcnt_sub_1: std_logic;
+ signal rcnt_sub_2: std_logic;
+ signal co0_3: std_logic;
+ signal rcnt_sub_3: std_logic;
+ signal rcnt_sub_4: std_logic;
+ signal co1_3: std_logic;
+ signal rcnt_sub_5: std_logic;
+ signal rcnt_sub_6: std_logic;
+ signal co2_3: std_logic;
+ signal rcnt_sub_7: std_logic;
+ signal rcnt_sub_8: std_logic;
+ signal co3_3: std_logic;
+ signal rcnt_sub_9: std_logic;
+ signal rcnt_sub_10: std_logic;
+ signal co4_3: std_logic;
+ signal rcnt_sub_11: std_logic;
+ signal rcnt_sub_12: std_logic;
+ signal co5_3: std_logic;
+ signal rcnt_sub_13: std_logic;
+ signal rcnt_sub_14: std_logic;
+ signal co6_3: std_logic;
+ signal rcnt_sub_15: std_logic;
+ signal rcnt_sub_16: std_logic;
+ signal co7_3: std_logic;
+ signal rcnt_sub_msb: std_logic;
+ signal co8_1d: std_logic;
+ signal co8_1: std_logic;
+ signal wfill_sub_0: std_logic;
+ signal wptr_0: std_logic;
+ signal wfill_sub_1: std_logic;
+ signal wfill_sub_2: std_logic;
+ signal co0_4: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wfill_sub_3: std_logic;
+ signal wfill_sub_4: std_logic;
+ signal co1_4: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wfill_sub_5: std_logic;
+ signal wfill_sub_6: std_logic;
+ signal co2_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wfill_sub_7: std_logic;
+ signal wfill_sub_8: std_logic;
+ signal co3_4: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wfill_sub_9: std_logic;
+ signal wfill_sub_10: std_logic;
+ signal co4_4: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wfill_sub_11: std_logic;
+ signal wfill_sub_12: std_logic;
+ signal co5_4: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wfill_sub_13: std_logic;
+ signal wfill_sub_14: std_logic;
+ signal co6_4: std_logic;
+ signal wptr_13: std_logic;
+ signal wptr_14: std_logic;
+ signal wfill_sub_15: std_logic;
+ signal co7_4: std_logic;
+ signal wfill_sub_msb: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal rfill_sub_10: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_9: std_logic;
+ signal rptr_10: std_logic;
+ signal rfill_sub_11: std_logic;
+ signal rfill_sub_12: std_logic;
+ signal co5_5: std_logic;
+ signal rptr_11: std_logic;
+ signal rptr_12: std_logic;
+ signal rfill_sub_13: std_logic;
+ signal rfill_sub_14: std_logic;
+ signal co6_5: std_logic;
+ signal rptr_13: std_logic;
+ signal rptr_14: std_logic;
+ signal rfill_sub_15: std_logic;
+ signal rfill_sub_16: std_logic;
+ signal co7_5: std_logic;
+ signal rptr_15: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal co8_2d: std_logic;
+ signal co8_2: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r2: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcount_r3: std_logic;
+ signal wcount_r4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcount_r5: std_logic;
+ signal wcount_r6: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcount_r7: std_logic;
+ signal wcount_r8: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcount_r9: std_logic;
+ signal wcount_r10: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcount_r11: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal co6_6: std_logic;
+ signal wcount_r13: std_logic;
+ signal wcount_r14: std_logic;
+ signal rcount_14: std_logic;
+ signal rcount_15: std_logic;
+ signal co7_6: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w1: std_logic;
+ signal rcount_w2: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_7: std_logic;
+ signal rcount_w3: std_logic;
+ signal rcount_w4: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_7: std_logic;
+ signal rcount_w5: std_logic;
+ signal rcount_w6: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_7: std_logic;
+ signal rcount_w7: std_logic;
+ signal rcount_w8: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_7: std_logic;
+ signal rcount_w9: std_logic;
+ signal rcount_w10: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_7: std_logic;
+ signal rcount_w11: std_logic;
+ signal rcount_w12: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_7: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w14: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal co6_7: std_logic;
+ signal rcount_w15: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_14: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcnt_reg_0: std_logic;
+ signal rcnt_reg_1: std_logic;
+ signal co0_8: std_logic;
+ signal rcnt_reg_2: std_logic;
+ signal rcnt_reg_3: std_logic;
+ signal co1_8: std_logic;
+ signal rcnt_reg_4: std_logic;
+ signal rcnt_reg_5: std_logic;
+ signal co2_8: std_logic;
+ signal rcnt_reg_6: std_logic;
+ signal rcnt_reg_7: std_logic;
+ signal co3_8: std_logic;
+ signal rcnt_reg_8: std_logic;
+ signal rcnt_reg_9: std_logic;
+ signal co4_8: std_logic;
+ signal rcnt_reg_10: std_logic;
+ signal rcnt_reg_11: std_logic;
+ signal co5_8: std_logic;
+ signal rcnt_reg_12: std_logic;
+ signal rcnt_reg_13: std_logic;
+ signal co6_8: std_logic;
+ signal rcnt_reg_14: std_logic;
+ signal rcnt_reg_15: std_logic;
+ signal co7_7: std_logic;
+ signal ae_clrsig: std_logic;
+ signal ae_setsig: std_logic;
+ signal ae_d: std_logic;
+ signal ae_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_3: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_9: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_9: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_9: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_9: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_9: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_9: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal co6_9: std_logic;
+ signal wcnt_reg_14: std_logic;
+ signal wcnt_reg_15: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component MUX321
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; D8: in std_logic;
+ D9: in std_logic; D10: in std_logic; D11: in std_logic;
+ D12: in std_logic; D13: in std_logic; D14: in std_logic;
+ D15: in std_logic; D16: in std_logic; D17: in std_logic;
+ D18: in std_logic; D19: in std_logic; D20: in std_logic;
+ D21: in std_logic; D22: in std_logic; D23: in std_logic;
+ D24: in std_logic; D25: in std_logic; D26: in std_logic;
+ D27: in std_logic; D28: in std_logic; D29: in std_logic;
+ D30: in std_logic; D31: in std_logic; SD1: in std_logic;
+ SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
+ SD5: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_180 : label is "0x8000";
+ attribute initval of LUT4_179 : label is "0x8000";
+ attribute initval of LUT4_178 : label is "0x8000";
+ attribute initval of LUT4_177 : label is "0x8000";
+ attribute initval of LUT4_176 : label is "0x8000";
+ attribute initval of LUT4_175 : label is "0x8000";
+ attribute initval of LUT4_174 : label is "0x8000";
+ attribute initval of LUT4_173 : label is "0x8000";
+ attribute initval of LUT4_172 : label is "0x8000";
+ attribute initval of LUT4_171 : label is "0x8000";
+ attribute initval of LUT4_170 : label is "0x8000";
+ attribute initval of LUT4_169 : label is "0x8000";
+ attribute initval of LUT4_168 : label is "0x8000";
+ attribute initval of LUT4_167 : label is "0x8000";
+ attribute initval of LUT4_166 : label is "0x8000";
+ attribute initval of LUT4_165 : label is "0x8000";
+ attribute initval of LUT4_164 : label is "0x8000";
+ attribute initval of LUT4_163 : label is "0x8000";
+ attribute initval of LUT4_162 : label is "0x8000";
+ attribute initval of LUT4_161 : label is "0x8000";
+ attribute initval of LUT4_160 : label is "0x8000";
+ attribute initval of LUT4_159 : label is "0x8000";
+ attribute initval of LUT4_158 : label is "0x8000";
+ attribute initval of LUT4_157 : label is "0x8000";
+ attribute initval of LUT4_156 : label is "0x8000";
+ attribute initval of LUT4_155 : label is "0x8000";
+ attribute initval of LUT4_154 : label is "0x8000";
+ attribute initval of LUT4_153 : label is "0x8000";
+ attribute initval of LUT4_152 : label is "0x8000";
+ attribute initval of LUT4_151 : label is "0x8000";
+ attribute initval of LUT4_150 : label is "0x8000";
+ attribute initval of LUT4_149 : label is "0x8000";
+ attribute initval of LUT4_148 : label is "0x8000";
+ attribute initval of LUT4_147 : label is "0x8000";
+ attribute initval of LUT4_146 : label is "0x8000";
+ attribute initval of LUT4_145 : label is "0x8000";
+ attribute initval of LUT4_144 : label is "0x8000";
+ attribute initval of LUT4_143 : label is "0x8000";
+ attribute initval of LUT4_142 : label is "0x8000";
+ attribute initval of LUT4_141 : label is "0x8000";
+ attribute initval of LUT4_140 : label is "0x8000";
+ attribute initval of LUT4_139 : label is "0x8000";
+ attribute initval of LUT4_138 : label is "0x8000";
+ attribute initval of LUT4_137 : label is "0x8000";
+ attribute initval of LUT4_136 : label is "0x8000";
+ attribute initval of LUT4_135 : label is "0x8000";
+ attribute initval of LUT4_134 : label is "0x8000";
+ attribute initval of LUT4_133 : label is "0x8000";
+ attribute initval of LUT4_132 : label is "0x8000";
+ attribute initval of LUT4_131 : label is "0x8000";
+ attribute initval of LUT4_130 : label is "0x8000";
+ attribute initval of LUT4_129 : label is "0x8000";
+ attribute initval of LUT4_128 : label is "0x8000";
+ attribute initval of LUT4_127 : label is "0x8000";
+ attribute initval of LUT4_126 : label is "0x8000";
+ attribute initval of LUT4_125 : label is "0x8000";
+ attribute initval of LUT4_124 : label is "0x8000";
+ attribute initval of LUT4_123 : label is "0x8000";
+ attribute initval of LUT4_122 : label is "0x8000";
+ attribute initval of LUT4_121 : label is "0x8000";
+ attribute initval of LUT4_120 : label is "0x8000";
+ attribute initval of LUT4_119 : label is "0x8000";
+ attribute initval of LUT4_118 : label is "0x8000";
+ attribute initval of LUT4_117 : label is "0x8000";
+ attribute initval of LUT4_116 : label is "0x8000";
+ attribute initval of LUT4_115 : label is "0x8000";
+ attribute initval of LUT4_114 : label is "0x8000";
+ attribute initval of LUT4_113 : label is "0x8000";
+ attribute initval of LUT4_112 : label is "0x8000";
+ attribute initval of LUT4_111 : label is "0x8000";
+ attribute initval of LUT4_110 : label is "0x8000";
+ attribute initval of LUT4_109 : label is "0x8000";
+ attribute initval of LUT4_108 : label is "0x8000";
+ attribute initval of LUT4_107 : label is "0x8000";
+ attribute initval of LUT4_106 : label is "0x8000";
+ attribute initval of LUT4_105 : label is "0x8000";
+ attribute initval of LUT4_104 : label is "0x8000";
+ attribute initval of LUT4_103 : label is "0x8000";
+ attribute initval of LUT4_102 : label is "0x8000";
+ attribute initval of LUT4_101 : label is "0x8000";
+ attribute initval of LUT4_100 : label is "0x8000";
+ attribute initval of LUT4_99 : label is "0x8000";
+ attribute initval of LUT4_98 : label is "0x8000";
+ attribute initval of LUT4_97 : label is "0x8000";
+ attribute initval of LUT4_96 : label is "0x8000";
+ attribute initval of LUT4_95 : label is "0x8000";
+ attribute initval of LUT4_94 : label is "0x8000";
+ attribute initval of LUT4_93 : label is "0x8000";
+ attribute initval of LUT4_92 : label is "0x8000";
+ attribute initval of LUT4_91 : label is "0x8000";
+ attribute initval of LUT4_90 : label is "0x8000";
+ attribute initval of LUT4_89 : label is "0x8000";
+ attribute initval of LUT4_88 : label is "0x8000";
+ attribute initval of LUT4_87 : label is "0x8000";
+ attribute initval of LUT4_86 : label is "0x8000";
+ attribute initval of LUT4_85 : label is "0x8000";
+ attribute initval of LUT4_84 : label is "0x8000";
+ attribute initval of LUT4_83 : label is "0x8000";
+ attribute initval of LUT4_82 : label is "0x8000";
+ attribute initval of LUT4_81 : label is "0x8000";
+ attribute initval of LUT4_80 : label is "0x8000";
+ attribute initval of LUT4_79 : label is "0x8000";
+ attribute initval of LUT4_78 : label is "0x8000";
+ attribute initval of LUT4_77 : label is "0x8000";
+ attribute initval of LUT4_76 : label is "0x8000";
+ attribute initval of LUT4_75 : label is "0x8000";
+ attribute initval of LUT4_74 : label is "0x8000";
+ attribute initval of LUT4_73 : label is "0x8000";
+ attribute initval of LUT4_72 : label is "0x8000";
+ attribute initval of LUT4_71 : label is "0x8000";
+ attribute initval of LUT4_70 : label is "0x8000";
+ attribute initval of LUT4_69 : label is "0x8000";
+ attribute initval of LUT4_68 : label is "0x8000";
+ attribute initval of LUT4_67 : label is "0x8000";
+ attribute initval of LUT4_66 : label is "0x8000";
+ attribute initval of LUT4_65 : label is "0x8000";
+ attribute initval of LUT4_64 : label is "0x8000";
+ attribute initval of LUT4_63 : label is "0x8000";
+ attribute initval of LUT4_62 : label is "0x8000";
+ attribute initval of LUT4_61 : label is "0x8000";
+ attribute initval of LUT4_60 : label is "0x8000";
+ attribute initval of LUT4_59 : label is "0x8000";
+ attribute initval of LUT4_58 : label is "0x8000";
+ attribute initval of LUT4_57 : label is "0x8000";
+ attribute initval of LUT4_56 : label is "0x8000";
+ attribute initval of LUT4_55 : label is "0x8000";
+ attribute initval of LUT4_54 : label is "0x8000";
+ attribute initval of LUT4_53 : label is "0x8000";
+ attribute initval of LUT4_52 : label is "0x6996";
+ attribute initval of LUT4_51 : label is "0x6996";
+ attribute initval of LUT4_50 : label is "0x6996";
+ attribute initval of LUT4_49 : label is "0x6996";
+ attribute initval of LUT4_48 : label is "0x6996";
+ attribute initval of LUT4_47 : label is "0x6996";
+ attribute initval of LUT4_46 : label is "0x6996";
+ attribute initval of LUT4_45 : label is "0x6996";
+ attribute initval of LUT4_44 : label is "0x6996";
+ attribute initval of LUT4_43 : label is "0x6996";
+ attribute initval of LUT4_42 : label is "0x6996";
+ attribute initval of LUT4_41 : label is "0x6996";
+ attribute initval of LUT4_40 : label is "0x6996";
+ attribute initval of LUT4_39 : label is "0x6996";
+ attribute initval of LUT4_38 : label is "0x6996";
+ attribute initval of LUT4_37 : label is "0x6996";
+ attribute initval of LUT4_36 : label is "0x6996";
+ attribute initval of LUT4_35 : label is "0x6996";
+ attribute initval of LUT4_34 : label is "0x6996";
+ attribute initval of LUT4_33 : label is "0x6996";
+ attribute initval of LUT4_32 : label is "0x6996";
+ attribute initval of LUT4_31 : label is "0x6996";
+ attribute initval of LUT4_30 : label is "0x6996";
+ attribute initval of LUT4_29 : label is "0x6996";
+ attribute initval of LUT4_28 : label is "0x6996";
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_0_30 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_0_29 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_0_28 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
+ attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL";
+ attribute GSR of pdp_ram_4_0_27 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
+ attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL";
+ attribute GSR of pdp_ram_5_0_26 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
+ attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL";
+ attribute GSR of pdp_ram_6_0_25 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_6_0_25 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_6_0_25 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
+ attribute CSDECODE_B of pdp_ram_7_0_24 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_7_0_24 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_7_0_24 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_7_0_24 : label is "NORMAL";
+ attribute GSR of pdp_ram_7_0_24 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_0_24 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_7_0_24 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_7_0_24 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_7_0_24 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_7_0_24 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
+ attribute CSDECODE_B of pdp_ram_8_0_23 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_8_0_23 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_8_0_23 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_8_0_23 : label is "NORMAL";
+ attribute GSR of pdp_ram_8_0_23 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_0_23 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_8_0_23 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_8_0_23 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_8_0_23 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_8_0_23 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
+ attribute CSDECODE_B of pdp_ram_9_0_22 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_9_0_22 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_9_0_22 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_9_0_22 : label is "NORMAL";
+ attribute GSR of pdp_ram_9_0_22 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_0_22 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_9_0_22 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_9_0_22 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_9_0_22 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_9_0_22 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
+ attribute CSDECODE_B of pdp_ram_10_0_21 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_10_0_21 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_10_0_21 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_10_0_21 : label is "NORMAL";
+ attribute GSR of pdp_ram_10_0_21 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_0_21 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_10_0_21 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_10_0_21 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_10_0_21 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_10_0_21 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
+ attribute CSDECODE_B of pdp_ram_11_0_20 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_11_0_20 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_11_0_20 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_11_0_20 : label is "NORMAL";
+ attribute GSR of pdp_ram_11_0_20 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_0_20 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_11_0_20 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_11_0_20 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_11_0_20 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_11_0_20 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
+ attribute CSDECODE_B of pdp_ram_12_0_19 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_12_0_19 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_12_0_19 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_12_0_19 : label is "NORMAL";
+ attribute GSR of pdp_ram_12_0_19 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_0_19 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_12_0_19 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_12_0_19 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_12_0_19 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_12_0_19 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
+ attribute CSDECODE_B of pdp_ram_13_0_18 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_13_0_18 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_13_0_18 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_13_0_18 : label is "NORMAL";
+ attribute GSR of pdp_ram_13_0_18 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_0_18 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_13_0_18 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_13_0_18 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_13_0_18 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_13_0_18 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
+ attribute CSDECODE_B of pdp_ram_14_0_17 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_14_0_17 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_14_0_17 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_14_0_17 : label is "NORMAL";
+ attribute GSR of pdp_ram_14_0_17 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_0_17 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_14_0_17 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_14_0_17 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_14_0_17 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_14_0_17 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
+ attribute CSDECODE_B of pdp_ram_15_0_16 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_15_0_16 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_15_0_16 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_15_0_16 : label is "NORMAL";
+ attribute GSR of pdp_ram_15_0_16 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_0_16 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_15_0_16 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_15_0_16 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_15_0_16 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_15_0_16 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
+ attribute CSDECODE_B of pdp_ram_16_0_15 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_16_0_15 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_16_0_15 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_16_0_15 : label is "NORMAL";
+ attribute GSR of pdp_ram_16_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_16_0_15 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_16_0_15 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_16_0_15 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_16_0_15 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_16_0_15 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
+ attribute CSDECODE_B of pdp_ram_17_0_14 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_17_0_14 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_17_0_14 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_17_0_14 : label is "NORMAL";
+ attribute GSR of pdp_ram_17_0_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_17_0_14 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_17_0_14 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_17_0_14 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_17_0_14 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_17_0_14 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
+ attribute CSDECODE_B of pdp_ram_18_0_13 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_18_0_13 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_18_0_13 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_18_0_13 : label is "NORMAL";
+ attribute GSR of pdp_ram_18_0_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_18_0_13 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_18_0_13 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_18_0_13 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_18_0_13 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_18_0_13 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
+ attribute CSDECODE_B of pdp_ram_19_0_12 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_19_0_12 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_19_0_12 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_19_0_12 : label is "NORMAL";
+ attribute GSR of pdp_ram_19_0_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_19_0_12 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_19_0_12 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_19_0_12 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_19_0_12 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_19_0_12 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
+ attribute CSDECODE_B of pdp_ram_20_0_11 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_20_0_11 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_20_0_11 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_20_0_11 : label is "NORMAL";
+ attribute GSR of pdp_ram_20_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_20_0_11 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_20_0_11 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_20_0_11 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_20_0_11 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_20_0_11 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
+ attribute CSDECODE_B of pdp_ram_21_0_10 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_21_0_10 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_21_0_10 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_21_0_10 : label is "NORMAL";
+ attribute GSR of pdp_ram_21_0_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_21_0_10 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_21_0_10 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_21_0_10 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_21_0_10 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_21_0_10 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
+ attribute CSDECODE_B of pdp_ram_22_0_9 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_22_0_9 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_22_0_9 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_22_0_9 : label is "NORMAL";
+ attribute GSR of pdp_ram_22_0_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_22_0_9 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_22_0_9 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_22_0_9 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_22_0_9 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_22_0_9 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
+ attribute CSDECODE_B of pdp_ram_23_0_8 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_23_0_8 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_23_0_8 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_23_0_8 : label is "NORMAL";
+ attribute GSR of pdp_ram_23_0_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_23_0_8 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_23_0_8 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_23_0_8 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_23_0_8 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_23_0_8 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
+ attribute CSDECODE_B of pdp_ram_24_0_7 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_24_0_7 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_24_0_7 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_24_0_7 : label is "NORMAL";
+ attribute GSR of pdp_ram_24_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_24_0_7 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_24_0_7 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_24_0_7 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_24_0_7 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_24_0_7 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
+ attribute CSDECODE_B of pdp_ram_25_0_6 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_25_0_6 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_25_0_6 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_25_0_6 : label is "NORMAL";
+ attribute GSR of pdp_ram_25_0_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_25_0_6 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_25_0_6 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_25_0_6 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_25_0_6 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_25_0_6 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
+ attribute CSDECODE_B of pdp_ram_26_0_5 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_26_0_5 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_26_0_5 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_26_0_5 : label is "NORMAL";
+ attribute GSR of pdp_ram_26_0_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
+ attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL";
+ attribute GSR of pdp_ram_27_0_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
+ attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL";
+ attribute GSR of pdp_ram_28_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
+ attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL";
+ attribute GSR of pdp_ram_29_0_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
+ attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL";
+ attribute GSR of pdp_ram_30_0_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_31_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "18";
+ attribute GSR of FF_239 : label is "ENABLED";
+ attribute GSR of FF_238 : label is "ENABLED";
+ attribute GSR of FF_237 : label is "ENABLED";
+ attribute GSR of FF_236 : label is "ENABLED";
+ attribute GSR of FF_235 : label is "ENABLED";
+ attribute GSR of FF_234 : label is "ENABLED";
+ attribute GSR of FF_233 : label is "ENABLED";
+ attribute GSR of FF_232 : label is "ENABLED";
+ attribute GSR of FF_231 : label is "ENABLED";
+ attribute GSR of FF_230 : label is "ENABLED";
+ attribute GSR of FF_229 : label is "ENABLED";
+ attribute GSR of FF_228 : label is "ENABLED";
+ attribute GSR of FF_227 : label is "ENABLED";
+ attribute GSR of FF_226 : label is "ENABLED";
+ attribute GSR of FF_225 : label is "ENABLED";
+ attribute GSR of FF_224 : label is "ENABLED";
+ attribute GSR of FF_223 : label is "ENABLED";
+ attribute GSR of FF_222 : label is "ENABLED";
+ attribute GSR of FF_221 : label is "ENABLED";
+ attribute GSR of FF_220 : label is "ENABLED";
+ attribute GSR of FF_219 : label is "ENABLED";
+ attribute GSR of FF_218 : label is "ENABLED";
+ attribute GSR of FF_217 : label is "ENABLED";
+ attribute GSR of FF_216 : label is "ENABLED";
+ attribute GSR of FF_215 : label is "ENABLED";
+ attribute GSR of FF_214 : label is "ENABLED";
+ attribute GSR of FF_213 : label is "ENABLED";
+ attribute GSR of FF_212 : label is "ENABLED";
+ attribute GSR of FF_211 : label is "ENABLED";
+ attribute GSR of FF_210 : label is "ENABLED";
+ attribute GSR of FF_209 : label is "ENABLED";
+ attribute GSR of FF_208 : label is "ENABLED";
+ attribute GSR of FF_207 : label is "ENABLED";
+ attribute GSR of FF_206 : label is "ENABLED";
+ attribute GSR of FF_205 : label is "ENABLED";
+ attribute GSR of FF_204 : label is "ENABLED";
+ attribute GSR of FF_203 : label is "ENABLED";
+ attribute GSR of FF_202 : label is "ENABLED";
+ attribute GSR of FF_201 : label is "ENABLED";
+ attribute GSR of FF_200 : label is "ENABLED";
+ attribute GSR of FF_199 : label is "ENABLED";
+ attribute GSR of FF_198 : label is "ENABLED";
+ attribute GSR of FF_197 : label is "ENABLED";
+ attribute GSR of FF_196 : label is "ENABLED";
+ attribute GSR of FF_195 : label is "ENABLED";
+ attribute GSR of FF_194 : label is "ENABLED";
+ attribute GSR of FF_193 : label is "ENABLED";
+ attribute GSR of FF_192 : label is "ENABLED";
+ attribute GSR of FF_191 : label is "ENABLED";
+ attribute GSR of FF_190 : label is "ENABLED";
+ attribute GSR of FF_189 : label is "ENABLED";
+ attribute GSR of FF_188 : label is "ENABLED";
+ attribute GSR of FF_187 : label is "ENABLED";
+ attribute GSR of FF_186 : label is "ENABLED";
+ attribute GSR of FF_185 : label is "ENABLED";
+ attribute GSR of FF_184 : label is "ENABLED";
+ attribute GSR of FF_183 : label is "ENABLED";
+ attribute GSR of FF_182 : label is "ENABLED";
+ attribute GSR of FF_181 : label is "ENABLED";
+ attribute GSR of FF_180 : label is "ENABLED";
+ attribute GSR of FF_179 : label is "ENABLED";
+ attribute GSR of FF_178 : label is "ENABLED";
+ attribute GSR of FF_177 : label is "ENABLED";
+ attribute GSR of FF_176 : label is "ENABLED";
+ attribute GSR of FF_175 : label is "ENABLED";
+ attribute GSR of FF_174 : label is "ENABLED";
+ attribute GSR of FF_173 : label is "ENABLED";
+ attribute GSR of FF_172 : label is "ENABLED";
+ attribute GSR of FF_171 : label is "ENABLED";
+ attribute GSR of FF_170 : label is "ENABLED";
+ attribute GSR of FF_169 : label is "ENABLED";
+ attribute GSR of FF_168 : label is "ENABLED";
+ attribute GSR of FF_167 : label is "ENABLED";
+ attribute GSR of FF_166 : label is "ENABLED";
+ attribute GSR of FF_165 : label is "ENABLED";
+ attribute GSR of FF_164 : label is "ENABLED";
+ attribute GSR of FF_163 : label is "ENABLED";
+ attribute GSR of FF_162 : label is "ENABLED";
+ attribute GSR of FF_161 : label is "ENABLED";
+ attribute GSR of FF_160 : label is "ENABLED";
+ attribute GSR of FF_159 : label is "ENABLED";
+ attribute GSR of FF_158 : label is "ENABLED";
+ attribute GSR of FF_157 : label is "ENABLED";
+ attribute GSR of FF_156 : label is "ENABLED";
+ attribute GSR of FF_155 : label is "ENABLED";
+ attribute GSR of FF_154 : label is "ENABLED";
+ attribute GSR of FF_153 : label is "ENABLED";
+ attribute GSR of FF_152 : label is "ENABLED";
+ attribute GSR of FF_151 : label is "ENABLED";
+ attribute GSR of FF_150 : label is "ENABLED";
+ attribute GSR of FF_149 : label is "ENABLED";
+ attribute GSR of FF_148 : label is "ENABLED";
+ attribute GSR of FF_147 : label is "ENABLED";
+ attribute GSR of FF_146 : label is "ENABLED";
+ attribute GSR of FF_145 : label is "ENABLED";
+ attribute GSR of FF_144 : label is "ENABLED";
+ attribute GSR of FF_143 : label is "ENABLED";
+ attribute GSR of FF_142 : label is "ENABLED";
+ attribute GSR of FF_141 : label is "ENABLED";
+ attribute GSR of FF_140 : label is "ENABLED";
+ attribute GSR of FF_139 : label is "ENABLED";
+ attribute GSR of FF_138 : label is "ENABLED";
+ attribute GSR of FF_137 : label is "ENABLED";
+ attribute GSR of FF_136 : label is "ENABLED";
+ attribute GSR of FF_135 : label is "ENABLED";
+ attribute GSR of FF_134 : label is "ENABLED";
+ attribute GSR of FF_133 : label is "ENABLED";
+ attribute GSR of FF_132 : label is "ENABLED";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t39: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_12: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t38: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_11: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t37: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t36: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t35: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t34: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t33: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t32: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t31: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t30: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t29: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t28: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t27: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t26: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t25: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t24: XOR2
+ port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
+
+ XOR2_t23: XOR2
+ port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
+
+ XOR2_t22: XOR2
+ port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
+
+ XOR2_t21: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t20: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t19: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t18: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t17: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t16: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t15: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t14: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t13: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ XOR2_t12: XOR2
+ port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+ XOR2_t11: XOR2
+ port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+ XOR2_t10: XOR2
+ port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
+
+ INV_10: INV
+ port map (A=>wptr_10, Z=>wptr_10_inv);
+
+ INV_9: INV
+ port map (A=>wptr_11, Z=>wptr_11_inv);
+
+ INV_8: INV
+ port map (A=>wptr_12, Z=>wptr_12_inv);
+
+ INV_7: INV
+ port map (A=>wptr_13, Z=>wptr_13_inv);
+
+ INV_6: INV
+ port map (A=>wptr_14, Z=>wptr_14_inv);
+
+ LUT4_180: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet);
+
+ LUT4_179: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_p00);
+
+ INV_5: INV
+ port map (A=>rptr_11, Z=>rptr_11_inv);
+
+ INV_4: INV
+ port map (A=>rptr_12, Z=>rptr_12_inv);
+
+ INV_3: INV
+ port map (A=>rptr_13, Z=>rptr_13_inv);
+
+ INV_2: INV
+ port map (A=>rptr_14, Z=>rptr_14_inv);
+
+ INV_1: INV
+ port map (A=>rptr_15, Z=>rptr_15_inv);
+
+ LUT4_178: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_1);
+
+ LUT4_177: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec1_r10);
+
+ LUT4_176: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_2);
+
+ LUT4_175: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec2_p01);
+
+ LUT4_174: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_3);
+
+ LUT4_173: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec3_r11);
+
+ LUT4_172: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_4);
+
+ LUT4_171: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec4_p02);
+
+ LUT4_170: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_5);
+
+ LUT4_169: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec5_r12);
+
+ LUT4_168: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_6);
+
+ LUT4_167: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec6_p03);
+
+ LUT4_166: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_7);
+
+ LUT4_165: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec7_r13);
+
+ LUT4_164: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_8);
+
+ LUT4_163: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec8_p04);
+
+ LUT4_162: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_9);
+
+ LUT4_161: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec9_r14);
+
+ LUT4_160: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_10);
+
+ LUT4_159: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
+
+ LUT4_158: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_11);
+
+ LUT4_157: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
+
+ LUT4_156: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_12);
+
+ LUT4_155: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
+
+ LUT4_154: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_13);
+
+ LUT4_153: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
+
+ LUT4_152: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_14);
+
+ LUT4_151: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
+
+ LUT4_150: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_15);
+
+ LUT4_149: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
+
+ LUT4_148: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_16);
+
+ LUT4_147: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
+
+ LUT4_146: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_17);
+
+ LUT4_145: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
+
+ LUT4_144: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_18);
+
+ LUT4_143: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
+
+ LUT4_142: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_19);
+
+ LUT4_141: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
+
+ LUT4_140: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_20);
+
+ LUT4_139: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
+
+ LUT4_138: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_21);
+
+ LUT4_137: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
+
+ LUT4_136: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_22);
+
+ LUT4_135: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
+
+ LUT4_134: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_23);
+
+ LUT4_133: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
+
+ LUT4_132: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_24);
+
+ LUT4_131: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
+
+ LUT4_130: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_25);
+
+ LUT4_129: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
+
+ LUT4_128: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_26);
+
+ LUT4_127: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
+
+ LUT4_126: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_27);
+
+ LUT4_125: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
+
+ LUT4_124: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_28);
+
+ LUT4_123: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
+
+ LUT4_122: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_29);
+
+ LUT4_121: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
+
+ LUT4_120: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
+ DO0=>func_and_inet_30);
+
+ LUT4_119: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
+
+ LUT4_118: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>func_and_inet_31);
+
+ LUT4_117: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
+
+ LUT4_116: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_32);
+
+ LUT4_115: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec32_p016);
+
+ LUT4_114: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_33);
+
+ LUT4_113: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec33_r116);
+
+ LUT4_112: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_34);
+
+ LUT4_111: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec34_p017);
+
+ LUT4_110: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_35);
+
+ LUT4_109: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec35_r117);
+
+ LUT4_108: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_36);
+
+ LUT4_107: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec36_p018);
+
+ LUT4_106: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_37);
+
+ LUT4_105: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec37_r118);
+
+ LUT4_104: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_38);
+
+ LUT4_103: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec38_p019);
+
+ LUT4_102: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_39);
+
+ LUT4_101: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec39_r119);
+
+ LUT4_100: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_40);
+
+ LUT4_99: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec40_p020);
+
+ LUT4_98: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_41);
+
+ LUT4_97: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec41_r120);
+
+ LUT4_96: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_42);
+
+ LUT4_95: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec42_p021);
+
+ LUT4_94: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_43);
+
+ LUT4_93: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec43_r121);
+
+ LUT4_92: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_44);
+
+ LUT4_91: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec44_p022);
+
+ LUT4_90: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_45);
+
+ LUT4_89: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec45_r122);
+
+ LUT4_88: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13_inv, DO0=>func_and_inet_46);
+
+ LUT4_87: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec46_p023);
+
+ LUT4_86: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_47);
+
+ LUT4_85: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec47_r123);
+
+ LUT4_84: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_48);
+
+ LUT4_83: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec48_p024);
+
+ LUT4_82: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_49);
+
+ LUT4_81: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec49_r124);
+
+ LUT4_80: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_50);
+
+ LUT4_79: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec50_p025);
+
+ LUT4_78: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_51);
+
+ LUT4_77: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec51_r125);
+
+ LUT4_76: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_52);
+
+ LUT4_75: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec52_p026);
+
+ LUT4_74: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_53);
+
+ LUT4_73: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec53_r126);
+
+ LUT4_72: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv,
+ AD0=>wptr_13, DO0=>func_and_inet_54);
+
+ LUT4_71: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec54_p027);
+
+ LUT4_70: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_55);
+
+ LUT4_69: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec55_r127);
+
+ LUT4_68: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_56);
+
+ LUT4_67: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec56_p028);
+
+ LUT4_66: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_57);
+
+ LUT4_65: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec57_r128);
+
+ LUT4_64: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_58);
+
+ LUT4_63: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec58_p029);
+
+ LUT4_62: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_59);
+
+ LUT4_61: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec59_r129);
+
+ LUT4_60: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12,
+ AD0=>wptr_13, DO0=>func_and_inet_60);
+
+ LUT4_59: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec60_p030);
+
+ LUT4_58: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_61);
+
+ LUT4_57: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec61_r130);
+
+ LUT4_56: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13,
+ DO0=>func_and_inet_62);
+
+ LUT4_55: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec62_p031);
+
+ LUT4_54: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>func_and_inet_63);
+
+ LUT4_53: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec63_r131);
+
+ LUT4_52: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
+ AD1=>w_gcount_r214, AD0=>w_gcount_r215,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_51: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>w_gcount_r211,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_50: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>w_gcount_r27,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_49: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23,
+ DO0=>w_g2b_xor_cluster_3);
+
+ LUT4_48: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r14);
+
+ LUT4_47: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
+ AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13);
+
+ LUT4_46: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
+ AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
+
+ LUT4_45: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
+
+ LUT4_44: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9);
+
+ LUT4_43: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8);
+
+ LUT4_42: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_41: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6);
+
+ LUT4_40: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_39: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_38: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_37: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3);
+
+ LUT4_36: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
+
+ LUT4_35: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
+ DO0=>wcount_r2);
+
+ LUT4_34: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_3_2);
+
+ LUT4_33: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
+ DO0=>wcount_r1);
+
+ LUT4_32: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
+ DO0=>wcount_r0);
+
+ LUT4_31: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
+ AD1=>r_gcount_w215, AD0=>r_gcount_w216,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_30: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
+ AD1=>r_gcount_w211, AD0=>r_gcount_w212,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_29: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>r_gcount_w28,
+ DO0=>r_g2b_xor_cluster_2);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_3);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w15);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
+ AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
+ AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
+ AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
+ AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
+ DO0=>rcount_w10);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>scuba_vlo,
+ DO0=>r_g2b_xor_cluster_2_1);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
+ DO0=>rcount_w3);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo,
+ DO0=>r_g2b_xor_cluster_3_2);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
+ DO0=>rcount_w2);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
+ DO0=>rcount_w1);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
+ AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
+ AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>func_xor_inet_4);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
+ AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
+ DO0=>func_xor_inet_5);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb);
+
+ XOR2_t4: XOR2
+ port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb);
+
+ XOR2_t3: XOR2
+ port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb);
+
+ XOR2_t2: XOR2
+ port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ INV_0: INV
+ port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv);
+
+ AND2_t1: AND2
+ port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig);
+
+ AND2_t0: AND2
+ port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig);
+
+ pdp_ram_0_0_31: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec0_p00,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
+ DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
+ DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
+ DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_1_0_30: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec2_p01,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
+ DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
+ DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
+ DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_2_0_29: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec4_p02,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
+ DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
+ DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
+ DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_3_0_28: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec6_p03,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
+ DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
+ DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
+ DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_4_0_27: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec8_p04,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
+ DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
+ DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
+ DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_5_0_26: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec10_p05,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
+ DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
+ DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
+ DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_6_0_25: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec12_p06,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
+ DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
+ DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
+ DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_7_0_24: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec14_p07,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
+ DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
+ DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
+ DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_8_0_23: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec16_p08,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
+ DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
+ DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
+ DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_9_0_22: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec18_p09,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
+ DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
+ DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
+ DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_10_0_21: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec20_p010,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
+ DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
+ DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
+ DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_11_0_20: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec22_p011,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
+ DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
+ DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
+ DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_12_0_19: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec24_p012,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
+ DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
+ DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
+ DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_13_0_18: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec26_p013,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
+ DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
+ DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
+ DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_14_0_17: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec28_p014,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
+ DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
+ DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
+ DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_15_0_16: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec30_p015,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
+ DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
+ DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
+ DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_16_0_15: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec32_p016,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
+ DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
+ DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
+ DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_17_0_14: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec34_p017,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
+ DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
+ DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
+ DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_18_0_13: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec36_p018,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
+ DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
+ DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
+ DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_19_0_12: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec38_p019,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
+ DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
+ DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
+ DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_20_0_11: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec40_p020,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
+ DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
+ DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
+ DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_21_0_10: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec42_p021,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
+ DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
+ DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
+ DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_22_0_9: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec44_p022,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
+ DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
+ DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
+ DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_23_0_8: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec46_p023,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
+ DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
+ DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
+ DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_24_0_7: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec48_p024,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
+ DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
+ DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
+ DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_25_0_6: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec50_p025,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
+ DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
+ DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
+ DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_26_0_5: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec52_p026,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
+ DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
+ DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
+ DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_27_0_4: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec54_p027,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
+ DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
+ DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
+ DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_28_0_3: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec56_p028,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
+ DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
+ DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
+ DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_29_0_2: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec58_p029,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
+ DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
+ DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
+ DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_30_0_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec60_p030,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
+ DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
+ DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
+ DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_31_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec62_p031,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
+ DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
+ DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
+ DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ FF_239: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_238: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_237: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_236: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_235: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_234: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_233: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_232: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_231: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_230: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_229: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_228: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_227: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_226: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_225: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_224: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_15);
+
+ FF_223: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_222: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_221: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_220: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_219: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_218: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_217: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_216: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_215: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_214: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_213: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_212: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_211: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_210: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_13);
+
+ FF_209: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_14);
+
+ FF_208: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_15);
+
+ FF_207: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_206: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_205: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_204: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_203: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_202: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_201: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_200: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_199: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_198: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_197: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_196: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_195: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_194: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_193: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_14);
+
+ FF_192: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_15);
+
+ FF_191: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_190: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_189: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_188: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_187: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_186: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_185: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_184: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_183: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_182: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_181: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_10);
+
+ FF_180: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_11);
+
+ FF_179: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_12);
+
+ FF_178: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_13);
+
+ FF_177: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_14);
+
+ FF_176: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_15);
+
+ FF_175: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_16);
+
+ FF_174: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_173: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_172: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_171: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_170: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_169: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_168: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_167: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_166: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_165: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_164: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_10);
+
+ FF_163: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_11);
+
+ FF_162: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_12);
+
+ FF_161: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_13);
+
+ FF_160: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_14);
+
+ FF_159: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_15);
+
+ FF_158: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_16);
+
+ FF_157: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_156: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_155: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_154: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_153: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_152: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_151: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_150: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_149: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_148: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_147: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_10);
+
+ FF_146: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_11);
+
+ FF_145: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_12);
+
+ FF_144: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_13);
+
+ FF_143: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_14);
+
+ FF_142: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_15);
+
+ FF_141: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_16);
+
+ FF_140: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_139: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_138: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_13_ff);
+
+ FF_137: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_14_ff);
+
+ FF_136: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_15_ff);
+
+ FF_135: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_134: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_133: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_132: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_131: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_130: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_129: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_128: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_127: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_126: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_125: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_124: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_123: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_122: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r13);
+
+ FF_121: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r14);
+
+ FF_120: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r15);
+
+ FF_119: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_118: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_117: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_116: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_115: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_114: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_113: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_112: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_111: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_110: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_109: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+ FF_108: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+ FF_107: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
+
+ FF_106: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
+
+ FF_105: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
+
+ FF_104: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
+
+ FF_103: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
+
+ FF_102: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_101: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_100: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_99: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_98: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_97: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_96: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_95: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_94: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_93: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_92: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_91: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_90: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_89: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r213);
+
+ FF_88: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r214);
+
+ FF_87: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r215);
+
+ FF_86: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_85: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_84: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_83: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_82: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_81: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_80: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_79: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_78: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_77: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_76: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w210);
+
+ FF_75: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w211);
+
+ FF_74: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w212);
+
+ FF_73: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w213);
+
+ FF_72: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w214);
+
+ FF_71: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w215);
+
+ FF_70: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w216);
+
+ FF_69: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_68: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_67: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_66: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_65: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_64: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_63: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_62: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_60: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_59: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_58: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13));
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14));
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15));
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16));
+
+ FF_3: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ w_gctr_7: CU2
+ port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
+ NC0=>iwcount_14, NC1=>iwcount_15);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_gctr_5: CU2
+ port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
+ NC0=>ircount_10, NC1=>ircount_11);
+
+ r_gctr_6: CU2
+ port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
+ NC0=>ircount_12, NC1=>ircount_13);
+
+ r_gctr_7: CU2
+ port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
+ NC0=>ircount_14, NC1=>ircount_15);
+
+ r_gctr_8: CU2
+ port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8,
+ NC0=>ircount_16, NC1=>open);
+
+ mux_8: MUX321
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
+ D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
+ D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
+ D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
+ D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
+ D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
+ D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
+ D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
+ D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(0));
+
+ mux_7: MUX321
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
+ D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
+ D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
+ D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
+ D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
+ D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
+ D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
+ D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
+ D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(1));
+
+ mux_6: MUX321
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
+ D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
+ D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
+ D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
+ D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
+ D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
+ D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
+ D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
+ D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(2));
+
+ mux_5: MUX321
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
+ D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
+ D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
+ D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
+ D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
+ D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
+ D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
+ D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
+ D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(3));
+
+ mux_4: MUX321
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
+ D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
+ D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
+ D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
+ D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
+ D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
+ D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
+ D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
+ D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(4));
+
+ mux_3: MUX321
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
+ D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
+ D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
+ D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
+ D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
+ D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
+ D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
+ D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
+ D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(5));
+
+ mux_2: MUX321
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
+ D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
+ D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
+ D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
+ D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
+ D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
+ D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
+ D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
+ D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(6));
+
+ mux_1: MUX321
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
+ D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
+ D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
+ D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
+ D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
+ D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
+ D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
+ D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
+ D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(7));
+
+ mux_0: MUX321
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
+ D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
+ D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
+ D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
+ D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
+ D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
+ D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
+ D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
+ D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(8));
+
+ wcnt_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo,
+ B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>wcnt_sub_0);
+
+ wcnt_1: FSUB2B
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2,
+ B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1,
+ S1=>wcnt_sub_2);
+
+ wcnt_2: FSUB2B
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4,
+ B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3,
+ S1=>wcnt_sub_4);
+
+ wcnt_3: FSUB2B
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6,
+ B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5,
+ S1=>wcnt_sub_6);
+
+ wcnt_4: FSUB2B
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8,
+ B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7,
+ S1=>wcnt_sub_8);
+
+ wcnt_5: FSUB2B
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10,
+ B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9,
+ S1=>wcnt_sub_10);
+
+ wcnt_6: FSUB2B
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12,
+ B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2,
+ S0=>wcnt_sub_11, S1=>wcnt_sub_12);
+
+ wcnt_7: FSUB2B
+ port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14,
+ B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13,
+ S1=>wcnt_sub_14);
+
+ wcnt_8: FSUB2B
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15,
+ S1=>open);
+
+ rcnt_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open,
+ S1=>rcnt_sub_0);
+
+ rcnt_1: FSUB2B
+ port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1,
+ B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1,
+ S1=>rcnt_sub_2);
+
+ rcnt_2: FSUB2B
+ port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3,
+ B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3,
+ S1=>rcnt_sub_4);
+
+ rcnt_3: FSUB2B
+ port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5,
+ B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5,
+ S1=>rcnt_sub_6);
+
+ rcnt_4: FSUB2B
+ port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7,
+ B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7,
+ S1=>rcnt_sub_8);
+
+ rcnt_5: FSUB2B
+ port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9,
+ B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9,
+ S1=>rcnt_sub_10);
+
+ rcnt_6: FSUB2B
+ port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11,
+ B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11,
+ S1=>rcnt_sub_12);
+
+ rcnt_7: FSUB2B
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13,
+ B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13,
+ S1=>rcnt_sub_14);
+
+ rcnt_8: FSUB2B
+ port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15,
+ B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15,
+ S1=>rcnt_sub_16);
+
+ rcntd: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open);
+
+ wfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo,
+ B1=>rcount_w1, BI=>scuba_vlo, BOUT=>co0_4, S0=>open,
+ S1=>wfill_sub_0);
+
+ wfill_1: FSUB2B
+ port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3,
+ BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2);
+
+ wfill_2: FSUB2B
+ port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5,
+ BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4);
+
+ wfill_3: FSUB2B
+ port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7,
+ BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6);
+
+ wfill_4: FSUB2B
+ port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9,
+ BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8);
+
+ wfill_5: FSUB2B
+ port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10,
+ B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9,
+ S1=>wfill_sub_10);
+
+ wfill_6: FSUB2B
+ port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12,
+ B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4,
+ S0=>wfill_sub_11, S1=>wfill_sub_12);
+
+ wfill_7: FSUB2B
+ port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14,
+ B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13,
+ S1=>wfill_sub_14);
+
+ wfill_8: FSUB2B
+ port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15,
+ S1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_5, BOUT=>co1_5, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_5, BOUT=>co2_5, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_5, B1=>rptr_6,
+ BI=>co2_5, BOUT=>co3_5, S0=>rfill_sub_5, S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_5, BOUT=>co4_5, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_9, B1=>rptr_10,
+ BI=>co4_5, BOUT=>co5_5, S0=>rfill_sub_9, S1=>rfill_sub_10);
+
+ rfill_6: FSUB2B
+ port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_11,
+ B1=>rptr_12, BI=>co5_5, BOUT=>co6_5, S0=>rfill_sub_11,
+ S1=>rfill_sub_12);
+
+ rfill_7: FSUB2B
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rptr_13,
+ B1=>rptr_14, BI=>co6_5, BOUT=>co7_5, S0=>rfill_sub_13,
+ S1=>rfill_sub_14);
+
+ rfill_8: FSUB2B
+ port map (A0=>wcount_r14, A1=>rfill_sub_msb, B0=>rptr_15,
+ B1=>scuba_vlo, BI=>co7_5, BOUT=>co8_2, S0=>rfill_sub_15,
+ S1=>rfill_sub_16);
+
+ rfilld: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>wcount_r0, CI=>cmp_ci, GE=>co0_6);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
+ B1=>wcount_r2, CI=>co0_6, GE=>co1_6);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
+ B1=>wcount_r4, CI=>co1_6, GE=>co2_6);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
+ B1=>wcount_r6, CI=>co2_6, GE=>co3_6);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
+ B1=>wcount_r8, CI=>co3_6, GE=>co4_6);
+
+ empty_cmp_5: AGEB2
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
+ B1=>wcount_r10, CI=>co4_6, GE=>co5_6);
+
+ empty_cmp_6: AGEB2
+ port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11,
+ B1=>w_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6);
+
+ empty_cmp_7: AGEB2
+ port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13,
+ B1=>wcount_r14, CI=>co6_6, GE=>co7_6);
+
+ empty_cmp_8: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co7_6, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
+ B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_7);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
+ B1=>rcount_w4, CI=>co0_7, GE=>co1_7);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
+ B1=>rcount_w6, CI=>co1_7, GE=>co2_7);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
+ B1=>rcount_w8, CI=>co2_7, GE=>co3_7);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9,
+ B1=>rcount_w10, CI=>co3_7, GE=>co4_7);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11,
+ B1=>rcount_w12, CI=>co4_7, GE=>co5_7);
+
+ full_cmp_6: AGEB2
+ port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w14, CI=>co5_7, GE=>co6_7);
+
+ full_cmp_7: AGEB2
+ port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15,
+ B1=>full_cmp_clr, CI=>co6_7, GE=>full_d_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ ae_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+ ae_cmp_0: AGEB2
+ port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
+ B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_8);
+
+ ae_cmp_1: AGEB2
+ port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
+ B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_8, GE=>co1_8);
+
+ ae_cmp_2: AGEB2
+ port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
+ B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_8, GE=>co2_8);
+
+ ae_cmp_3: AGEB2
+ port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
+ B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_8, GE=>co3_8);
+
+ ae_cmp_4: AGEB2
+ port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
+ B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_8, GE=>co4_8);
+
+ ae_cmp_5: AGEB2
+ port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
+ B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_8, GE=>co5_8);
+
+ ae_cmp_6: AGEB2
+ port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13),
+ B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_8, GE=>co6_8);
+
+ ae_cmp_7: AGEB2
+ port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15),
+ B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_8, GE=>co7_7);
+
+ ae_cmp_8: AGEB2
+ port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
+ B1=>scuba_vlo, CI=>co7_7, GE=>ae_d_c);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
+ af_d_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
+
+ af_d_cmp_0: AGEB2
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_9);
+
+ af_d_cmp_1: AGEB2
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), CI=>co0_9, GE=>co1_9);
+
+ af_d_cmp_2: AGEB2
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), CI=>co1_9, GE=>co2_9);
+
+ af_d_cmp_3: AGEB2
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>AmFullThresh(7), CI=>co2_9, GE=>co3_9);
+
+ af_d_cmp_4: AGEB2
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ B1=>AmFullThresh(9), CI=>co3_9, GE=>co4_9);
+
+ af_d_cmp_5: AGEB2
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ B1=>AmFullThresh(11), CI=>co4_9, GE=>co5_9);
+
+ af_d_cmp_6: AGEB2
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ B1=>AmFullThresh(13), CI=>co5_9, GE=>co6_9);
+
+ af_d_cmp_7: AGEB2
+ port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
+ B1=>scuba_vlo, CI=>co6_9, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a3: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_32kx16x8_mb2 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:MUX321 use entity ecp2m.MUX321(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.4
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
+
+-- Mon Jul 26 21:40:04 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_64kx9 is
+ port (
+ Data: in std_logic_vector(8 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_64kx9;
+
+architecture Structure of fifo_64kx9 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal func_and_inet: std_logic;
+ signal func_and_inet_1: std_logic;
+ signal func_and_inet_2: std_logic;
+ signal func_and_inet_3: std_logic;
+ signal func_and_inet_4: std_logic;
+ signal func_and_inet_5: std_logic;
+ signal func_and_inet_6: std_logic;
+ signal func_and_inet_7: std_logic;
+ signal func_and_inet_8: std_logic;
+ signal func_and_inet_9: std_logic;
+ signal func_and_inet_10: std_logic;
+ signal func_and_inet_11: std_logic;
+ signal func_and_inet_12: std_logic;
+ signal func_and_inet_13: std_logic;
+ signal func_and_inet_14: std_logic;
+ signal func_and_inet_15: std_logic;
+ signal func_and_inet_16: std_logic;
+ signal func_and_inet_17: std_logic;
+ signal func_and_inet_18: std_logic;
+ signal func_and_inet_19: std_logic;
+ signal func_and_inet_20: std_logic;
+ signal func_and_inet_21: std_logic;
+ signal func_and_inet_22: std_logic;
+ signal func_and_inet_23: std_logic;
+ signal func_and_inet_24: std_logic;
+ signal func_and_inet_25: std_logic;
+ signal func_and_inet_26: std_logic;
+ signal func_and_inet_27: std_logic;
+ signal func_and_inet_28: std_logic;
+ signal func_and_inet_29: std_logic;
+ signal wptr_15_inv: std_logic;
+ signal func_and_inet_30: std_logic;
+ signal rptr_15_inv: std_logic;
+ signal func_and_inet_31: std_logic;
+ signal func_and_inet_32: std_logic;
+ signal func_and_inet_33: std_logic;
+ signal func_and_inet_34: std_logic;
+ signal func_and_inet_35: std_logic;
+ signal func_and_inet_36: std_logic;
+ signal func_and_inet_37: std_logic;
+ signal func_and_inet_38: std_logic;
+ signal func_and_inet_39: std_logic;
+ signal func_and_inet_40: std_logic;
+ signal func_and_inet_41: std_logic;
+ signal func_and_inet_42: std_logic;
+ signal func_and_inet_43: std_logic;
+ signal func_and_inet_44: std_logic;
+ signal func_and_inet_45: std_logic;
+ signal wptr_14_inv: std_logic;
+ signal func_and_inet_46: std_logic;
+ signal rptr_14_inv: std_logic;
+ signal func_and_inet_47: std_logic;
+ signal func_and_inet_48: std_logic;
+ signal func_and_inet_49: std_logic;
+ signal func_and_inet_50: std_logic;
+ signal func_and_inet_51: std_logic;
+ signal func_and_inet_52: std_logic;
+ signal func_and_inet_53: std_logic;
+ signal wptr_13_inv: std_logic;
+ signal func_and_inet_54: std_logic;
+ signal rptr_13_inv: std_logic;
+ signal func_and_inet_55: std_logic;
+ signal func_and_inet_56: std_logic;
+ signal func_and_inet_57: std_logic;
+ signal wptr_12_inv: std_logic;
+ signal func_and_inet_58: std_logic;
+ signal rptr_12_inv: std_logic;
+ signal func_and_inet_59: std_logic;
+ signal wptr_11_inv: std_logic;
+ signal func_and_inet_60: std_logic;
+ signal rptr_11_inv: std_logic;
+ signal func_and_inet_61: std_logic;
+ signal func_and_inet_62: std_logic;
+ signal func_and_inet_63: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal w_g2b_xor_cluster_3_1: std_logic;
+ signal w_g2b_xor_cluster_3_2: std_logic;
+ signal w_g2b_xor_cluster_3: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal func_xor_inet_3: std_logic;
+ signal func_xor_inet_2: std_logic;
+ signal func_xor_inet_1: std_logic;
+ signal func_xor_inet: std_logic;
+ signal func_xor_inet_4: std_logic;
+ signal func_xor_inet_5: std_logic;
+ signal r_g2b_xor_cluster_2_1: std_logic;
+ signal r_g2b_xor_cluster_3_1: std_logic;
+ signal r_g2b_xor_cluster_3_2: std_logic;
+ signal r_g2b_xor_cluster_3: std_logic;
+ signal r_g2b_xor_cluster_2: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal func_xor_inet_9: std_logic;
+ signal func_xor_inet_8: std_logic;
+ signal func_xor_inet_7: std_logic;
+ signal func_xor_inet_6: std_logic;
+ signal func_xor_inet_10: std_logic;
+ signal func_xor_inet_11: std_logic;
+ signal dec1_r10: std_logic;
+ signal dec0_p00: std_logic;
+ signal dec3_r11: std_logic;
+ signal dec2_p01: std_logic;
+ signal dec5_r12: std_logic;
+ signal dec4_p02: std_logic;
+ signal dec7_r13: std_logic;
+ signal dec6_p03: std_logic;
+ signal dec9_r14: std_logic;
+ signal dec8_p04: std_logic;
+ signal dec11_r15: std_logic;
+ signal dec10_p05: std_logic;
+ signal dec13_r16: std_logic;
+ signal dec12_p06: std_logic;
+ signal dec15_r17: std_logic;
+ signal dec14_p07: std_logic;
+ signal dec17_r18: std_logic;
+ signal dec16_p08: std_logic;
+ signal dec19_r19: std_logic;
+ signal dec18_p09: std_logic;
+ signal dec21_r110: std_logic;
+ signal dec20_p010: std_logic;
+ signal dec23_r111: std_logic;
+ signal dec22_p011: std_logic;
+ signal dec25_r112: std_logic;
+ signal dec24_p012: std_logic;
+ signal dec27_r113: std_logic;
+ signal dec26_p013: std_logic;
+ signal dec29_r114: std_logic;
+ signal dec28_p014: std_logic;
+ signal dec31_r115: std_logic;
+ signal dec30_p015: std_logic;
+ signal dec33_r116: std_logic;
+ signal dec32_p016: std_logic;
+ signal dec35_r117: std_logic;
+ signal dec34_p017: std_logic;
+ signal dec37_r118: std_logic;
+ signal dec36_p018: std_logic;
+ signal dec39_r119: std_logic;
+ signal dec38_p019: std_logic;
+ signal dec41_r120: std_logic;
+ signal dec40_p020: std_logic;
+ signal dec43_r121: std_logic;
+ signal dec42_p021: std_logic;
+ signal dec45_r122: std_logic;
+ signal dec44_p022: std_logic;
+ signal dec47_r123: std_logic;
+ signal dec46_p023: std_logic;
+ signal dec49_r124: std_logic;
+ signal dec48_p024: std_logic;
+ signal dec51_r125: std_logic;
+ signal dec50_p025: std_logic;
+ signal dec53_r126: std_logic;
+ signal dec52_p026: std_logic;
+ signal dec55_r127: std_logic;
+ signal dec54_p027: std_logic;
+ signal dec57_r128: std_logic;
+ signal dec56_p028: std_logic;
+ signal dec59_r129: std_logic;
+ signal dec58_p029: std_logic;
+ signal dec61_r130: std_logic;
+ signal dec60_p030: std_logic;
+ signal dec63_r131: std_logic;
+ signal dec62_p031: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal w_gdata_12: std_logic;
+ signal w_gdata_13: std_logic;
+ signal w_gdata_14: std_logic;
+ signal w_gdata_15: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal wptr_14: std_logic;
+ signal wptr_15: std_logic;
+ signal wptr_16: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal r_gdata_9: std_logic;
+ signal r_gdata_10: std_logic;
+ signal r_gdata_11: std_logic;
+ signal r_gdata_12: std_logic;
+ signal r_gdata_13: std_logic;
+ signal r_gdata_14: std_logic;
+ signal r_gdata_15: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_16: std_logic;
+ signal rptr_11: std_logic;
+ signal rptr_12: std_logic;
+ signal rptr_13: std_logic;
+ signal rptr_14: std_logic;
+ signal rptr_15: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal w_gcount_13: std_logic;
+ signal w_gcount_14: std_logic;
+ signal w_gcount_15: std_logic;
+ signal w_gcount_16: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal r_gcount_10: std_logic;
+ signal r_gcount_11: std_logic;
+ signal r_gcount_12: std_logic;
+ signal r_gcount_13: std_logic;
+ signal r_gcount_14: std_logic;
+ signal r_gcount_15: std_logic;
+ signal r_gcount_16: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal w_gcount_r213: std_logic;
+ signal w_gcount_r13: std_logic;
+ signal w_gcount_r214: std_logic;
+ signal w_gcount_r14: std_logic;
+ signal w_gcount_r215: std_logic;
+ signal w_gcount_r15: std_logic;
+ signal w_gcount_r216: std_logic;
+ signal w_gcount_r16: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal r_gcount_w210: std_logic;
+ signal r_gcount_w10: std_logic;
+ signal r_gcount_w211: std_logic;
+ signal r_gcount_w11: std_logic;
+ signal r_gcount_w212: std_logic;
+ signal r_gcount_w12: std_logic;
+ signal r_gcount_w213: std_logic;
+ signal r_gcount_w13: std_logic;
+ signal r_gcount_w214: std_logic;
+ signal r_gcount_w14: std_logic;
+ signal r_gcount_w215: std_logic;
+ signal r_gcount_w15: std_logic;
+ signal r_gcount_w216: std_logic;
+ signal r_gcount_w16: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5: std_logic;
+ signal iwcount_14: std_logic;
+ signal iwcount_15: std_logic;
+ signal co6: std_logic;
+ signal iwcount_16: std_logic;
+ signal co8: std_logic;
+ signal wcount_16: std_logic;
+ signal co7: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_1: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_1: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co5_1: std_logic;
+ signal ircount_14: std_logic;
+ signal ircount_15: std_logic;
+ signal co6_1: std_logic;
+ signal ircount_16: std_logic;
+ signal co8_1: std_logic;
+ signal rcount_16: std_logic;
+ signal co7_1: std_logic;
+ signal mdout1_31_0: std_logic;
+ signal mdout1_30_0: std_logic;
+ signal mdout1_29_0: std_logic;
+ signal mdout1_28_0: std_logic;
+ signal mdout1_27_0: std_logic;
+ signal mdout1_26_0: std_logic;
+ signal mdout1_25_0: std_logic;
+ signal mdout1_24_0: std_logic;
+ signal mdout1_23_0: std_logic;
+ signal mdout1_22_0: std_logic;
+ signal mdout1_21_0: std_logic;
+ signal mdout1_20_0: std_logic;
+ signal mdout1_19_0: std_logic;
+ signal mdout1_18_0: std_logic;
+ signal mdout1_17_0: std_logic;
+ signal mdout1_16_0: std_logic;
+ signal mdout1_15_0: std_logic;
+ signal mdout1_14_0: std_logic;
+ signal mdout1_13_0: std_logic;
+ signal mdout1_12_0: std_logic;
+ signal mdout1_11_0: std_logic;
+ signal mdout1_10_0: std_logic;
+ signal mdout1_9_0: std_logic;
+ signal mdout1_8_0: std_logic;
+ signal mdout1_7_0: std_logic;
+ signal mdout1_6_0: std_logic;
+ signal mdout1_5_0: std_logic;
+ signal mdout1_4_0: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_31_1: std_logic;
+ signal mdout1_30_1: std_logic;
+ signal mdout1_29_1: std_logic;
+ signal mdout1_28_1: std_logic;
+ signal mdout1_27_1: std_logic;
+ signal mdout1_26_1: std_logic;
+ signal mdout1_25_1: std_logic;
+ signal mdout1_24_1: std_logic;
+ signal mdout1_23_1: std_logic;
+ signal mdout1_22_1: std_logic;
+ signal mdout1_21_1: std_logic;
+ signal mdout1_20_1: std_logic;
+ signal mdout1_19_1: std_logic;
+ signal mdout1_18_1: std_logic;
+ signal mdout1_17_1: std_logic;
+ signal mdout1_16_1: std_logic;
+ signal mdout1_15_1: std_logic;
+ signal mdout1_14_1: std_logic;
+ signal mdout1_13_1: std_logic;
+ signal mdout1_12_1: std_logic;
+ signal mdout1_11_1: std_logic;
+ signal mdout1_10_1: std_logic;
+ signal mdout1_9_1: std_logic;
+ signal mdout1_8_1: std_logic;
+ signal mdout1_7_1: std_logic;
+ signal mdout1_6_1: std_logic;
+ signal mdout1_5_1: std_logic;
+ signal mdout1_4_1: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_31_2: std_logic;
+ signal mdout1_30_2: std_logic;
+ signal mdout1_29_2: std_logic;
+ signal mdout1_28_2: std_logic;
+ signal mdout1_27_2: std_logic;
+ signal mdout1_26_2: std_logic;
+ signal mdout1_25_2: std_logic;
+ signal mdout1_24_2: std_logic;
+ signal mdout1_23_2: std_logic;
+ signal mdout1_22_2: std_logic;
+ signal mdout1_21_2: std_logic;
+ signal mdout1_20_2: std_logic;
+ signal mdout1_19_2: std_logic;
+ signal mdout1_18_2: std_logic;
+ signal mdout1_17_2: std_logic;
+ signal mdout1_16_2: std_logic;
+ signal mdout1_15_2: std_logic;
+ signal mdout1_14_2: std_logic;
+ signal mdout1_13_2: std_logic;
+ signal mdout1_12_2: std_logic;
+ signal mdout1_11_2: std_logic;
+ signal mdout1_10_2: std_logic;
+ signal mdout1_9_2: std_logic;
+ signal mdout1_8_2: std_logic;
+ signal mdout1_7_2: std_logic;
+ signal mdout1_6_2: std_logic;
+ signal mdout1_5_2: std_logic;
+ signal mdout1_4_2: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_31_3: std_logic;
+ signal mdout1_30_3: std_logic;
+ signal mdout1_29_3: std_logic;
+ signal mdout1_28_3: std_logic;
+ signal mdout1_27_3: std_logic;
+ signal mdout1_26_3: std_logic;
+ signal mdout1_25_3: std_logic;
+ signal mdout1_24_3: std_logic;
+ signal mdout1_23_3: std_logic;
+ signal mdout1_22_3: std_logic;
+ signal mdout1_21_3: std_logic;
+ signal mdout1_20_3: std_logic;
+ signal mdout1_19_3: std_logic;
+ signal mdout1_18_3: std_logic;
+ signal mdout1_17_3: std_logic;
+ signal mdout1_16_3: std_logic;
+ signal mdout1_15_3: std_logic;
+ signal mdout1_14_3: std_logic;
+ signal mdout1_13_3: std_logic;
+ signal mdout1_12_3: std_logic;
+ signal mdout1_11_3: std_logic;
+ signal mdout1_10_3: std_logic;
+ signal mdout1_9_3: std_logic;
+ signal mdout1_8_3: std_logic;
+ signal mdout1_7_3: std_logic;
+ signal mdout1_6_3: std_logic;
+ signal mdout1_5_3: std_logic;
+ signal mdout1_4_3: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_31_4: std_logic;
+ signal mdout1_30_4: std_logic;
+ signal mdout1_29_4: std_logic;
+ signal mdout1_28_4: std_logic;
+ signal mdout1_27_4: std_logic;
+ signal mdout1_26_4: std_logic;
+ signal mdout1_25_4: std_logic;
+ signal mdout1_24_4: std_logic;
+ signal mdout1_23_4: std_logic;
+ signal mdout1_22_4: std_logic;
+ signal mdout1_21_4: std_logic;
+ signal mdout1_20_4: std_logic;
+ signal mdout1_19_4: std_logic;
+ signal mdout1_18_4: std_logic;
+ signal mdout1_17_4: std_logic;
+ signal mdout1_16_4: std_logic;
+ signal mdout1_15_4: std_logic;
+ signal mdout1_14_4: std_logic;
+ signal mdout1_13_4: std_logic;
+ signal mdout1_12_4: std_logic;
+ signal mdout1_11_4: std_logic;
+ signal mdout1_10_4: std_logic;
+ signal mdout1_9_4: std_logic;
+ signal mdout1_8_4: std_logic;
+ signal mdout1_7_4: std_logic;
+ signal mdout1_6_4: std_logic;
+ signal mdout1_5_4: std_logic;
+ signal mdout1_4_4: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_31_5: std_logic;
+ signal mdout1_30_5: std_logic;
+ signal mdout1_29_5: std_logic;
+ signal mdout1_28_5: std_logic;
+ signal mdout1_27_5: std_logic;
+ signal mdout1_26_5: std_logic;
+ signal mdout1_25_5: std_logic;
+ signal mdout1_24_5: std_logic;
+ signal mdout1_23_5: std_logic;
+ signal mdout1_22_5: std_logic;
+ signal mdout1_21_5: std_logic;
+ signal mdout1_20_5: std_logic;
+ signal mdout1_19_5: std_logic;
+ signal mdout1_18_5: std_logic;
+ signal mdout1_17_5: std_logic;
+ signal mdout1_16_5: std_logic;
+ signal mdout1_15_5: std_logic;
+ signal mdout1_14_5: std_logic;
+ signal mdout1_13_5: std_logic;
+ signal mdout1_12_5: std_logic;
+ signal mdout1_11_5: std_logic;
+ signal mdout1_10_5: std_logic;
+ signal mdout1_9_5: std_logic;
+ signal mdout1_8_5: std_logic;
+ signal mdout1_7_5: std_logic;
+ signal mdout1_6_5: std_logic;
+ signal mdout1_5_5: std_logic;
+ signal mdout1_4_5: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_31_6: std_logic;
+ signal mdout1_30_6: std_logic;
+ signal mdout1_29_6: std_logic;
+ signal mdout1_28_6: std_logic;
+ signal mdout1_27_6: std_logic;
+ signal mdout1_26_6: std_logic;
+ signal mdout1_25_6: std_logic;
+ signal mdout1_24_6: std_logic;
+ signal mdout1_23_6: std_logic;
+ signal mdout1_22_6: std_logic;
+ signal mdout1_21_6: std_logic;
+ signal mdout1_20_6: std_logic;
+ signal mdout1_19_6: std_logic;
+ signal mdout1_18_6: std_logic;
+ signal mdout1_17_6: std_logic;
+ signal mdout1_16_6: std_logic;
+ signal mdout1_15_6: std_logic;
+ signal mdout1_14_6: std_logic;
+ signal mdout1_13_6: std_logic;
+ signal mdout1_12_6: std_logic;
+ signal mdout1_11_6: std_logic;
+ signal mdout1_10_6: std_logic;
+ signal mdout1_9_6: std_logic;
+ signal mdout1_8_6: std_logic;
+ signal mdout1_7_6: std_logic;
+ signal mdout1_6_6: std_logic;
+ signal mdout1_5_6: std_logic;
+ signal mdout1_4_6: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_31_7: std_logic;
+ signal mdout1_30_7: std_logic;
+ signal mdout1_29_7: std_logic;
+ signal mdout1_28_7: std_logic;
+ signal mdout1_27_7: std_logic;
+ signal mdout1_26_7: std_logic;
+ signal mdout1_25_7: std_logic;
+ signal mdout1_24_7: std_logic;
+ signal mdout1_23_7: std_logic;
+ signal mdout1_22_7: std_logic;
+ signal mdout1_21_7: std_logic;
+ signal mdout1_20_7: std_logic;
+ signal mdout1_19_7: std_logic;
+ signal mdout1_18_7: std_logic;
+ signal mdout1_17_7: std_logic;
+ signal mdout1_16_7: std_logic;
+ signal mdout1_15_7: std_logic;
+ signal mdout1_14_7: std_logic;
+ signal mdout1_13_7: std_logic;
+ signal mdout1_12_7: std_logic;
+ signal mdout1_11_7: std_logic;
+ signal mdout1_10_7: std_logic;
+ signal mdout1_9_7: std_logic;
+ signal mdout1_8_7: std_logic;
+ signal mdout1_7_7: std_logic;
+ signal mdout1_6_7: std_logic;
+ signal mdout1_5_7: std_logic;
+ signal mdout1_4_7: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal rptr_15_ff: std_logic;
+ signal rptr_14_ff: std_logic;
+ signal rptr_13_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal mdout1_31_8: std_logic;
+ signal mdout1_30_8: std_logic;
+ signal mdout1_29_8: std_logic;
+ signal mdout1_28_8: std_logic;
+ signal mdout1_27_8: std_logic;
+ signal mdout1_26_8: std_logic;
+ signal mdout1_25_8: std_logic;
+ signal mdout1_24_8: std_logic;
+ signal mdout1_23_8: std_logic;
+ signal mdout1_22_8: std_logic;
+ signal mdout1_21_8: std_logic;
+ signal mdout1_20_8: std_logic;
+ signal mdout1_19_8: std_logic;
+ signal mdout1_18_8: std_logic;
+ signal mdout1_17_8: std_logic;
+ signal mdout1_16_8: std_logic;
+ signal mdout1_15_8: std_logic;
+ signal mdout1_14_8: std_logic;
+ signal mdout1_13_8: std_logic;
+ signal mdout1_12_8: std_logic;
+ signal mdout1_11_8: std_logic;
+ signal mdout1_10_8: std_logic;
+ signal mdout1_9_8: std_logic;
+ signal mdout1_8_8: std_logic;
+ signal mdout1_7_8: std_logic;
+ signal mdout1_6_8: std_logic;
+ signal mdout1_5_8: std_logic;
+ signal mdout1_4_8: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wcount_r8: std_logic;
+ signal wcount_r9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wcount_r10: std_logic;
+ signal wcount_r11: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal wcount_r12: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal co6_2: std_logic;
+ signal wcount_r14: std_logic;
+ signal wcount_r15: std_logic;
+ signal rcount_14: std_logic;
+ signal rcount_15: std_logic;
+ signal co7_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal rcount_w6: std_logic;
+ signal rcount_w7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal rcount_w8: std_logic;
+ signal rcount_w9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal rcount_w10: std_logic;
+ signal rcount_w11: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_3: std_logic;
+ signal rcount_w12: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal co6_3: std_logic;
+ signal rcount_w14: std_logic;
+ signal rcount_w15: std_logic;
+ signal wcount_14: std_logic;
+ signal wcount_15: std_logic;
+ signal co7_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component MUX321
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; D8: in std_logic;
+ D9: in std_logic; D10: in std_logic; D11: in std_logic;
+ D12: in std_logic; D13: in std_logic; D14: in std_logic;
+ D15: in std_logic; D16: in std_logic; D17: in std_logic;
+ D18: in std_logic; D19: in std_logic; D20: in std_logic;
+ D21: in std_logic; D22: in std_logic; D23: in std_logic;
+ D24: in std_logic; D25: in std_logic; D26: in std_logic;
+ D27: in std_logic; D28: in std_logic; D29: in std_logic;
+ D30: in std_logic; D31: in std_logic; SD1: in std_logic;
+ SD2: in std_logic; SD3: in std_logic; SD4: in std_logic;
+ SD5: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_187 : label is "0x8000";
+ attribute initval of LUT4_186 : label is "0x8000";
+ attribute initval of LUT4_185 : label is "0x8000";
+ attribute initval of LUT4_184 : label is "0x8000";
+ attribute initval of LUT4_183 : label is "0x8000";
+ attribute initval of LUT4_182 : label is "0x8000";
+ attribute initval of LUT4_181 : label is "0x8000";
+ attribute initval of LUT4_180 : label is "0x8000";
+ attribute initval of LUT4_179 : label is "0x8000";
+ attribute initval of LUT4_178 : label is "0x8000";
+ attribute initval of LUT4_177 : label is "0x8000";
+ attribute initval of LUT4_176 : label is "0x8000";
+ attribute initval of LUT4_175 : label is "0x8000";
+ attribute initval of LUT4_174 : label is "0x8000";
+ attribute initval of LUT4_173 : label is "0x8000";
+ attribute initval of LUT4_172 : label is "0x8000";
+ attribute initval of LUT4_171 : label is "0x8000";
+ attribute initval of LUT4_170 : label is "0x8000";
+ attribute initval of LUT4_169 : label is "0x8000";
+ attribute initval of LUT4_168 : label is "0x8000";
+ attribute initval of LUT4_167 : label is "0x8000";
+ attribute initval of LUT4_166 : label is "0x8000";
+ attribute initval of LUT4_165 : label is "0x8000";
+ attribute initval of LUT4_164 : label is "0x8000";
+ attribute initval of LUT4_163 : label is "0x8000";
+ attribute initval of LUT4_162 : label is "0x8000";
+ attribute initval of LUT4_161 : label is "0x8000";
+ attribute initval of LUT4_160 : label is "0x8000";
+ attribute initval of LUT4_159 : label is "0x8000";
+ attribute initval of LUT4_158 : label is "0x8000";
+ attribute initval of LUT4_157 : label is "0x8000";
+ attribute initval of LUT4_156 : label is "0x8000";
+ attribute initval of LUT4_155 : label is "0x8000";
+ attribute initval of LUT4_154 : label is "0x8000";
+ attribute initval of LUT4_153 : label is "0x8000";
+ attribute initval of LUT4_152 : label is "0x8000";
+ attribute initval of LUT4_151 : label is "0x8000";
+ attribute initval of LUT4_150 : label is "0x8000";
+ attribute initval of LUT4_149 : label is "0x8000";
+ attribute initval of LUT4_148 : label is "0x8000";
+ attribute initval of LUT4_147 : label is "0x8000";
+ attribute initval of LUT4_146 : label is "0x8000";
+ attribute initval of LUT4_145 : label is "0x8000";
+ attribute initval of LUT4_144 : label is "0x8000";
+ attribute initval of LUT4_143 : label is "0x8000";
+ attribute initval of LUT4_142 : label is "0x8000";
+ attribute initval of LUT4_141 : label is "0x8000";
+ attribute initval of LUT4_140 : label is "0x8000";
+ attribute initval of LUT4_139 : label is "0x8000";
+ attribute initval of LUT4_138 : label is "0x8000";
+ attribute initval of LUT4_137 : label is "0x8000";
+ attribute initval of LUT4_136 : label is "0x8000";
+ attribute initval of LUT4_135 : label is "0x8000";
+ attribute initval of LUT4_134 : label is "0x8000";
+ attribute initval of LUT4_133 : label is "0x8000";
+ attribute initval of LUT4_132 : label is "0x8000";
+ attribute initval of LUT4_131 : label is "0x8000";
+ attribute initval of LUT4_130 : label is "0x8000";
+ attribute initval of LUT4_129 : label is "0x8000";
+ attribute initval of LUT4_128 : label is "0x8000";
+ attribute initval of LUT4_127 : label is "0x8000";
+ attribute initval of LUT4_126 : label is "0x8000";
+ attribute initval of LUT4_125 : label is "0x8000";
+ attribute initval of LUT4_124 : label is "0x8000";
+ attribute initval of LUT4_123 : label is "0x8000";
+ attribute initval of LUT4_122 : label is "0x8000";
+ attribute initval of LUT4_121 : label is "0x8000";
+ attribute initval of LUT4_120 : label is "0x8000";
+ attribute initval of LUT4_119 : label is "0x8000";
+ attribute initval of LUT4_118 : label is "0x8000";
+ attribute initval of LUT4_117 : label is "0x8000";
+ attribute initval of LUT4_116 : label is "0x8000";
+ attribute initval of LUT4_115 : label is "0x8000";
+ attribute initval of LUT4_114 : label is "0x8000";
+ attribute initval of LUT4_113 : label is "0x8000";
+ attribute initval of LUT4_112 : label is "0x8000";
+ attribute initval of LUT4_111 : label is "0x8000";
+ attribute initval of LUT4_110 : label is "0x8000";
+ attribute initval of LUT4_109 : label is "0x8000";
+ attribute initval of LUT4_108 : label is "0x8000";
+ attribute initval of LUT4_107 : label is "0x8000";
+ attribute initval of LUT4_106 : label is "0x8000";
+ attribute initval of LUT4_105 : label is "0x8000";
+ attribute initval of LUT4_104 : label is "0x8000";
+ attribute initval of LUT4_103 : label is "0x8000";
+ attribute initval of LUT4_102 : label is "0x8000";
+ attribute initval of LUT4_101 : label is "0x8000";
+ attribute initval of LUT4_100 : label is "0x8000";
+ attribute initval of LUT4_99 : label is "0x8000";
+ attribute initval of LUT4_98 : label is "0x8000";
+ attribute initval of LUT4_97 : label is "0x8000";
+ attribute initval of LUT4_96 : label is "0x8000";
+ attribute initval of LUT4_95 : label is "0x8000";
+ attribute initval of LUT4_94 : label is "0x8000";
+ attribute initval of LUT4_93 : label is "0x8000";
+ attribute initval of LUT4_92 : label is "0x8000";
+ attribute initval of LUT4_91 : label is "0x8000";
+ attribute initval of LUT4_90 : label is "0x8000";
+ attribute initval of LUT4_89 : label is "0x8000";
+ attribute initval of LUT4_88 : label is "0x8000";
+ attribute initval of LUT4_87 : label is "0x8000";
+ attribute initval of LUT4_86 : label is "0x8000";
+ attribute initval of LUT4_85 : label is "0x8000";
+ attribute initval of LUT4_84 : label is "0x8000";
+ attribute initval of LUT4_83 : label is "0x8000";
+ attribute initval of LUT4_82 : label is "0x8000";
+ attribute initval of LUT4_81 : label is "0x8000";
+ attribute initval of LUT4_80 : label is "0x8000";
+ attribute initval of LUT4_79 : label is "0x8000";
+ attribute initval of LUT4_78 : label is "0x8000";
+ attribute initval of LUT4_77 : label is "0x8000";
+ attribute initval of LUT4_76 : label is "0x8000";
+ attribute initval of LUT4_75 : label is "0x8000";
+ attribute initval of LUT4_74 : label is "0x8000";
+ attribute initval of LUT4_73 : label is "0x8000";
+ attribute initval of LUT4_72 : label is "0x8000";
+ attribute initval of LUT4_71 : label is "0x8000";
+ attribute initval of LUT4_70 : label is "0x8000";
+ attribute initval of LUT4_69 : label is "0x8000";
+ attribute initval of LUT4_68 : label is "0x8000";
+ attribute initval of LUT4_67 : label is "0x8000";
+ attribute initval of LUT4_66 : label is "0x8000";
+ attribute initval of LUT4_65 : label is "0x8000";
+ attribute initval of LUT4_64 : label is "0x8000";
+ attribute initval of LUT4_63 : label is "0x8000";
+ attribute initval of LUT4_62 : label is "0x8000";
+ attribute initval of LUT4_61 : label is "0x8000";
+ attribute initval of LUT4_60 : label is "0x8000";
+ attribute initval of LUT4_59 : label is "0x6996";
+ attribute initval of LUT4_58 : label is "0x6996";
+ attribute initval of LUT4_57 : label is "0x6996";
+ attribute initval of LUT4_56 : label is "0x6996";
+ attribute initval of LUT4_55 : label is "0x6996";
+ attribute initval of LUT4_54 : label is "0x6996";
+ attribute initval of LUT4_53 : label is "0x6996";
+ attribute initval of LUT4_52 : label is "0x6996";
+ attribute initval of LUT4_51 : label is "0x6996";
+ attribute initval of LUT4_50 : label is "0x6996";
+ attribute initval of LUT4_49 : label is "0x6996";
+ attribute initval of LUT4_48 : label is "0x6996";
+ attribute initval of LUT4_47 : label is "0x6996";
+ attribute initval of LUT4_46 : label is "0x6996";
+ attribute initval of LUT4_45 : label is "0x6996";
+ attribute initval of LUT4_44 : label is "0x6996";
+ attribute initval of LUT4_43 : label is "0x6996";
+ attribute initval of LUT4_42 : label is "0x6996";
+ attribute initval of LUT4_41 : label is "0x6996";
+ attribute initval of LUT4_40 : label is "0x6996";
+ attribute initval of LUT4_39 : label is "0x6996";
+ attribute initval of LUT4_38 : label is "0x6996";
+ attribute initval of LUT4_37 : label is "0x6996";
+ attribute initval of LUT4_36 : label is "0x6996";
+ attribute initval of LUT4_35 : label is "0x6996";
+ attribute initval of LUT4_34 : label is "0x6996";
+ attribute initval of LUT4_33 : label is "0x6996";
+ attribute initval of LUT4_32 : label is "0x6996";
+ attribute initval of LUT4_31 : label is "0x6996";
+ attribute initval of LUT4_30 : label is "0x6996";
+ attribute initval of LUT4_29 : label is "0x6996";
+ attribute initval of LUT4_28 : label is "0x6996";
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_0_30 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_0_29 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_0_28 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is "";
+ attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL";
+ attribute GSR of pdp_ram_4_0_27 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is "";
+ attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL";
+ attribute GSR of pdp_ram_5_0_26 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is "";
+ attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL";
+ attribute GSR of pdp_ram_6_0_25 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_6_0_25 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_6_0_25 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is "";
+ attribute CSDECODE_B of pdp_ram_7_0_24 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_7_0_24 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_7_0_24 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_7_0_24 : label is "NORMAL";
+ attribute GSR of pdp_ram_7_0_24 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_0_24 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_7_0_24 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_7_0_24 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_7_0_24 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_7_0_24 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is "";
+ attribute CSDECODE_B of pdp_ram_8_0_23 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_8_0_23 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_8_0_23 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_8_0_23 : label is "NORMAL";
+ attribute GSR of pdp_ram_8_0_23 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_0_23 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_8_0_23 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_8_0_23 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_8_0_23 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_8_0_23 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is "";
+ attribute CSDECODE_B of pdp_ram_9_0_22 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_9_0_22 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_9_0_22 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_9_0_22 : label is "NORMAL";
+ attribute GSR of pdp_ram_9_0_22 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_0_22 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_9_0_22 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_9_0_22 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_9_0_22 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_9_0_22 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is "";
+ attribute CSDECODE_B of pdp_ram_10_0_21 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_10_0_21 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_10_0_21 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_10_0_21 : label is "NORMAL";
+ attribute GSR of pdp_ram_10_0_21 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_0_21 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_10_0_21 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_10_0_21 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_10_0_21 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_10_0_21 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is "";
+ attribute CSDECODE_B of pdp_ram_11_0_20 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_11_0_20 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_11_0_20 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_11_0_20 : label is "NORMAL";
+ attribute GSR of pdp_ram_11_0_20 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_0_20 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_11_0_20 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_11_0_20 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_11_0_20 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_11_0_20 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is "";
+ attribute CSDECODE_B of pdp_ram_12_0_19 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_12_0_19 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_12_0_19 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_12_0_19 : label is "NORMAL";
+ attribute GSR of pdp_ram_12_0_19 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_0_19 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_12_0_19 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_12_0_19 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_12_0_19 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_12_0_19 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is "";
+ attribute CSDECODE_B of pdp_ram_13_0_18 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_13_0_18 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_13_0_18 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_13_0_18 : label is "NORMAL";
+ attribute GSR of pdp_ram_13_0_18 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_0_18 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_13_0_18 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_13_0_18 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_13_0_18 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_13_0_18 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is "";
+ attribute CSDECODE_B of pdp_ram_14_0_17 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_14_0_17 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_14_0_17 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_14_0_17 : label is "NORMAL";
+ attribute GSR of pdp_ram_14_0_17 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_0_17 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_14_0_17 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_14_0_17 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_14_0_17 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_14_0_17 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is "";
+ attribute CSDECODE_B of pdp_ram_15_0_16 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_15_0_16 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_15_0_16 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_15_0_16 : label is "NORMAL";
+ attribute GSR of pdp_ram_15_0_16 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_0_16 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_15_0_16 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_15_0_16 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_15_0_16 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_15_0_16 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is "";
+ attribute CSDECODE_B of pdp_ram_16_0_15 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_16_0_15 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_16_0_15 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_16_0_15 : label is "NORMAL";
+ attribute GSR of pdp_ram_16_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_16_0_15 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_16_0_15 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_16_0_15 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_16_0_15 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_16_0_15 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is "";
+ attribute CSDECODE_B of pdp_ram_17_0_14 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_17_0_14 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_17_0_14 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_17_0_14 : label is "NORMAL";
+ attribute GSR of pdp_ram_17_0_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_17_0_14 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_17_0_14 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_17_0_14 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_17_0_14 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_17_0_14 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is "";
+ attribute CSDECODE_B of pdp_ram_18_0_13 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_18_0_13 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_18_0_13 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_18_0_13 : label is "NORMAL";
+ attribute GSR of pdp_ram_18_0_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_18_0_13 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_18_0_13 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_18_0_13 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_18_0_13 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_18_0_13 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is "";
+ attribute CSDECODE_B of pdp_ram_19_0_12 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_19_0_12 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_19_0_12 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_19_0_12 : label is "NORMAL";
+ attribute GSR of pdp_ram_19_0_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_19_0_12 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_19_0_12 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_19_0_12 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_19_0_12 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_19_0_12 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is "";
+ attribute CSDECODE_B of pdp_ram_20_0_11 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_20_0_11 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_20_0_11 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_20_0_11 : label is "NORMAL";
+ attribute GSR of pdp_ram_20_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_20_0_11 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_20_0_11 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_20_0_11 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_20_0_11 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_20_0_11 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is "";
+ attribute CSDECODE_B of pdp_ram_21_0_10 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_21_0_10 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_21_0_10 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_21_0_10 : label is "NORMAL";
+ attribute GSR of pdp_ram_21_0_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_21_0_10 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_21_0_10 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_21_0_10 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_21_0_10 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_21_0_10 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is "";
+ attribute CSDECODE_B of pdp_ram_22_0_9 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_22_0_9 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_22_0_9 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_22_0_9 : label is "NORMAL";
+ attribute GSR of pdp_ram_22_0_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_22_0_9 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_22_0_9 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_22_0_9 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_22_0_9 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_22_0_9 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is "";
+ attribute CSDECODE_B of pdp_ram_23_0_8 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_23_0_8 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_23_0_8 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_23_0_8 : label is "NORMAL";
+ attribute GSR of pdp_ram_23_0_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_23_0_8 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_23_0_8 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_23_0_8 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_23_0_8 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_23_0_8 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is "";
+ attribute CSDECODE_B of pdp_ram_24_0_7 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_24_0_7 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_24_0_7 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_24_0_7 : label is "NORMAL";
+ attribute GSR of pdp_ram_24_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_24_0_7 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_24_0_7 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_24_0_7 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_24_0_7 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_24_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is "";
+ attribute CSDECODE_B of pdp_ram_25_0_6 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_25_0_6 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_25_0_6 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_25_0_6 : label is "NORMAL";
+ attribute GSR of pdp_ram_25_0_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_25_0_6 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_25_0_6 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_25_0_6 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_25_0_6 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_25_0_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is "";
+ attribute CSDECODE_B of pdp_ram_26_0_5 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_26_0_5 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_26_0_5 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_26_0_5 : label is "NORMAL";
+ attribute GSR of pdp_ram_26_0_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is "";
+ attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL";
+ attribute GSR of pdp_ram_27_0_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is "";
+ attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL";
+ attribute GSR of pdp_ram_28_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is "";
+ attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL";
+ attribute GSR of pdp_ram_29_0_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is "";
+ attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL";
+ attribute GSR of pdp_ram_30_0_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_31_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "9";
+ attribute GSR of FF_176 : label is "ENABLED";
+ attribute GSR of FF_175 : label is "ENABLED";
+ attribute GSR of FF_174 : label is "ENABLED";
+ attribute GSR of FF_173 : label is "ENABLED";
+ attribute GSR of FF_172 : label is "ENABLED";
+ attribute GSR of FF_171 : label is "ENABLED";
+ attribute GSR of FF_170 : label is "ENABLED";
+ attribute GSR of FF_169 : label is "ENABLED";
+ attribute GSR of FF_168 : label is "ENABLED";
+ attribute GSR of FF_167 : label is "ENABLED";
+ attribute GSR of FF_166 : label is "ENABLED";
+ attribute GSR of FF_165 : label is "ENABLED";
+ attribute GSR of FF_164 : label is "ENABLED";
+ attribute GSR of FF_163 : label is "ENABLED";
+ attribute GSR of FF_162 : label is "ENABLED";
+ attribute GSR of FF_161 : label is "ENABLED";
+ attribute GSR of FF_160 : label is "ENABLED";
+ attribute GSR of FF_159 : label is "ENABLED";
+ attribute GSR of FF_158 : label is "ENABLED";
+ attribute GSR of FF_157 : label is "ENABLED";
+ attribute GSR of FF_156 : label is "ENABLED";
+ attribute GSR of FF_155 : label is "ENABLED";
+ attribute GSR of FF_154 : label is "ENABLED";
+ attribute GSR of FF_153 : label is "ENABLED";
+ attribute GSR of FF_152 : label is "ENABLED";
+ attribute GSR of FF_151 : label is "ENABLED";
+ attribute GSR of FF_150 : label is "ENABLED";
+ attribute GSR of FF_149 : label is "ENABLED";
+ attribute GSR of FF_148 : label is "ENABLED";
+ attribute GSR of FF_147 : label is "ENABLED";
+ attribute GSR of FF_146 : label is "ENABLED";
+ attribute GSR of FF_145 : label is "ENABLED";
+ attribute GSR of FF_144 : label is "ENABLED";
+ attribute GSR of FF_143 : label is "ENABLED";
+ attribute GSR of FF_142 : label is "ENABLED";
+ attribute GSR of FF_141 : label is "ENABLED";
+ attribute GSR of FF_140 : label is "ENABLED";
+ attribute GSR of FF_139 : label is "ENABLED";
+ attribute GSR of FF_138 : label is "ENABLED";
+ attribute GSR of FF_137 : label is "ENABLED";
+ attribute GSR of FF_136 : label is "ENABLED";
+ attribute GSR of FF_135 : label is "ENABLED";
+ attribute GSR of FF_134 : label is "ENABLED";
+ attribute GSR of FF_133 : label is "ENABLED";
+ attribute GSR of FF_132 : label is "ENABLED";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t34: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_11: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t33: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_10: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t32: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t31: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t30: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t29: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t28: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t27: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t26: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t25: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t24: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t23: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t22: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t21: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15);
+
+ XOR2_t15: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t14: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t13: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t12: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t11: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t10: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15);
+
+ INV_9: INV
+ port map (A=>wptr_11, Z=>wptr_11_inv);
+
+ INV_8: INV
+ port map (A=>wptr_12, Z=>wptr_12_inv);
+
+ INV_7: INV
+ port map (A=>wptr_13, Z=>wptr_13_inv);
+
+ INV_6: INV
+ port map (A=>wptr_14, Z=>wptr_14_inv);
+
+ INV_5: INV
+ port map (A=>wptr_15, Z=>wptr_15_inv);
+
+ LUT4_187: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet);
+
+ LUT4_186: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_p00);
+
+ INV_4: INV
+ port map (A=>rptr_11, Z=>rptr_11_inv);
+
+ INV_3: INV
+ port map (A=>rptr_12, Z=>rptr_12_inv);
+
+ INV_2: INV
+ port map (A=>rptr_13, Z=>rptr_13_inv);
+
+ INV_1: INV
+ port map (A=>rptr_14, Z=>rptr_14_inv);
+
+ INV_0: INV
+ port map (A=>rptr_15, Z=>rptr_15_inv);
+
+ LUT4_185: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_1);
+
+ LUT4_184: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec1_r10);
+
+ LUT4_183: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_2);
+
+ LUT4_182: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec2_p01);
+
+ LUT4_181: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_3);
+
+ LUT4_180: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec3_r11);
+
+ LUT4_179: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_4);
+
+ LUT4_178: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec4_p02);
+
+ LUT4_177: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_5);
+
+ LUT4_176: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec5_r12);
+
+ LUT4_175: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_6);
+
+ LUT4_174: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec6_p03);
+
+ LUT4_173: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_7);
+
+ LUT4_172: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec7_r13);
+
+ LUT4_171: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_8);
+
+ LUT4_170: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec8_p04);
+
+ LUT4_169: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_9);
+
+ LUT4_168: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec9_r14);
+
+ LUT4_167: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_10);
+
+ LUT4_166: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05);
+
+ LUT4_165: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_11);
+
+ LUT4_164: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15);
+
+ LUT4_163: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_12);
+
+ LUT4_162: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06);
+
+ LUT4_161: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_13);
+
+ LUT4_160: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16);
+
+ LUT4_159: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_14);
+
+ LUT4_158: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07);
+
+ LUT4_157: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_15);
+
+ LUT4_156: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17);
+
+ LUT4_155: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_16);
+
+ LUT4_154: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08);
+
+ LUT4_153: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_17);
+
+ LUT4_152: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18);
+
+ LUT4_151: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_18);
+
+ LUT4_150: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09);
+
+ LUT4_149: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_19);
+
+ LUT4_148: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19);
+
+ LUT4_147: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_20);
+
+ LUT4_146: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010);
+
+ LUT4_145: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_21);
+
+ LUT4_144: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110);
+
+ LUT4_143: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_22);
+
+ LUT4_142: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011);
+
+ LUT4_141: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_23);
+
+ LUT4_140: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111);
+
+ LUT4_139: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_24);
+
+ LUT4_138: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012);
+
+ LUT4_137: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_25);
+
+ LUT4_136: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112);
+
+ LUT4_135: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_26);
+
+ LUT4_134: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013);
+
+ LUT4_133: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_27);
+
+ LUT4_132: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113);
+
+ LUT4_131: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_28);
+
+ LUT4_130: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014);
+
+ LUT4_129: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_29);
+
+ LUT4_128: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114);
+
+ LUT4_127: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>func_and_inet_30);
+
+ LUT4_126: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015);
+
+ LUT4_125: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>func_and_inet_31);
+
+ LUT4_124: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv,
+ AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115);
+
+ LUT4_123: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_32);
+
+ LUT4_122: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec32_p016);
+
+ LUT4_121: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_33);
+
+ LUT4_120: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec33_r116);
+
+ LUT4_119: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_34);
+
+ LUT4_118: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec34_p017);
+
+ LUT4_117: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_35);
+
+ LUT4_116: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec35_r117);
+
+ LUT4_115: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_36);
+
+ LUT4_114: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec36_p018);
+
+ LUT4_113: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_37);
+
+ LUT4_112: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec37_r118);
+
+ LUT4_111: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_38);
+
+ LUT4_110: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec38_p019);
+
+ LUT4_109: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_39);
+
+ LUT4_108: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec39_r119);
+
+ LUT4_107: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_40);
+
+ LUT4_106: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec40_p020);
+
+ LUT4_105: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_41);
+
+ LUT4_104: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec41_r120);
+
+ LUT4_103: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_42);
+
+ LUT4_102: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec42_p021);
+
+ LUT4_101: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_43);
+
+ LUT4_100: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec43_r121);
+
+ LUT4_99: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_44);
+
+ LUT4_98: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec44_p022);
+
+ LUT4_97: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_45);
+
+ LUT4_96: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec45_r122);
+
+ LUT4_95: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>func_and_inet_46);
+
+ LUT4_94: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec46_p023);
+
+ LUT4_93: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>func_and_inet_47);
+
+ LUT4_92: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec47_r123);
+
+ LUT4_91: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_48);
+
+ LUT4_90: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec48_p024);
+
+ LUT4_89: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_49);
+
+ LUT4_88: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec49_r124);
+
+ LUT4_87: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_50);
+
+ LUT4_86: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec50_p025);
+
+ LUT4_85: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_51);
+
+ LUT4_84: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec51_r125);
+
+ LUT4_83: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_52);
+
+ LUT4_82: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec52_p026);
+
+ LUT4_81: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_53);
+
+ LUT4_80: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec53_r126);
+
+ LUT4_79: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>func_and_inet_54);
+
+ LUT4_78: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec54_p027);
+
+ LUT4_77: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>func_and_inet_55);
+
+ LUT4_76: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec55_r127);
+
+ LUT4_75: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_56);
+
+ LUT4_74: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec56_p028);
+
+ LUT4_73: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_57);
+
+ LUT4_72: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec57_r128);
+
+ LUT4_71: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_58);
+
+ LUT4_70: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec58_p029);
+
+ LUT4_69: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_59);
+
+ LUT4_68: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec59_r129);
+
+ LUT4_67: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>func_and_inet_60);
+
+ LUT4_66: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec60_p030);
+
+ LUT4_65: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>func_and_inet_61);
+
+ LUT4_64: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec61_r130);
+
+ LUT4_63: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>func_and_inet_62);
+
+ LUT4_62: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec62_p031);
+
+ LUT4_61: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>func_and_inet_63);
+
+ LUT4_60: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec63_r131);
+
+ LUT4_59: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214,
+ AD1=>w_gcount_r215, AD0=>w_gcount_r216,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_58: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>w_gcount_r212,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_57: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_56: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_3);
+
+ LUT4_55: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r15);
+
+ LUT4_54: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215,
+ AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14);
+
+ LUT4_53: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
+ AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12);
+
+ LUT4_52: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
+ AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11);
+
+ LUT4_51: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0,
+ DO0=>wcount_r10);
+
+ LUT4_50: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9);
+
+ LUT4_49: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8);
+
+ LUT4_48: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7);
+
+ LUT4_47: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_46: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+ LUT4_45: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_44: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4);
+
+ LUT4_43: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1);
+
+ LUT4_42: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
+ DO0=>wcount_r3);
+
+ LUT4_41: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_3_2);
+
+ LUT4_40: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2,
+ DO0=>wcount_r2);
+
+ LUT4_39: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
+ DO0=>wcount_r1);
+
+ LUT4_38: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet);
+
+ LUT4_37: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1);
+
+ LUT4_36: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2);
+
+ LUT4_35: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
+ AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3);
+
+ LUT4_34: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>func_xor_inet_4);
+
+ LUT4_33: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1,
+ AD1=>func_xor_inet_2, AD0=>func_xor_inet_3,
+ DO0=>func_xor_inet_5);
+
+ LUT4_32: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_31: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214,
+ AD1=>r_gcount_w215, AD0=>r_gcount_w216,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_30: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
+ AD1=>r_gcount_w211, AD0=>r_gcount_w212,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_29: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>r_gcount_w28,
+ DO0=>r_g2b_xor_cluster_2);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_3);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w15);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215,
+ AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
+ AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212,
+ AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
+ AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0,
+ DO0=>rcount_w10);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>scuba_vlo,
+ DO0=>r_g2b_xor_cluster_2_1);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1,
+ DO0=>rcount_w3);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo,
+ DO0=>r_g2b_xor_cluster_3_2);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2,
+ DO0=>rcount_w2);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3,
+ DO0=>rcount_w1);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
+ AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213,
+ AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>func_xor_inet_10);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7,
+ AD1=>func_xor_inet_8, AD0=>func_xor_inet_9,
+ DO0=>func_xor_inet_11);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_31: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
+ DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
+ DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
+ DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_1_0_30: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
+ DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
+ DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
+ DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_2_0_29: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
+ DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
+ DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
+ DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_3_0_28: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
+ DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
+ DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
+ DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_4_0_27: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
+ DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
+ DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
+ DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_5_0_26: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
+ DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
+ DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
+ DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_6_0_25: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
+ DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
+ DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
+ DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_7_0_24: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
+ DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
+ DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
+ DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_8_0_23: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
+ DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
+ DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
+ DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_9_0_22: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
+ DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
+ DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
+ DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_10_0_21: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0,
+ DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3,
+ DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6,
+ DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_11_0_20: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0,
+ DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3,
+ DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6,
+ DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_12_0_19: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0,
+ DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3,
+ DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6,
+ DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_13_0_18: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0,
+ DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3,
+ DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6,
+ DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_14_0_17: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0,
+ DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3,
+ DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6,
+ DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_15_0_16: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0,
+ DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3,
+ DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6,
+ DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_16_0_15: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0,
+ DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3,
+ DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6,
+ DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_17_0_14: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0,
+ DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3,
+ DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6,
+ DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_18_0_13: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0,
+ DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3,
+ DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6,
+ DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_19_0_12: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0,
+ DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3,
+ DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6,
+ DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_20_0_11: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0,
+ DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3,
+ DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6,
+ DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_21_0_10: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0,
+ DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3,
+ DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6,
+ DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_22_0_9: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0,
+ DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3,
+ DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6,
+ DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_23_0_8: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0,
+ DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3,
+ DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6,
+ DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_24_0_7: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0,
+ DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3,
+ DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6,
+ DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_25_0_6: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0,
+ DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3,
+ DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6,
+ DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_26_0_5: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0,
+ DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3,
+ DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6,
+ DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_27_0_4: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0,
+ DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3,
+ DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6,
+ DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_28_0_3: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0,
+ DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3,
+ DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6,
+ DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_29_0_2: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0,
+ DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3,
+ DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6,
+ DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_30_0_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0,
+ DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3,
+ DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6,
+ DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ pdp_ram_31_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0,
+ DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3,
+ DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6,
+ DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ FF_176: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_175: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_174: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_173: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_172: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_171: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_170: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_169: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_168: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_167: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_166: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_165: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_164: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_163: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_162: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_161: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_15);
+
+ FF_160: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_16);
+
+ FF_159: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_158: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_157: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_156: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_155: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_154: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_153: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_152: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_151: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_150: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_149: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_148: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_147: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_146: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_13);
+
+ FF_145: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_14);
+
+ FF_144: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_15);
+
+ FF_143: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_16);
+
+ FF_142: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_141: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_140: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_139: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_138: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_137: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_136: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_135: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_134: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_133: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_132: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_131: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_130: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_129: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_128: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_14);
+
+ FF_127: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_15);
+
+ FF_126: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_16);
+
+ FF_125: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_124: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_123: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_10);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_11);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_12);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_13);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_14);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_15);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_16);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_10);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_11);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_12);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_13);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_14);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_15);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_16);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_10);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_11);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_12);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_13);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_14);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_15);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_16);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_13_ff);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_14_ff);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
+ Q=>rptr_15_ff);
+
+ FF_69: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_68: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_67: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_66: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_65: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_64: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_63: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_62: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_60: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_59: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_58: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r13);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r14);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r15);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r16);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r213);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r214);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r215);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r216);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w210);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w211);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w212);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w213);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w214);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w215);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w216);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ w_gctr_7: CU2
+ port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7,
+ NC0=>iwcount_14, NC1=>iwcount_15);
+
+ w_gctr_8: CU2
+ port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8,
+ NC0=>iwcount_16, NC1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_gctr_5: CU2
+ port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
+ NC0=>ircount_10, NC1=>ircount_11);
+
+ r_gctr_6: CU2
+ port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1,
+ NC0=>ircount_12, NC1=>ircount_13);
+
+ r_gctr_7: CU2
+ port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1,
+ NC0=>ircount_14, NC1=>ircount_15);
+
+ r_gctr_8: CU2
+ port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1,
+ NC0=>ircount_16, NC1=>open);
+
+ mux_8: MUX321
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
+ D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
+ D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
+ D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0,
+ D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0,
+ D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0,
+ D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0,
+ D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0,
+ D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(0));
+
+ mux_7: MUX321
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
+ D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
+ D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
+ D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1,
+ D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1,
+ D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1,
+ D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1,
+ D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1,
+ D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(1));
+
+ mux_6: MUX321
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
+ D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
+ D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
+ D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2,
+ D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2,
+ D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2,
+ D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2,
+ D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2,
+ D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(2));
+
+ mux_5: MUX321
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
+ D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
+ D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
+ D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3,
+ D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3,
+ D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3,
+ D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3,
+ D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3,
+ D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(3));
+
+ mux_4: MUX321
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
+ D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
+ D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
+ D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4,
+ D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4,
+ D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4,
+ D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4,
+ D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4,
+ D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(4));
+
+ mux_3: MUX321
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
+ D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
+ D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
+ D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5,
+ D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5,
+ D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5,
+ D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5,
+ D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5,
+ D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(5));
+
+ mux_2: MUX321
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
+ D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
+ D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
+ D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6,
+ D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6,
+ D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6,
+ D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6,
+ D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6,
+ D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(6));
+
+ mux_1: MUX321
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
+ D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
+ D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
+ D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7,
+ D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7,
+ D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7,
+ D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7,
+ D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7,
+ D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(7));
+
+ mux_0: MUX321
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
+ D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
+ D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
+ D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8,
+ D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8,
+ D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8,
+ D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8,
+ D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8,
+ D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff,
+ SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff,
+ SD5=>rptr_15_ff, Z=>Q(8));
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
+ B1=>wcount_r9, CI=>co3_2, GE=>co4_2);
+
+ empty_cmp_5: AGEB2
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
+ B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
+
+ empty_cmp_6: AGEB2
+ port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12,
+ B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2);
+
+ empty_cmp_7: AGEB2
+ port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14,
+ B1=>wcount_r15, CI=>co6_2, GE=>co7_2);
+
+ empty_cmp_8: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
+ B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
+ B1=>rcount_w9, CI=>co3_3, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
+ B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
+
+ full_cmp_6: AGEB2
+ port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12,
+ B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3);
+
+ full_cmp_7: AGEB2
+ port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14,
+ B1=>rcount_w15, CI=>co6_3, GE=>co7_3);
+
+ full_cmp_8: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_64kx9 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:MUX321 use entity ecp2m.MUX321(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trbnet.git / commitdiff