BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
-PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
BLOCK PATH TO PORT "TEMPSENS";
BLOCK PATH FROM PORT "TEMPSENS";
BLOCK PATH TO PORT "TESTLINE";
+
+PROHIBIT PRIMARY NET "ENPIRION_CLOCK_c" ;
+PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ;
\ No newline at end of file
#################################################################\r
# AddOn Connector\r
#################################################################\r
-# # LOCATE COMP "DQLL0_0_N" SITE "AA1";\r
-# # LOCATE COMP "DQLL0_1_N" SITE "AB1";\r
-# # LOCATE COMP "DQLL0_2_N" SITE "AA3";\r
-# # LOCATE COMP "DQLL0_3_N" SITE "AB5";\r
-# # LOCATE COMP "DQLL0_4_N" SITE "AA7";\r
-# # LOCATE COMP "DQLL1_0_N" SITE "Y1";\r
-# # LOCATE COMP "DQLL1_1_N" SITE "W3";\r
-# # LOCATE COMP "DQLL1_2_N" SITE "W1";\r
-# # LOCATE COMP "DQLL1_3_N" SITE "W9";\r
-# # LOCATE COMP "DQLL1_4_N" SITE "AA8";\r
-# # LOCATE COMP "DQLL2_0_N" SITE "AC4";\r
-# # LOCATE COMP "DQLL2_1_N" SITE "AC1";\r
-# # LOCATE COMP "DQLL2_2_N" SITE "AB3";\r
-# # LOCATE COMP "DQLL2_3_N" SITE "AB8";\r
-# # LOCATE COMP "DQLL2_4_N" SITE "AB6";\r
-# # LOCATE COMP "DQLL3_0_N" SITE "AE3";\r
-# # LOCATE COMP "DQLL3_1_N" SITE "AC10"\r
-# # LOCATE COMP "DQLL3_2_N" SITE "AE1";\r
-# # LOCATE COMP "DQLL3_3_N" SITE "AD3";\r
-# # LOCATE COMP "DQLL3_4_N" SITE "AC8";\r
-# # LOCATE COMP "DQLR0_0_N" SITE "AB33"\r
-# # LOCATE COMP "DQLR0_1_N" SITE "AA26"\r
-# # LOCATE COMP "DQLR0_2_N" SITE "AC33"\r
-# # LOCATE COMP "DQLR0_3_N" SITE "AA30"\r
-# # LOCATE COMP "DQLR0_4_N" SITE "AA27"\r
-# # LOCATE COMP "DQLR1_0_N" SITE "AD30"\r
-# # LOCATE COMP "DQLR1_1_N" SITE "AB31"\r
-# # LOCATE COMP "DQLR1_2_N" SITE "AE33"\r
-# # LOCATE COMP "DQLR1_3_N" SITE "AD34"\r
-# # LOCATE COMP "DQLR1_4_N" SITE "AG34"\r
-# # LOCATE COMP "DQLR2_0_N" SITE "W29";\r
-# # LOCATE COMP "DQLR2_1_N" SITE "W26";\r
-# # LOCATE COMP "DQLR2_2_N" SITE "W33";;\r
-# # LOCATE COMP "DQLR2_3_N" SITE "Y33";;\r
-# # LOCATE COMP "DQLR2_4_N" SITE "Y25";\r
-# # LOCATE COMP "DQSLL0_C" SITE "AB9";\r
-# # LOCATE COMP "DQSLL1_C" SITE "Y6";\r
-# # LOCATE COMP "DQSLL2_C" SITE "AE5";\r
-# # LOCATE COMP "DQSLL3_C" SITE "AK1";\r
-# # LOCATE COMP "DQSLR0_C" SITE "AC30"\r
-# # LOCATE COMP "DQSLR1_C" SITE "AB25";\r
-# # LOCATE COMP "DQSLR2_C" SITE "AA29";\r
-# # LOCATE COMP "DQSUL0_C" SITE "M9";;\r
-# # LOCATE COMP "DQSUL1_C" SITE "L9";;\r
-# # LOCATE COMP "DQSUL2_C" SITE "H3";;\r
-# # LOCATE COMP "DQSUL3_C" SITE "N10";;\r
-# # LOCATE COMP "DQSUR0_C" SITE "M27";;\r
-# # LOCATE COMP "DQSUR1_C" SITE "N28";;\r
-# # LOCATE COMP "DQSUR2_C" SITE "U30";;\r
-# # LOCATE COMP "DQUL0_0_N" SITE "L4";;\r
-# # LOCATE COMP "DQUL0_1_N" SITE "M3";;\r
-# # LOCATE COMP "DQUL0_2_N" SITE "K5";;\r
-# # LOCATE COMP "DQUL0_3_N" SITE "M1";;\r
-# # LOCATE COMP "DQUL0_4_N" SITE "L6";;\r
-# # LOCATE COMP "DQUL1_0_N" SITE "L1";;\r
-# # LOCATE COMP "DQUL1_1_N" SITE "K1";;\r
-# # LOCATE COMP "DQUL1_2_N" SITE "K3";;\r
-# # LOCATE COMP "DQUL1_3_N" SITE "L7";;\r
-# # LOCATE COMP "DQUL1_4_N" SITE "J6";;\r
-# # LOCATE COMP "DQUL2_0_N" SITE "F1";;\r
-# # LOCATE COMP "DQUL2_1_N" SITE "E3";\r
-# # LOCATE COMP "DQUL2_2_N" SITE "G1";\r
-# # LOCATE COMP "DQUL2_3_N" SITE "J1";\r
-# # LOCATE COMP "DQUL2_4_N" SITE "H2";\r
-# # LOCATE COMP "DQUL3_0_N" SITE "N3";\r
-# # LOCATE COMP "DQUL3_1_N" SITE "N1";\r
-# # LOCATE COMP "DQUL3_2_N" SITE "N5";\r
-# # LOCATE COMP "DQUL3_3_N" SITE "P4";\r
-# # LOCATE COMP "DQUL3_4_N" SITE "P8";\r
-# # LOCATE COMP "DQUR0_0_N" SITE "M25";\r
-# # LOCATE COMP "DQUR0_1_N" SITE "L31";\r
-# # LOCATE COMP "DQUR0_2_N" SITE "L33";;\r
-# # LOCATE COMP "DQUR0_3_N" SITE "K30";\r
-# # LOCATE COMP "DQUR0_4_N" SITE "K33";\r
-# # LOCATE COMP "DQUR1_0_N" SITE "N29";\r
-# # LOCATE COMP "DQUR1_1_N" SITE "P26";\r
-# # LOCATE COMP "DQUR1_2_N" SITE "N31";\r
-# # LOCATE COMP "DQUR1_3_N" SITE "N33";\r
-# # LOCATE COMP "DQUR1_4_N" SITE "P27";;\r
-# # LOCATE COMP "DQUR2_0_N" SITE "T31";;\r
-# # LOCATE COMP "DQUR2_1_N" SITE "T27";;\r
-# # LOCATE COMP "DQUR2_2_N" SITE "U31";;\r
-# # LOCATE COMP "DQUR2_3_N" SITE "T33";;\r
-# # LOCATE COMP "DQUR2_4_N" SITE "U27";\r
-# \r
-# LOCATE COMP "DQLL0_0" SITE "AA2"; #was "DQLL0_0_P" 1\r
-# LOCATE COMP "DQLL0_1" SITE "AB2"; #was "DQLL0_1_P" 5\r
-# LOCATE COMP "DQLL0_2" SITE "AA4"; #was "DQLL0_2_P" 9\r
-# LOCATE COMP "DQSLL0" SITE "AA10"; #was "DQSLL0_T" 13\r
-# LOCATE COMP "DQLL0_3" SITE "AA5"; #was "DQLL0_3_P" 17\r
-# LOCATE COMP "DQLL0_4" SITE "Y7"; #was "DQLL0_4_P" 21\r
-# LOCATE COMP "DQLL2_0" SITE "AC5"; #was "DQLL2_0_P" 25\r
-# LOCATE COMP "DQLL2_1" SITE "AC2"; #was "DQLL2_1_P" 29\r
-# LOCATE COMP "DQLL2_2" SITE "AB4"; #was "DQLL2_2_P" 33\r
-# LOCATE COMP "DQSLL2" SITE "AD5"; #was "DQSLL2_T" 37\r
-# LOCATE COMP "DQLL2_3" SITE "AA9"; #was "DQLL2_3_P" 41\r
-# LOCATE COMP "DQLL2_4" SITE "AB7"; #was "DQLL2_4_P" 45\r
-# LOCATE COMP "DQUL3_0" SITE "N4"; #was "DQUL3_0_P" 49\r
-# LOCATE COMP "DQUL3_1" SITE "N2"; #was "DQUL3_1_P" 53\r
-# LOCATE COMP "DQUL3_2" SITE "M5"; #was "DQUL3_2_P" 57\r
-# LOCATE COMP "DQSUL3" SITE "M10"; #was "DQSUL3_T" 61\r
-# LOCATE COMP "DQUL3_3" SITE "P5"; #was "DQUL3_3_P" 65\r
-# LOCATE COMP "DQUL3_4" SITE "N8"; #was "DQUL3_4_P" 69\r
-# LOCATE COMP "DQUL1_0" SITE "L2"; #was "DQUL1_0_P" 73\r
-# LOCATE COMP "DQUL1_1" SITE "K2"; #was "DQUL1_1_P" 77\r
-# LOCATE COMP "DQUL1_2" SITE "K4"; #was "DQUL1_2_P" 81\r
-# LOCATE COMP "DQSUL1" SITE "L10"; #was "DQSUL1_T" 85\r
-# LOCATE COMP "DQUL1_3" SITE "M8"; #was "DQUL1_3_P" 89\r
-# LOCATE COMP "DQUL1_4" SITE "K7"; #was "DQUL1_4_P" 93\r
-# \r
-# LOCATE COMP "DQUR0_0" SITE "L26"; #was "DQUR0_0_P" 105\r
-# LOCATE COMP "DQUR0_1" SITE "L32"; #was "DQUR0_1_P" 109\r
-# LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113\r
-# LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117\r
-# LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121\r
-# LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125\r
-# LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129\r
-# LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133\r
-# LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137\r
-# LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141\r
-# LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145\r
-# LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149\r
-# \r
-# LOCATE COMP "DQLR1_0" SITE "AD31"; #was "DQLR1_0_P" 169\r
-# LOCATE COMP "DQLR1_1" SITE "AB32"; #was "DQLR1_1_P" 173\r
-# LOCATE COMP "DQLR1_2" SITE "AE34"; #was "DQLR1_2_P" 177\r
-# LOCATE COMP "DQSLR1" SITE "AB26"; #was "DQSLR1_T" 181\r
-# LOCATE COMP "DQLR1_3" SITE "AD33"; #was "DQLR1_3_P" 185\r
-# LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189\r
-# \r
-# \r
-# LOCATE COMP "DQLL3_0" SITE "AE4"; #was "DQLL3_0_P" 2\r
-# LOCATE COMP "DQLL3_1" SITE "AB10"; #was "DQLL3_1_P" 6\r
-# LOCATE COMP "DQLL3_2" SITE "AE2"; #was "DQLL3_2_P" 10\r
-# LOCATE COMP "DQSLL3" SITE "AJ1"; #was "DQSLL3_T" 14\r
-# LOCATE COMP "DQLL3_3" SITE "AD4"; #was "DQLL3_3_P" 18\r
-# LOCATE COMP "DQLL3_4" SITE "AC9"; #was "DQLL3_4_P" 22\r
-# LOCATE COMP "DQLL1_0" SITE "Y2"; #was "DQLL1_0_P" 26\r
-# LOCATE COMP "DQLL1_1" SITE "W4"; #was "DQLL1_1_P" 30\r
-# LOCATE COMP "DQLL1_2" SITE "W2"; #was "DQLL1_2_P" 34\r
-# LOCATE COMP "DQSLL1" SITE "W6"; #was "DQSLL1_T" 38\r
-# LOCATE COMP "DQLL1_3" SITE "W8"; #was "DQLL1_3_P" 42\r
-# LOCATE COMP "DQLL1_4" SITE "Y8"; #was "DQLL1_4_P" 46\r
-# LOCATE COMP "DQUL2_0" SITE "F2"; #was "DQUL2_0_P" 50\r
-# LOCATE COMP "DQUL2_1" SITE "F3"; #was "DQUL2_1_P" 54\r
-# LOCATE COMP "DQUL2_2" SITE "G2"; #was "DQUL2_2_P" 58\r
-# LOCATE COMP "DQSUL2" SITE "G3"; #was "DQSUL2_T" 62\r
-# LOCATE COMP "DQUL2_3" SITE "H1"; #was "DQUL2_3_P" 66\r
-# LOCATE COMP "DQUL2_4" SITE "J3"; #was "DQUL2_4_P" 70\r
-# LOCATE COMP "DQUL0_0" SITE "L5"; #was "DQUL0_0_P" 74\r
-# LOCATE COMP "DQUL0_1" SITE "M4"; #was "DQUL0_1_P" 78\r
-# LOCATE COMP "DQUL0_2" SITE "K6"; #was "DQUL0_2_P" 82\r
-# LOCATE COMP "DQSUL0" SITE "N9"; #was "DQSUL0_T" 86\r
-# LOCATE COMP "DQUL0_3" SITE "M2"; #was "DQUL0_3_P" 90\r
-# LOCATE COMP "DQUL0_4" SITE "M7"; #was "DQUL0_4_P" 94\r
-# \r
-# LOCATE COMP "DQUR1_0" SITE "N30"; #was "DQUR1_0_P" 106\r
-# LOCATE COMP "DQUR1_1" SITE "N26"; #was "DQUR1_1_P" 110\r
-# LOCATE COMP "DQUR1_2" SITE "N32"; #was "DQUR1_2_P" 114\r
-# LOCATE COMP "DQSUR1" SITE "N27"; #was "DQSUR1_T" 118\r
-# LOCATE COMP "DQUR1_3" SITE "N34"; #was "DQUR1_3_P" 122\r
-# LOCATE COMP "DQUR1_4" SITE "P28"; #was "DQUR1_4_P" 126\r
-# LOCATE COMP "DQUR2_0" SITE "T32"; #was "DQUR2_0_P" 130\r
-# LOCATE COMP "DQUR2_1" SITE "T26"; #was "DQUR2_1_P" 134\r
-# LOCATE COMP "DQUR2_2" SITE "U32"; #was "DQUR2_2_P" 138\r
-# LOCATE COMP "DQSUR2" SITE "T30"; #was "DQSUR2_T" 142\r
-# LOCATE COMP "DQUR2_3" SITE "T34"; #was "DQUR2_3_P" 146\r
-# LOCATE COMP "DQUR2_4" SITE "U26"; #was "DQUR2_4_P" 150\r
-# \r
-# LOCATE COMP "DQLR2_0" SITE "W30"; #was "DQLR2_0_P" 170\r
-# LOCATE COMP "DQLR2_1" SITE "W27"; #was "DQLR2_1_P" 174\r
-# LOCATE COMP "DQLR2_2" SITE "W34"; #was "DQLR2_2_P" 178\r
-# LOCATE COMP "DQSLR2" SITE "Y30"; #was "DQSLR2_T" 182\r
-# LOCATE COMP "DQLR2_3" SITE "Y34"; #was "DQLR2_3_P" 186\r
-# LOCATE COMP "DQLR2_4" SITE "Y26"; #was "DQLR2_4_P" 190\r
-# \r
-# DEFINE PORT GROUP "DQ_group" "DQ*" ;\r
-# IOBUF GROUP "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; \r
-\r
\r
+LOCATE COMP "INP_0" SITE "AA2"; #was "DQLL0_0_P" 1\r
+# LOCATE COMP "IN_0_N" SITE "AA1";\r
+LOCATE COMP "INP_1" SITE "AB2"; #was "DQLL0_1_P" 5\r
+# LOCATE COMP "IN_1_N" SITE "AB1";\r
+LOCATE COMP "INP_2" SITE "AA4"; #was "DQLL0_2_P" 9\r
+# LOCATE COMP "IN_2_N" SITE "AA3";\r
+LOCATE COMP "INP_3" SITE "AA10"; #was "DQSLL0_T" 13\r
+# LOCATE COMP "IN_3_N" SITE "AB9";\r
+DEFINE PORT GROUP "IN_group" "INP*" ;\r
+IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+\r
+\r
+\r
+LOCATE COMP "OUTP_1" SITE "AB10"; #was "DQLL3_1_P" 6\r
+LOCATE COMP "OUTP_2" SITE "AE2"; #was "DQLL3_2_P" 10\r
+LOCATE COMP "OUTP_3" SITE "AC9"; #was "DQLL3_4_P" 22\r
+LOCATE COMP "OUTP_4" SITE "W4"; #was "DQLL1_1_P" 30\r
+LOCATE COMP "OUTP_5" SITE "W8"; #was "DQLL1_3_P" 42\r
+LOCATE COMP "OUTP_6" SITE "Y8"; #was "DQLL1_4_P" 46\r
+LOCATE COMP "OUTP_7" SITE "F3"; #was "DQUL2_1_P" 54\r
+LOCATE COMP "OUTP_8" SITE "G2"; #was "DQUL2_2_P" 58\r
+LOCATE COMP "OUTP_9" SITE "AA5"; #was "DQLL0_3_P" 17\r
+LOCATE COMP "OUTP_10" SITE "Y7"; #was "DQLL0_4_P" 21\r
+LOCATE COMP "OUTP_11" SITE "AC2"; #was "DQLL2_1_P" 29\r
+LOCATE COMP "OUTP_12" SITE "AA9"; #was "DQLL2_3_P" 41\r
+LOCATE COMP "OUTP_13" SITE "AB7"; #was "DQLL2_4_P" 45\r
+LOCATE COMP "OUTP_14" SITE "N2"; #was "DQUL3_1_P" 53\r
+LOCATE COMP "OUTP_15" SITE "M4"; #was "DQUL0_1_P" 78\r
+LOCATE COMP "OUTP_16" SITE "K6"; #was "DQUL0_2_P" 82\r
+\r
+LOCATE COMP "OUTP_FAN_0" SITE "J3"; #was "DQUL2_4_P" 70\r
+LOCATE COMP "OUTP_FAN_1" SITE "K7"; #was "DQUL1_4_P" 93\r
+LOCATE COMP "OUTP_FAN_2" SITE "K2"; #was "DQUL1_1_P" 77\r
+LOCATE COMP "OUTP_FAN_3" SITE "M7"; #was "DQUL0_4_P" 94\r
+\r
+LOCATE COMP "OUTP_ANA_0" SITE "AA31"; #was "DQLR0_3_P" 145\r
+LOCATE COMP "OUTP_ANA_1" SITE "AA25"; #was "DQLR0_1_P" 133\r
+LOCATE COMP "OUTP_ANA_2" SITE "L32"; #was "DQUR0_1_P" 109\r
+LOCATE COMP "OUTP_ANA_3" SITE "K29"; #was "DQUR0_3_P" 121\r
+LOCATE COMP "OUTP_ANA_4" SITE "L26"; #was "DQUR0_0_P" 105\r
+LOCATE COMP "OUTP_ANA_5" SITE "AD31"; #was "DQLR1_0_P" 169\r
+LOCATE COMP "OUTP_ANA_6" SITE "AD33"; #was "DQLR1_3_P" 185\r
+LOCATE COMP "OUTP_ANA_7" SITE "AE34"; #was "DQLR1_2_P" 177\r
+LOCATE COMP "OUTP_ANA_8" SITE "W27"; #was "DQLR2_1_P" 174\r
+LOCATE COMP "OUTP_ANA_9" SITE "Y34"; #was "DQLR2_3_P" 186\r
+\r
+DEFINE PORT GROUP "OUT_group" "OUTP*" ;\r
+IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 SLEW=FAST ;\r
+\r
+\r
+\r
+\r
+LOCATE COMP "SEL1_0" SITE "M26"; #was "DQSUR0_T" 113\r
+LOCATE COMP "SEL1_1" SITE "M27";\r
+LOCATE COMP "SEL1_2" SITE "L34"; #was "DQUR0_2_P" 117\r
+LOCATE COMP "SEL1_3" SITE "L33";\r
+LOCATE COMP "SEL2_0" SITE "W30"; #was "DQLR2_0_P" 170\r
+LOCATE COMP "SEL2_1" SITE "W29";\r
+LOCATE COMP "SEL2_2" SITE "W34"; #was "DQLR2_2_P" 178\r
+LOCATE COMP "SEL2_3" SITE "W33";\r
+LOCATE COMP "SELO1_0" SITE "K34"; #was "DQUR0_4_P" 125\r
+LOCATE COMP "SELO1_1" SITE "K33";\r
+LOCATE COMP "SELO2_0" SITE "Y30"; #was "DQSLR2_T" 182\r
+LOCATE COMP "SELO2_1" SITE "AA29";\r
+DEFINE PORT GROUP "SEL_group" "SEL*" ;\r
+IOBUF GROUP "SEL_group" IO_TYPE=LVCMOS25 SLEW=FAST PULLMODE=NONE DRIVE=20;\r
+\r
+\r
+\r
+LOCATE COMP "LED_PULSER_0" SITE "AE4"; #was "DQLL3_0_P" 2\r
+LOCATE COMP "LED_PULSER_1" SITE "AE3";\r
+LOCATE COMP "LED_PULSER_2" SITE "AB26"; #was "DQSLR1_T" 181\r
+LOCATE COMP "LED_PULSER_3" SITE "AB25";\r
+LOCATE COMP "LED_PULSER_4" SITE "AB34"; #was "DQLR0_0_P" 129\r
+DEFINE PORT GROUP "PULSER_LED_group" "LED_PULSER*" ;\r
+IOBUF GROUP "PULSER_LED_group" IO_TYPE=LVCMOS25 SLEW=SLOW PULLMODE=NONE DRIVE=4;\r
+\r
+\r
+LOCATE COMP "MOSI" SITE "N26"; #was "DQUR1_1_P" 110\r
+LOCATE COMP "MISO" SITE "N32"; #was "DQUR1_2_P" 114\r
+LOCATE COMP "SCK" SITE "P28"; #was "DQUR1_4_P" 126\r
+LOCATE COMP "SCS" SITE "T26"; #was "DQUR2_1_P" 134\r
+IOBUF PORT "MOSI" IO_TYPE=LVDS25 SLEW=SLOW ;\r
+IOBUF PORT "MISO" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+IOBUF PORT "SCK" IO_TYPE=LVDS25 SLEW=SLOW ;\r
+IOBUF PORT "SCS" IO_TYPE=LVDS25 SLEW=SLOW ;\r
+\r
+LOCATE COMP "PULSER_TRIG_OUT" SITE "Y26"; #was "DQLR2_4_P" 190\r
+IOBUF PORT "PULSER_TRIG_OUT" IO_TYPE=LVDS25 SLEW=FAST ;\r
\r
\r
#################################################################\r
BLOCK RESETPATHS ;\r
BLOCK ASYNCPATHS ;\r
\r
+\r
+\r
+\r
+# LOCATE COMP "LED_LINKOK_1" SITE "AA2"; #was "DQLL0_0_P" 1\r
+# LOCATE COMP "LED_RX_1" SITE "AA1";\r
+# LOCATE COMP "LED_TX_1" SITE "AB2"; #was "DQLL0_1_P" 5\r
+# LOCATE COMP "SFP_MOD0_1" SITE "AB1";\r
+# LOCATE COMP "SFP_MOD1_1" SITE "AA4"; #was "DQLL0_2_P" 9\r
+# LOCATE COMP "SFP_MOD2_1" SITE "AA3";\r
+# LOCATE COMP "SFP_RATESEL_1" SITE "AA10"; #was "DQSLL0_T" 13\r
+# LOCATE COMP "SFP_TXDIS_1" SITE "AB9";\r
+# LOCATE COMP "SFP_LOS_1" SITE "AA5"; #was "DQLL0_3_P" 17\r
+# LOCATE COMP "SFP_TXFAULT_1" SITE "AB5";\r
+\r
+# LOCATE COMP "LED_LINKOK_2" SITE "Y7"; #was "DQLL0_4_P" 21\r
+# LOCATE COMP "LED_RX_2" SITE "AA7";\r
+# LOCATE COMP "LED_TX_2" SITE "AC5"; #was "DQLL2_0_P" 25\r
+# LOCATE COMP "SFP_MOD0_2" SITE "AC4";\r
+# LOCATE COMP "SFP_MOD1_2" SITE "AC2"; #was "DQLL2_1_P" 29\r
+# LOCATE COMP "SFP_MOD2_2" SITE "AC1";\r
+# LOCATE COMP "SFP_RATESEL_2" SITE "AB4"; #was "DQLL2_2_P" 33\r
+# LOCATE COMP "SFP_TXDIS_2" SITE "AB3";\r
+# LOCATE COMP "SFP_LOS_2" SITE "AD5"; #was "DQSLL2_T" 37\r
+# LOCATE COMP "SFP_TXFAULT_2" SITE "AE5";\r
+\r
+# LOCATE COMP SITE "AA9"; #was "DQLL2_3_P" 41\r
+# LOCATE COMP SITE "AB8";\r
+# LOCATE COMP SITE "AB7"; #was "DQLL2_4_P" 45\r
+# LOCATE COMP SITE "AB6";\r
+# LOCATE COMP SITE "N4"; #was "DQUL3_0_P" 49\r
+# LOCATE COMP SITE "N3";\r
+# LOCATE COMP SITE "N2"; #was "DQUL3_1_P" 53\r
+# LOCATE COMP SITE "N1";\r
+# LOCATE COMP SITE "M5"; #was "DQUL3_2_P" 57\r
+# LOCATE COMP SITE "N5";\r
+# LOCATE COMP SITE "M10"; #was "DQSUL3_T" 61\r
+# LOCATE COMP SITE "N10";;\r
+# LOCATE COMP SITE "P5"; #was "DQUL3_3_P" 65\r
+# LOCATE COMP SITE "P4";\r
+# LOCATE COMP SITE "N8"; #was "DQUL3_4_P" 69\r
+# LOCATE COMP SITE "P8";\r
+\r
+# LOCATE COMP "DQUL1_0" SITE "L2"; #was "DQUL1_0_P" 73\r
+# LOCATE COMP "DQUL1_0" SITE "L1";;\r
+# LOCATE COMP "DQUL1_1" SITE "K2"; #was "DQUL1_1_P" 77\r
+# LOCATE COMP "DQUL1_1" SITE "K1";;\r
+# LOCATE COMP "DQUL1_2" SITE "K4"; #was "DQUL1_2_P" 81\r
+# LOCATE COMP "DQUL1_2" SITE "K3";;\r
+# LOCATE COMP "DQSUL1" SITE "L10"; #was "DQSUL1_T" 85\r
+# LOCATE COMP "DQSUL1" SITE "L9";;\r
+# LOCATE COMP "DQUL1_3" SITE "M8"; #was "DQUL1_3_P" 89\r
+# LOCATE COMP "DQUL1_3" SITE "L7";;\r
+# LOCATE COMP "DQUL1_4" SITE "K7"; #was "DQUL1_4_P" 93\r
+# LOCATE COMP "DQUL1_4" SITE "J6";;\r
+# \r
+# LOCATE COMP "DQUR0_0" SITE "L26"; #was "DQUR0_0_P" 105\r
+# LOCATE COMP "DQUR0_0" SITE "M25";\r
+# LOCATE COMP "DQUR0_1" SITE "L32"; #was "DQUR0_1_P" 109\r
+# LOCATE COMP "DQUR0_1" SITE "L31";\r
+# LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113\r
+# LOCATE COMP "DQSUR0" SITE "M27";;\r
+# LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117\r
+# LOCATE COMP "DQUR0_2" SITE "L33";;\r
+# LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121\r
+# LOCATE COMP "DQUR0_3" SITE "K30";\r
+# LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125\r
+# LOCATE COMP "DQUR0_4" SITE "K33";\r
+\r
+# LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129\r
+# LOCATE COMP "DQLR0_0" SITE "AB33"\r
+# LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133\r
+# LOCATE COMP "DQLR0_1" SITE "AA26"\r
+# LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137\r
+# LOCATE COMP "DQLR0_2" SITE "AC33"\r
+# LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141\r
+# LOCATE COMP "DQSLR0" SITE "AC30"\r
+# LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145\r
+# LOCATE COMP "DQLR0_3" SITE "AA30"\r
+# LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149\r
+# LOCATE COMP "DQLR0_4" SITE "AA27"\r
+# \r
+# LOCATE COMP "LED_LINKOK_5" SITE "AD31"; #was "DQLR1_0_P" 169\r
+# LOCATE COMP "LED_RX_5" SITE "AD30"\r
+# LOCATE COMP "LED_TX_5" SITE "AB32"; #was "DQLR1_1_P" 173\r
+# LOCATE COMP "SFP_MOD0_5" SITE "AB31"\r
+# LOCATE COMP "SFP_MOD1_5" SITE "AE34"; #was "DQLR1_2_P" 177\r
+# LOCATE COMP "SFP_MOD2_5" SITE "AE33"\r
+# LOCATE COMP "SFP_RATESEL_5" SITE "AB26"; #was "DQSLR1_T" 181\r
+# LOCATE COMP "SFP_TXDIS_5" SITE "AB25";\r
+# LOCATE COMP "SFP_LOS_5" SITE "AD33"; #was "DQLR1_3_P" 185\r
+# LOCATE COMP "SFP_TXFAULT_5" SITE "AD34"\r
+# LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189\r
+# LOCATE COMP "DQLR1_4" SITE "AG34"\r
+# \r
+# LOCATE COMP "LED_LINKOK_3" SITE "AE4"; #was "DQLL3_0_P" 2\r
+# LOCATE COMP "LED_RX_3" SITE "AE3";\r
+# LOCATE COMP "LED_TX_3" SITE "AB10"; #was "DQLL3_1_P" 6\r
+# LOCATE COMP "SFP_MOD0_3" SITE "AC10"\r
+# LOCATE COMP "SFP_MOD1_3" SITE "AE2"; #was "DQLL3_2_P" 10\r
+# LOCATE COMP "SFP_MOD2_3" SITE "AE1";\r
+# LOCATE COMP "SFP_RATESEL_3" SITE "AJ1"; #was "DQSLL3_T" 14\r
+# LOCATE COMP "SFP_TXDIS_3" SITE "AK1";\r
+# LOCATE COMP "SFP_LOS_3" SITE "AD4"; #was "DQLL3_3_P" 18\r
+# LOCATE COMP "SFP_TXFAULT_3" SITE "AD3";\r
+\r
+# LOCATE COMP "LED_LINKOK_4" SITE "AC9"; #was "DQLL3_4_P" 22\r
+# LOCATE COMP "LED_RX_4" SITE "AC8";\r
+# LOCATE COMP "LED_TX_4" SITE "Y2"; #was "DQLL1_0_P" 26\r
+# LOCATE COMP "SFP_MOD0_4" SITE "Y1";\r
+# LOCATE COMP "SFP_MOD1_4" SITE "W4"; #was "DQLL1_1_P" 30\r
+# LOCATE COMP "SFP_MOD2_4" SITE "W3";\r
+# LOCATE COMP "SFP_RATESEL_4" SITE "W2"; #was "DQLL1_2_P" 34\r
+# LOCATE COMP "SFP_TXDIS_4" SITE "W1";\r
+# LOCATE COMP "SFP_LOS_4" SITE "W6"; #was "DQSLL1_T" 38\r
+# LOCATE COMP "SFP_TXFAULT_4" SITE "Y6";\r
+\r
+# LOCATE COMP "DQLL1_3" SITE "W8"; #was "DQLL1_3_P" 42\r
+# LOCATE COMP "DQLL1_3" SITE "W9";\r
+# LOCATE COMP "DQLL1_4" SITE "Y8"; #was "DQLL1_4_P" 46\r
+# LOCATE COMP "DQLL1_4" SITE "AA8";\r
+\r
+# LOCATE COMP "DQUL2_0" SITE "F2"; #was "DQUL2_0_P" 50\r
+# LOCATE COMP "DQUL2_0" SITE "F1";;\r
+# LOCATE COMP "DQUL2_1" SITE "F3"; #was "DQUL2_1_P" 54\r
+# LOCATE COMP "DQUL2_1" SITE "E3";\r
+# LOCATE COMP "DQUL2_2" SITE "G2"; #was "DQUL2_2_P" 58\r
+# LOCATE COMP "DQUL2_2" SITE "G1";\r
+# LOCATE COMP "DQSUL2" SITE "G3"; #was "DQSUL2_T" 62\r
+# LOCATE COMP "DQSUL2" SITE "H3";;\r
+# LOCATE COMP "DQUL2_3" SITE "H1"; #was "DQUL2_3_P" 66\r
+# LOCATE COMP "DQUL2_3" SITE "J1";\r
+# LOCATE COMP "DQUL2_4" SITE "J3"; #was "DQUL2_4_P" 70\r
+# LOCATE COMP "DQUL2_4" SITE "H2";\r
+\r
+# LOCATE COMP "DQUL0_0" SITE "L5"; #was "DQUL0_0_P" 74\r
+# LOCATE COMP "DQUL0_0" SITE "L4";;\r
+# LOCATE COMP "DQUL0_1" SITE "M4"; #was "DQUL0_1_P" 78\r
+# LOCATE COMP "DQUL0_1" SITE "M3";;\r
+# LOCATE COMP "DQUL0_2" SITE "K6"; #was "DQUL0_2_P" 82\r
+# LOCATE COMP "DQUL0_2" SITE "K5";;\r
+# LOCATE COMP "DQSUL0" SITE "N9"; #was "DQSUL0_T" 86\r
+# LOCATE COMP "DQSUL0" SITE "M9";;\r
+# LOCATE COMP "DQUL0_3" SITE "M2"; #was "DQUL0_3_P" 90\r
+# LOCATE COMP "DQUL0_3" SITE "M1";;\r
+# LOCATE COMP "DQUL0_4" SITE "M7"; #was "DQUL0_4_P" 94\r
+# LOCATE COMP "DQUL0_4" SITE "L6";;\r
+# \r
+# LOCATE COMP "DQUR1_0" SITE "N30"; #was "DQUR1_0_P" 106\r
+# LOCATE COMP "DQUR1_0" SITE "N29";\r
+# LOCATE COMP "DQUR1_1" SITE "N26"; #was "DQUR1_1_P" 110\r
+# LOCATE COMP "DQUR1_1" SITE "P26";\r
+# LOCATE COMP "DQUR1_2" SITE "N32"; #was "DQUR1_2_P" 114\r
+# LOCATE COMP "DQUR1_2" SITE "N31";\r
+# LOCATE COMP "DQSUR1" SITE "N27"; #was "DQSUR1_T" 118\r
+# LOCATE COMP "DQSUR1" SITE "N28";;\r
+# LOCATE COMP "DQUR1_3" SITE "N34"; #was "DQUR1_3_P" 122\r
+# LOCATE COMP "DQUR1_3" SITE "N33";\r
+# LOCATE COMP "DQUR1_4" SITE "P28"; #was "DQUR1_4_P" 126\r
+# LOCATE COMP "DQUR1_4" SITE "P27";\r
+\r
+# LOCATE COMP "DQUR2_0" SITE "T32"; #was "DQUR2_0_P" 130\r
+# LOCATE COMP "DQUR2_0" SITE "T31";;\r
+# LOCATE COMP "DQUR2_1" SITE "T26"; #was "DQUR2_1_P" 134\r
+# LOCATE COMP "DQUR2_1" SITE "T27";;\r
+# LOCATE COMP "DQUR2_2" SITE "U32"; #was "DQUR2_2_P" 138\r
+# LOCATE COMP "DQUR2_2" SITE "U31";;\r
+# LOCATE COMP "DQSUR2" SITE "T30"; #was "DQSUR2_T" 142\r
+# LOCATE COMP "DQSUR2" SITE "U30";;\r
+# LOCATE COMP "DQUR2_3" SITE "T34"; #was "DQUR2_3_P" 146\r
+# LOCATE COMP "DQUR2_3" SITE "T33";;\r
+# LOCATE COMP "DQUR2_4" SITE "U26"; #was "DQUR2_4_P" 150\r
+# LOCATE COMP "DQUR2_4" SITE "U27";\r
+# \r
+# LOCATE COMP "LED_LINKOK_6" SITE "W30"; #was "DQLR2_0_P" 170\r
+# LOCATE COMP "LED_RX_6" SITE "W29";\r
+# LOCATE COMP "LED_TX_6" SITE "W27"; #was "DQLR2_1_P" 174\r
+# LOCATE COMP "SFP_MOD0_6" SITE "W26";\r
+# LOCATE COMP "SFP_MOD1_6" SITE "W34"; #was "DQLR2_2_P" 178\r
+# LOCATE COMP "SFP_MOD2_6" SITE "W33";;\r
+# LOCATE COMP "SFP_RATESEL_6" SITE "Y30"; #was "DQSLR2_T" 182\r
+# LOCATE COMP "SFP_TXDIS_6" SITE "AA29";\r
+# LOCATE COMP "SFP_LOS_6" SITE "Y34"; #was "DQLR2_3_P" 186\r
+# LOCATE COMP "SFP_TXFAULT_6" SITE "Y33";;\r
+\r
+\r
+\r
+\r
+\r
LOCATE COMP "2V_IO_PCSA" SITE "AF18";\r
LOCATE COMP "2V_IO_PCSA" SITE "AF19";\r
LOCATE COMP "2V_IO_PCSA" SITE "AF20";\r
--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_components.all;
+ use work.trb_net_std.all;
+ use work.config.all;
+
+entity pulser is
+ generic(
+ CHANNELNUM : integer := 30
+ );
+ port(
+ SYSCLK : in std_logic;
+ CLK_FAST_LEFT : in std_logic;
+ CLK_FAST_RIGHT : in std_logic;
+
+ RESET : in std_logic;
+
+ --Slowcontrol
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ --AddOn Connector
+ OUTP : out std_logic_vector(16 downto 1);
+ OUTP_FAN : out std_logic_vector(3 downto 0);
+ OUTP_ANA : out std_logic_vector(9 downto 0);
+
+ INP : in std_logic_vector(3 downto 0);
+
+ SEL1 : out std_logic_vector(3 downto 0);
+ SEL2 : out std_logic_vector(3 downto 0);
+ SELO1 : out std_logic_vector(1 downto 0);
+ SELO2 : out std_logic_vector(1 downto 0);
+
+
+ TRIG : out std_logic;
+
+ LED_PULSER : out std_logic_vector(4 downto 0);
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+--OUTP 80pin, first 16 pairs
+--OUTP_FAN(0): 80pin, 17-31, odd lines
+--OUTP_FAN(1): 80pin, 18-32, even lines
+--OUTP_FAN(2): 34pin, odd lines
+--OUTP_FAN(3): 34pin, even lines
+--OUTP_ANA(0-4): Analog1 - 390,470,820,1800,6800 Ohm
+--OUTP_ANA(5-9): Analog2 - 390,470,820,1800,6800 Ohm
+--SEL1/2 : Analog1/2 39,56,68,82 pF
+
+--Pulsers: 0 - 15: OUTP, 16 - 19: OUTP_FAN, 20 - 29: OUTP_ANA
+
+--0x00 Pulser enable
+--0x01 Pulser invert
+--0x10 Pulser control strobe
+
+--0x40 - 0x41 Analog configuration (Bit0-4: SEL, Bit 8-9 SELO
+
+--0x80 - 0x9f pulser period, 5 ns
+--0xa0 - 0xbf pulse length, 1.25 ns (only multiples of 5ns supported)
+--0xc0 - 0xdf pulser offset, 5 ns
+
+
+architecture pulser_arch of pulser is
+
+signal clk_slow_left, clk_slow_right : std_logic;
+
+type arr_32unsigned_t is array(0 to 31) of unsigned(31 downto 0);
+
+signal period : arr_32unsigned_t;
+signal length : arr_32unsigned_t;
+signal offset : arr_32unsigned_t;
+signal timer : arr_32unsigned_t;
+
+signal ana1_in_select, ana2_in_select : std_logic_vector(3 downto 0);
+signal ana1_out_select, ana2_out_select: std_logic_vector(1 downto 0);
+signal control_strobes : std_logic_vector(31 downto 0);
+signal pulser_enable : std_logic_vector(31 downto 0);
+signal pulser_invert : std_logic_vector(31 downto 0);
+signal pulser_reset : std_logic;
+
+-- type pulse_ddr_t is array(0 to 31) of std_logic_vector(3 downto 0);
+-- signal pulse : pulse_ddr_t;
+
+type dleft_t is array(0 to 3) of std_logic_vector(19 downto 0);
+type dright_t is array(0 to 3) of std_logic_vector(9 downto 0);
+signal data_left : dleft_t;
+signal data_right : dright_t;
+
+
+begin
+
+
+
+
+multi_ch_pulser_left : for n in 0 to 19 generate
+ pulser : entity work.single_channel_pulser
+ port map (
+ CLK => clk_slow_left,
+ RESET => pulser_reset,
+ FREQUENCY => period(n)(23 downto 0),
+ PULSE_WIDTH => length(n)(23 downto 0),
+ OFFSET => offset(n)(23 downto 0),
+ INVERT => pulser_invert(n),
+ PULSE(0) => data_left(0)(n),
+ PULSE(1) => data_left(1)(n),
+ PULSE(2) => data_left(2)(n),
+ PULSE(3) => data_left(3)(n)
+ );
+end generate;
+
+
+multi_ch_pulser_right : for n in 0 to 9 generate
+ pulser : entity work.single_channel_pulser
+ port map (
+ CLK => clk_slow_right,
+ RESET => pulser_reset,
+ FREQUENCY => period(n+20)(23 downto 0),
+ PULSE_WIDTH => length(n+20)(23 downto 0),
+ OFFSET => offset(n+20)(23 downto 0),
+ INVERT => pulser_invert(n+20),
+ PULSE(0) => data_right(0)(n),
+ PULSE(1) => data_right(1)(n),
+ PULSE(2) => data_right(2)(n),
+ PULSE(3) => data_right(3)(n)
+ );
+end generate;
+
+
+
+-- gen_outp : for n in 0 to 15 generate
+-- OUTP(n+1) <= data_left(0)(n);
+-- end generate;
+--
+-- gen_outp_fan : for n in 0 to 3 generate
+-- OUTP_FAN(n) <= data_left(0)(n+16);
+-- end generate;
+
+-- gen_outp_ana : for n in 0 to 9 generate
+-- OUTP_ANA(n) <= pulse(n+20)(0);
+-- end generate;
+
+THE_LEFT_DDR : entity work.ddr_20
+ port map(
+ clk => CLK_FAST_LEFT,
+ pll_lock => open,
+ pll_reset => '0',
+ reset => '0',
+ sclk => clk_slow_left,
+ da0 => data_left(0),
+ da1 => data_left(1),
+ db0 => data_left(2),
+ db1 => data_left(3),
+ q(15 downto 0) => OUTP(16 downto 1),
+ q(19 downto 16) => OUTP_FAN(3 downto 0)
+ );
+
+
+THE_RIGHT_DDR : entity work.ddr_10
+ port map(
+ clk => CLK_FAST_RIGHT,
+ pll_lock => open,
+ pll_reset => '0',
+ reset => '0',
+ sclk => clk_slow_right,
+ da0 => data_right(0),
+ da1 => data_right(1),
+ db0 => data_right(2),
+ db1 => data_right(3),
+ q => OUTP_ANA
+ );
+
+
+
+
+-------------------------------------------------
+-- Control Bus
+-------------------------------------------------
+
+
+ proc_ctrlbus : process begin
+ wait until rising_edge(SYSCLK);
+ BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; BUS_TX.unknown <= '0';
+ control_strobes <= (others => '0');
+ pulser_reset <= RESET;
+
+ if BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(7 downto 5) = "100" then
+ BUS_TX.data <= std_logic_vector(period(to_integer(unsigned(BUS_RX.addr(4 downto 0)))));
+ elsif BUS_RX.addr(7 downto 5) = "101" then
+ BUS_TX.data <= std_logic_vector(length(to_integer(unsigned(BUS_RX.addr(4 downto 0)))));
+ elsif BUS_RX.addr(7 downto 5) = "110" then
+ BUS_TX.data <= std_logic_vector(offset(to_integer(unsigned(BUS_RX.addr(4 downto 0)))));
+ elsif BUS_RX.addr(7 downto 0) = x"00" then
+ BUS_TX.data <= pulser_enable;
+ elsif BUS_RX.addr(7 downto 0) = x"01" then
+ BUS_TX.data <= pulser_invert;
+ elsif BUS_RX.addr(7 downto 0) = x"40" then
+ BUS_TX.data(3 downto 0) <= ana1_in_select ;
+ BUS_TX.data(9 downto 8) <= ana1_out_select;
+ elsif BUS_RX.addr(7 downto 0) = x"41" then
+ BUS_TX.data(3 downto 0) <= ana2_in_select ;
+ BUS_TX.data(9 downto 8) <= ana2_out_select;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+
+ elsif BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(7 downto 5) = "100" then
+ period(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
+ pulser_reset <= '1';
+ elsif BUS_RX.addr(7 downto 5) = "101" then
+ length(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
+ pulser_reset <= '1';
+ elsif BUS_RX.addr(7 downto 5) = "110" then
+ offset(to_integer(unsigned(BUS_RX.addr(4 downto 0)))) <= unsigned(BUS_RX.data);
+ pulser_reset <= '1';
+ elsif BUS_RX.addr(7 downto 0) = x"00" then
+ pulser_enable <= BUS_RX.data;
+ elsif BUS_RX.addr(7 downto 0) = x"01" then
+ pulser_invert <= BUS_RX.data;
+ elsif BUS_RX.addr(7 downto 0) = x"10" then
+ control_strobes <= BUS_RX.data;
+ pulser_reset <= BUS_RX.data(0);
+ elsif BUS_RX.addr(7 downto 0) = x"40" then
+ ana1_in_select <= BUS_RX.data(3 downto 0);
+ ana1_out_select <= BUS_RX.data(9 downto 8);
+ elsif BUS_RX.addr(7 downto 0) = x"41" then
+ ana2_in_select <= BUS_RX.data(3 downto 0);
+ ana2_out_select <= BUS_RX.data(9 downto 8);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ end if;
+
+ end process;
+
+
+-------------------------------------------------
+-- Control Lines
+-------------------------------------------------
+ SEL1 <= ana1_in_select;
+ SEL2 <= ana2_in_select;
+ SELO1 <= ana1_out_select;
+ SELO2 <= ana2_out_select;
+
+
+-------------------------------------------------
+-- LED
+-------------------------------------------------
+ --all LED are inverted D2-D6
+ LED_PULSER(0) <= '0'; --next to 34-pin
+ LED_PULSER(1) <= '0'; --next to KEL-80
+ LED_PULSER(2) <= '0'; --Analog 1
+ LED_PULSER(3) <= '0'; --Analog 2
+ LED_PULSER(4) <= '1'; --SPI active
+
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+---------------------------------------------------------------------------------------------------------------\r
+--Implementation of a pulse generator, with single channel output.\r
+---------------------------------------------------------------------------------------------------------------\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+\r
+entity single_channel_pulser is\r
+ \r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ FREQUENCY : in unsigned(23 downto 0);\r
+ PULSE_WIDTH : in unsigned(23 downto 0);\r
+ OFFSET : in unsigned(23 downto 0);\r
+ INVERT : in std_logic;\r
+ PULSE : out std_logic_vector(3 downto 0)\r
+ );\r
+ \r
+end entity;\r
+ \r
+architecture single_channel_pulser_arch of single_channel_pulser is\r
+\r
+signal timer : unsigned(23 downto 0) := (others => '0'); \r
+signal last_timer : unsigned(23 downto 0) := (others => '0'); \r
+signal reset_counter : std_logic;\r
+signal frequency_i : unsigned(23 downto 0); \r
+signal reset_delay : std_logic;\r
+signal pulse_width_i : unsigned(23 downto 0);\r
+\r
+type state_type is (idle, generate_pulse, finish);\r
+signal state : state_type;\r
+\r
+\r
+begin\r
+\r
+ PROC_TIMER : process (CLK) --it counts \r
+ begin\r
+ if rising_edge(CLK) then\r
+ if reset_counter = '1' then \r
+ timer <= (others => '0') after 1 ns; \r
+ else \r
+ timer <= timer+1 after 1 ns;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ PROC_FREQUENCY : process (CLK) --It eliminates the offset of -2 for the frequency \r
+ begin\r
+ if rising_edge(CLK) then\r
+ if FREQUENCY >= x"000002" then\r
+ frequency_i <= FREQUENCY-2 after 1 ns;\r
+ end if;\r
+ reset_delay <= RESET; --I want the timer to start again after the operations with the frequency\r
+ end if;\r
+ end process;\r
+\r
+\r
+ PROC_RESET_COUNTER: process (CLK) --it resets (reset_counter active high) when timer=FREQUENCY or reset_delay=1 or the FF change \r
+ begin\r
+ if rising_edge(CLK) then\r
+ if reset_delay = '1' or last_timer = frequency_i or RESET = '1' then --was FREQUENCY\r
+ reset_counter <= '1' after 1 ns;\r
+ else\r
+ reset_counter <= '0' after 1 ns;\r
+ end if; \r
+ end if;\r
+ end process;\r
+ \r
+ \r
+last_timer <= timer when rising_edge(CLK); \r
+ \r
+ PROC_PULSE_MANAGER : process(CLK) \r
+ begin \r
+ if RESET = '1' then \r
+ state <= idle; \r
+ \r
+ elsif rising_edge(CLK) then\r
+ \r
+ case state is\r
+ \r
+ when idle => \r
+ PULSE <= "0000";\r
+ pulse_width_i <= PULSE_WIDTH;\r
+ \r
+ if last_timer = x"000000" then\r
+ state <= generate_pulse;\r
+ end if;\r
+ \r
+ when generate_pulse =>\r
+ if pulse_width_i = x"000002" then \r
+ PULSE <= "0011" after 1 ns;\r
+ elsif pulse_width_i = x"000003" then \r
+ PULSE <= "0111" after 1 ns;\r
+ elsif pulse_width_i >= x"000004" then \r
+ PULSE <= "1111" after 1 ns; \r
+ else \r
+ PULSE <= "0001";\r
+ end if;\r
+ pulse_width_i <= pulse_width_i-4;\r
+ \r
+ if pulse_width_i <= 4 then\r
+ state <= finish;\r
+ else \r
+ state <= generate_pulse;\r
+ end if;\r
+ \r
+ when finish =>\r
+ state <= idle;\r
+ PULSE <= "0000";\r
+\r
+ end case;\r
+ \r
+ end if; \r
+ \r
+ \r
+\r
+ end process;\r
+ \r
+\r
+end architecture;\r
+\r
+
\ No newline at end of file
--Address settings
constant INIT_ADDRESS : std_logic_vector := x"F3CC";
- constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61";
constant INCLUDE_UART : integer := c_YES;
-TOPNAME => "trb3sc_basic",
+TOPNAME => "trb3sc_pulser",
lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.4_x64',
+lattice_path => '/d/jspc29/lattice/diamond/3.5_x64',
synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options",
+synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
nodelist_file => 'nodelist_frankfurt.txt',
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ddr_10" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 03 12:59:08.310" version="5.4" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="ddr_10.lpc" type="lpc" modified="2015 07 03 12:58:57.000"/>
+ <File name="ddr_10.vhd" type="top_level_vhdl" modified="2015 07 03 12:58:57.000"/>
+ <File name="ddr_10_tmpl.vhd" type="template_vhdl" modified="2015 07 03 12:58:57.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=5.4
+ModuleName=ddr_10
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/03/2015
+Time=12:58:57
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Transmit
+trioddr=0
+io_type=LVDS25
+num_int=1
+width=10
+freq_in=480
+bandwidth=9600
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Transmit
+trioddr2=0
+io_type2=LVDS25
+freq_in2=480
+gear=2x
+aligned2=Edge-to-Edge
+num_int2=1
+width2=10
+Interface=GDDRX2_TX.Aligned
+Delay=
+Number=
+dqs1=
+dqs2=
+dqs3=
+dqs4=
+dqs5=
+dqs6=
+dqs7=
+dqs8=
+val=Bypass
+Phase=TRDLLB/DLLDELB
+Divider=CLKDIVB
+Multiplier=2
+PllFreq=240
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94)
+-- Module Version: 5.4
+--/d/jspc29/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n ddr_10 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 10 -freq_in 480 -gear 2 -clk eclk -aligned -num_clk 2 -e
+
+-- Fri Jul 3 12:58:57 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ddr_10 is
+ port (
+ clk: in std_logic;
+ pll_lock: out std_logic;
+ pll_reset: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ da0: in std_logic_vector(9 downto 0);
+ da1: in std_logic_vector(9 downto 0);
+ db0: in std_logic_vector(9 downto 0);
+ db1: in std_logic_vector(9 downto 0);
+ q: out std_logic_vector(9 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr_10 : entity is true;
+end ddr_10;
+
+architecture Structure of ddr_10 is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal dqclk12: std_logic;
+ signal dqclk02: std_logic;
+ signal dqclk11: std_logic;
+ signal dqclk01: std_logic;
+ signal dqclk10: std_logic;
+ signal dqclk00: std_logic;
+ signal cdiv8: std_logic;
+ signal cdiv4: std_logic;
+ signal cdiv1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal eclk: std_logic;
+ signal reset_d2: std_logic;
+ signal reset_d1: std_logic;
+ signal clkok2: std_logic;
+ signal clkok: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal scuba_vlo: std_logic;
+ signal clkintfb: std_logic;
+ signal buf_qo9: std_logic;
+ signal buf_qo8: std_logic;
+ signal buf_qo7: std_logic;
+ signal buf_qo6: std_logic;
+ signal buf_qo5: std_logic;
+ signal buf_qo4: std_logic;
+ signal buf_qo3: std_logic;
+ signal buf_qo2: std_logic;
+ signal buf_qo1: std_logic;
+ signal buf_qo0: std_logic;
+ signal sclk_t: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RST: in std_logic; RSTK: in std_logic;
+ WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic;
+ DRPAI0: in std_logic; DFPAI3: in std_logic;
+ DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic;
+ FDA2: in std_logic; FDA1: in std_logic;
+ FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic;
+ CLKOK2: out std_logic; LOCK: out std_logic;
+ CLKINTFB: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component CLKDIVB
+ port (CLKI: in std_logic; RST: in std_logic;
+ RELEASE: in std_logic; CDIV1: out std_logic;
+ CDIV2: out std_logic; CDIV4: out std_logic;
+ CDIV8: out std_logic);
+ end component;
+ component ODDRX2D
+ generic (MEMMODE : in String; ISI_CAL : in String);
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; SCLK: in std_logic;
+ DQCLK1: in std_logic; DQCLK0: in std_logic;
+ Q: out std_logic);
+ end component;
+ component DQSBUFE1
+ generic (DYNDEL_CNTL : in String; DYNDEL_VAL : in Integer;
+ DYNDEL_TYPE : in String);
+ port (ECLKW: in std_logic; RST: in std_logic;
+ DYNDELPOL: in std_logic; DYNDELAY6: in std_logic;
+ DYNDELAY5: in std_logic; DYNDELAY4: in std_logic;
+ DYNDELAY3: in std_logic; DYNDELAY2: in std_logic;
+ DYNDELAY1: in std_logic; DYNDELAY0: in std_logic;
+ DQCLK0: out std_logic; DQCLK1: out std_logic);
+ end component;
+ component ECLKSYNCA
+ port (ECLKI: in std_logic; STOP: in std_logic;
+ ECLKO: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst9_OB : label is "LVDS25";
+ attribute ODDRAPPS of Inst8_ODDRX2D : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED";
+ attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "240.000000";
+ attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "240.000000";
+ attribute IO_TYPE of Inst1_OB9 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB8 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS25";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst9_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst_ODDRX2D_1_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(9), DB0=>db0(9), DA1=>da1(9), DB1=>db1(9),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo9);
+
+ Inst_ODDRX2D_1_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(8), DB0=>db0(8), DA1=>da1(8), DB1=>db1(8),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo8);
+
+ Inst_ODDRX2D_1_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(7), DB0=>db0(7), DA1=>da1(7), DB1=>db1(7),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo7);
+
+ Inst_ODDRX2D_1_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(6), DB0=>db0(6), DA1=>da1(6), DB1=>db1(6),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo6);
+
+ Inst_ODDRX2D_1_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(5), DB0=>db0(5), DA1=>da1(5), DB1=>db1(5),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo5);
+
+ Inst_ODDRX2D_0_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(4), DB0=>db0(4), DA1=>da1(4), DB1=>db1(4),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo4);
+
+ Inst_ODDRX2D_0_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(3), DB0=>db0(3), DA1=>da1(3), DB1=>db1(3),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo3);
+
+ Inst_ODDRX2D_0_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(2), DB0=>db0(2), DA1=>da1(2), DB1=>db1(2),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo2);
+
+ Inst_ODDRX2D_0_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(1), DB0=>db0(1), DA1=>da1(1), DB1=>db1(1),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1);
+
+ Inst_ODDRX2D_0_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(0), DB0=>db0(0), DA1=>da1(0), DB1=>db1(0),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0);
+
+
+ Inst7_DQSBUFE13: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+
+ Inst7_DQSBUFE12: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+ Inst7_DQSBUFE11: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+ Inst7_DQSBUFE10: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst6_CLKDIVB: CLKDIVB
+ port map (CLKI=>eclk, RST=>reset, RELEASE=>scuba_vhi,
+ CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+ Inst5_ECLKSYNCA: ECLKSYNCA
+ port map (ECLKI=>clkop, STOP=>reset_d2, ECLKO=>eclk);
+
+ Inst4_FD1S3BX: FD1S3BX
+ port map (D=>reset_d1, CK=>clkok, PD=>reset, Q=>reset_d2);
+
+ Inst3_FD1S3BX: FD1S3BX
+ port map (D=>reset, CK=>clkok, PD=>reset, Q=>reset_d1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst2_EHXPLLF: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOS", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FIN=> "240.000000")
+ port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>clkop, CLKOS=>clkos,
+ CLKOK=>clkok, CLKOK2=>clkok2, LOCK=>pll_lock,
+ CLKINTFB=>clkintfb);
+
+ Inst1_OB9: OB
+ port map (I=>buf_qo9, O=>q(9));
+
+ Inst1_OB8: OB
+ port map (I=>buf_qo8, O=>q(8));
+
+ Inst1_OB7: OB
+ port map (I=>buf_qo7, O=>q(7));
+
+ Inst1_OB6: OB
+ port map (I=>buf_qo6, O=>q(6));
+
+ Inst1_OB5: OB
+ port map (I=>buf_qo5, O=>q(5));
+
+ Inst1_OB4: OB
+ port map (I=>buf_qo4, O=>q(4));
+
+ Inst1_OB3: OB
+ port map (I=>buf_qo3, O=>q(3));
+
+ Inst1_OB2: OB
+ port map (I=>buf_qo2, O=>q(2));
+
+ Inst1_OB1: OB
+ port map (I=>buf_qo1, O=>q(1));
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ddr_10 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+ for all:ODDRX2D use entity ecp3.ODDRX2D(V); end for;
+ for all:DQSBUFE1 use entity ecp3.DQSBUFE1(V); end for;
+ for all:ECLKSYNCA use entity ecp3.ECLKSYNCA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94)
+-- Module Version: 5.4
+--/d/jspc29/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n ddr_10 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 10 -freq_in 480 -gear 2 -clk eclk -aligned -num_clk 2 -e
+
+-- Fri Jul 3 12:58:57 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ddr_10 is
+ port (
+ clk: in std_logic;
+ pll_lock: out std_logic;
+ pll_reset: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ da0: in std_logic_vector(9 downto 0);
+ da1: in std_logic_vector(9 downto 0);
+ db0: in std_logic_vector(9 downto 0);
+ db1: in std_logic_vector(9 downto 0);
+ q: out std_logic_vector(9 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr_10 : entity is true;
+end ddr_10;
+
+architecture Structure of ddr_10 is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal dqclk13: std_logic;
+ signal dqclk03: std_logic;
+ signal dqclk12: std_logic;
+ signal dqclk02: std_logic;
+ signal dqclk11: std_logic;
+ signal dqclk01: std_logic;
+ signal dqclk10: std_logic;
+ signal dqclk00: std_logic;
+ signal cdiv8: std_logic;
+ signal cdiv4: std_logic;
+ signal cdiv1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal eclk: std_logic;
+ signal reset_d2: std_logic;
+ signal reset_d1: std_logic;
+ signal clkok2: std_logic;
+ signal clkok: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal scuba_vlo: std_logic;
+ signal clkintfb: std_logic;
+ signal buf_qo9: std_logic;
+ signal buf_qo8: std_logic;
+ signal buf_qo7: std_logic;
+ signal buf_qo6: std_logic;
+ signal buf_qo5: std_logic;
+ signal buf_qo4: std_logic;
+ signal buf_qo3: std_logic;
+ signal buf_qo2: std_logic;
+ signal buf_qo1: std_logic;
+ signal buf_qo0: std_logic;
+ signal sclk_t: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RST: in std_logic; RSTK: in std_logic;
+ WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic;
+ DRPAI0: in std_logic; DFPAI3: in std_logic;
+ DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic;
+ FDA2: in std_logic; FDA1: in std_logic;
+ FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic;
+ CLKOK2: out std_logic; LOCK: out std_logic;
+ CLKINTFB: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component CLKDIVB
+ port (CLKI: in std_logic; RST: in std_logic;
+ RELEASE: in std_logic; CDIV1: out std_logic;
+ CDIV2: out std_logic; CDIV4: out std_logic;
+ CDIV8: out std_logic);
+ end component;
+ component ODDRX2D
+ generic (MEMMODE : in String; ISI_CAL : in String);
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; SCLK: in std_logic;
+ DQCLK1: in std_logic; DQCLK0: in std_logic;
+ Q: out std_logic);
+ end component;
+ component DQSBUFE1
+ generic (DYNDEL_CNTL : in String; DYNDEL_VAL : in Integer;
+ DYNDEL_TYPE : in String);
+ port (ECLKW: in std_logic; RST: in std_logic;
+ DYNDELPOL: in std_logic; DYNDELAY6: in std_logic;
+ DYNDELAY5: in std_logic; DYNDELAY4: in std_logic;
+ DYNDELAY3: in std_logic; DYNDELAY2: in std_logic;
+ DYNDELAY1: in std_logic; DYNDELAY0: in std_logic;
+ DQCLK0: out std_logic; DQCLK1: out std_logic);
+ end component;
+ component ECLKSYNCA
+ port (ECLKI: in std_logic; STOP: in std_logic;
+ ECLKO: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute IO_TYPE : string;
+ attribute ODDRAPPS of Inst_ODDRX2D_1_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED";
+ attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "240.000000";
+ attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "240.000000";
+ attribute IO_TYPE of Inst1_OB9 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB8 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS25";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst_ODDRX2D_1_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(9), DB0=>db0(9), DA1=>da1(9), DB1=>db1(9),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo9);
+
+ Inst_ODDRX2D_1_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(8), DB0=>db0(8), DA1=>da1(8), DB1=>db1(8),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo8);
+
+ Inst_ODDRX2D_1_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(7), DB0=>db0(7), DA1=>da1(7), DB1=>db1(7),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo7);
+
+ Inst_ODDRX2D_1_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(6), DB0=>db0(6), DA1=>da1(6), DB1=>db1(6),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo6);
+
+ Inst_ODDRX2D_1_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(5), DB0=>db0(5), DA1=>da1(5), DB1=>db1(5),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo5);
+
+ Inst_ODDRX2D_0_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(4), DB0=>db0(4), DA1=>da1(4), DB1=>db1(4),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo4);
+
+ Inst_ODDRX2D_0_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(3), DB0=>db0(3), DA1=>da1(3), DB1=>db1(3),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo3);
+
+ Inst_ODDRX2D_0_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(2), DB0=>db0(2), DA1=>da1(2), DB1=>db1(2),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo2);
+
+ Inst_ODDRX2D_0_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(1), DB0=>db0(1), DA1=>da1(1), DB1=>db1(1),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1);
+
+ Inst_ODDRX2D_0_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(0), DB0=>db0(0), DA1=>da1(0), DB1=>db1(0),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0);
+
+
+ Inst7_DQSBUFE13: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+
+ Inst7_DQSBUFE12: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+ Inst7_DQSBUFE11: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+ Inst7_DQSBUFE10: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst6_CLKDIVB: CLKDIVB
+ port map (CLKI=>eclk, RST=>reset, RELEASE=>scuba_vhi,
+ CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+ Inst5_ECLKSYNCA: ECLKSYNCA
+ port map (ECLKI=>clkop, STOP=>reset_d2, ECLKO=>eclk);
+
+ Inst4_FD1S3BX: FD1S3BX
+ port map (D=>reset_d1, CK=>clkok, PD=>reset, Q=>reset_d2);
+
+ Inst3_FD1S3BX: FD1S3BX
+ port map (D=>reset, CK=>clkok, PD=>reset, Q=>reset_d1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst2_EHXPLLF: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOS", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FIN=> "240.000000")
+ port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>clkop, CLKOS=>clkos,
+ CLKOK=>clkok, CLKOK2=>clkok2, LOCK=>pll_lock,
+ CLKINTFB=>clkintfb);
+
+ Inst1_OB9: OB
+ port map (I=>buf_qo9, O=>q(9));
+
+ Inst1_OB8: OB
+ port map (I=>buf_qo8, O=>q(8));
+
+ Inst1_OB7: OB
+ port map (I=>buf_qo7, O=>q(7));
+
+ Inst1_OB6: OB
+ port map (I=>buf_qo6, O=>q(6));
+
+ Inst1_OB5: OB
+ port map (I=>buf_qo5, O=>q(5));
+
+ Inst1_OB4: OB
+ port map (I=>buf_qo4, O=>q(4));
+
+ Inst1_OB3: OB
+ port map (I=>buf_qo3, O=>q(3));
+
+ Inst1_OB2: OB
+ port map (I=>buf_qo2, O=>q(2));
+
+ Inst1_OB1: OB
+ port map (I=>buf_qo1, O=>q(1));
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ddr_10 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+ for all:ODDRX2D use entity ecp3.ODDRX2D(V); end for;
+ for all:DQSBUFE1 use entity ecp3.DQSBUFE1(V); end for;
+ for all:ECLKSYNCA use entity ecp3.ECLKSYNCA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ddr_20" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 03 11:01:27.886" version="6.0" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="ddr_20.lpc" type="lpc" modified="2015 07 03 11:01:17.000"/>
+ <File name="ddr_20.vhd" type="top_level_vhdl" modified="2015 07 03 11:01:17.000"/>
+ <File name="ddr_20_tmpl.vhd" type="template_vhdl" modified="2015 07 03 11:01:17.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=ddr_20
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/03/2015
+Time=11:01:17
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Transmit
+trioddr=0
+io_type=LVDS25
+num_int=1
+width=20
+freq_in=480
+bandwidth=19200
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Transmit
+trioddr2=0
+io_type2=LVDS25
+freq_in2=480
+gear=2x
+aligned2=Edge-to-Edge
+num_int2=1
+width2=20
+Interface=GDDRX2_TX.Aligned
+Delay=
+Number=
+dqs1=
+dqs2=
+dqs3=
+dqs4=
+dqs5=
+dqs6=
+dqs7=
+dqs8=
+val=Bypass
+Phase=TRDLLB/DLLDELB
+Divider=CLKDIVB
+Multiplier=2
+PllFreq=240
+
+[Command]
+cmd_line= -w -n ddr_20 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 20 -freq_in 480 -gear 2 -clk eclk -aligned -num_clk 2
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n ddr_20 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 20 -freq_in 480 -gear 2 -clk eclk -aligned -num_clk 2
+
+-- Fri Jul 3 11:01:17 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ddr_20 is
+ port (
+ clk: in std_logic;
+ clkout: out std_logic;
+ pll_lock: out std_logic;
+ pll_reset: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ da0: in std_logic_vector(19 downto 0);
+ da1: in std_logic_vector(19 downto 0);
+ db0: in std_logic_vector(19 downto 0);
+ db1: in std_logic_vector(19 downto 0);
+ q: out std_logic_vector(19 downto 0));
+end ddr_20;
+
+architecture Structure of ddr_20 is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal dqclk14: std_logic;
+ signal dqclk04: std_logic;
+ signal dqclk13: std_logic;
+ signal dqclk03: std_logic;
+ signal dqclk12: std_logic;
+ signal dqclk02: std_logic;
+ signal dqclk11: std_logic;
+ signal dqclk01: std_logic;
+ signal dqclk10: std_logic;
+ signal dqclk00: std_logic;
+ signal cdiv8: std_logic;
+ signal cdiv4: std_logic;
+ signal cdiv1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal eclk: std_logic;
+ signal reset_d2: std_logic;
+ signal reset_d1: std_logic;
+ signal clkok2: std_logic;
+ signal clkok: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal scuba_vlo: std_logic;
+ signal clkintfb: std_logic;
+ signal buf_qo19: std_logic;
+ signal buf_qo18: std_logic;
+ signal buf_qo17: std_logic;
+ signal buf_qo16: std_logic;
+ signal buf_qo15: std_logic;
+ signal buf_qo14: std_logic;
+ signal buf_qo13: std_logic;
+ signal buf_qo12: std_logic;
+ signal buf_qo11: std_logic;
+ signal buf_qo10: std_logic;
+ signal buf_qo9: std_logic;
+ signal buf_qo8: std_logic;
+ signal buf_qo7: std_logic;
+ signal buf_qo6: std_logic;
+ signal buf_qo5: std_logic;
+ signal buf_qo4: std_logic;
+ signal buf_qo3: std_logic;
+ signal buf_qo2: std_logic;
+ signal buf_qo1: std_logic;
+ signal buf_qo0: std_logic;
+ signal sclk_t: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RST: in std_logic; RSTK: in std_logic;
+ WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic;
+ DRPAI0: in std_logic; DFPAI3: in std_logic;
+ DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic;
+ FDA2: in std_logic; FDA1: in std_logic;
+ FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic;
+ CLKOK2: out std_logic; LOCK: out std_logic;
+ CLKINTFB: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component CLKDIVB
+ port (CLKI: in std_logic; RST: in std_logic;
+ RELEASE: in std_logic; CDIV1: out std_logic;
+ CDIV2: out std_logic; CDIV4: out std_logic;
+ CDIV8: out std_logic);
+ end component;
+ component ODDRX2D
+ generic (MEMMODE : in String; ISI_CAL : in String);
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; SCLK: in std_logic;
+ DQCLK1: in std_logic; DQCLK0: in std_logic;
+ Q: out std_logic);
+ end component;
+ component DQSBUFE1
+ generic (DYNDEL_CNTL : in String; DYNDEL_VAL : in Integer;
+ DYNDEL_TYPE : in String);
+ port (ECLKW: in std_logic; RST: in std_logic;
+ DYNDELPOL: in std_logic; DYNDELAY6: in std_logic;
+ DYNDELAY5: in std_logic; DYNDELAY4: in std_logic;
+ DYNDELAY3: in std_logic; DYNDELAY2: in std_logic;
+ DYNDELAY1: in std_logic; DYNDELAY0: in std_logic;
+ DQCLK0: out std_logic; DQCLK1: out std_logic);
+ end component;
+ component ECLKSYNCA
+ port (ECLKI: in std_logic; STOP: in std_logic;
+ ECLKO: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst9_OB : label is "LVDS25";
+ attribute ODDRAPPS of Inst8_ODDRX2D : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED";
+ attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "240.000000";
+ attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "240.000000";
+ attribute IO_TYPE of Inst1_OB19 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB18 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB17 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB16 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB15 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB14 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB13 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB12 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB11 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB10 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB9 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB8 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS25";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst9_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst8_ODDRX2D: ODDRX2D
+ generic map (ISI_CAL=> "BYPASS", MEMMODE=> "ENABLED")
+ port map (DA0=>scuba_vhi, DB0=>scuba_vlo, DA1=>scuba_vhi,
+ DB1=>scuba_vlo, SCLK=>sclk_t, DQCLK1=>dqclk14,
+ DQCLK0=>dqclk04, Q=>buf_clkout);
+
+ Inst_ODDRX2D_3_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(19), DB0=>db0(19), DA1=>da1(19), DB1=>db1(19),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo19);
+
+ Inst_ODDRX2D_3_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(18), DB0=>db0(18), DA1=>da1(18), DB1=>db1(18),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo18);
+
+ Inst_ODDRX2D_3_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(17), DB0=>db0(17), DA1=>da1(17), DB1=>db1(17),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo17);
+
+ Inst_ODDRX2D_3_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(16), DB0=>db0(16), DA1=>da1(16), DB1=>db1(16),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo16);
+
+ Inst_ODDRX2D_3_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(15), DB0=>db0(15), DA1=>da1(15), DB1=>db1(15),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo15);
+
+ Inst_ODDRX2D_2_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(14), DB0=>db0(14), DA1=>da1(14), DB1=>db1(14),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo14);
+
+ Inst_ODDRX2D_2_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(13), DB0=>db0(13), DA1=>da1(13), DB1=>db1(13),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo13);
+
+ Inst_ODDRX2D_2_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(12), DB0=>db0(12), DA1=>da1(12), DB1=>db1(12),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo12);
+
+ Inst_ODDRX2D_2_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(11), DB0=>db0(11), DA1=>da1(11), DB1=>db1(11),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo11);
+
+ Inst_ODDRX2D_2_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(10), DB0=>db0(10), DA1=>da1(10), DB1=>db1(10),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo10);
+
+ Inst_ODDRX2D_1_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(9), DB0=>db0(9), DA1=>da1(9), DB1=>db1(9),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo9);
+
+ Inst_ODDRX2D_1_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(8), DB0=>db0(8), DA1=>da1(8), DB1=>db1(8),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo8);
+
+ Inst_ODDRX2D_1_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(7), DB0=>db0(7), DA1=>da1(7), DB1=>db1(7),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo7);
+
+ Inst_ODDRX2D_1_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(6), DB0=>db0(6), DA1=>da1(6), DB1=>db1(6),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo6);
+
+ Inst_ODDRX2D_1_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(5), DB0=>db0(5), DA1=>da1(5), DB1=>db1(5),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo5);
+
+ Inst_ODDRX2D_0_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(4), DB0=>db0(4), DA1=>da1(4), DB1=>db1(4),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo4);
+
+ Inst_ODDRX2D_0_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(3), DB0=>db0(3), DA1=>da1(3), DB1=>db1(3),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo3);
+
+ Inst_ODDRX2D_0_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(2), DB0=>db0(2), DA1=>da1(2), DB1=>db1(2),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo2);
+
+ Inst_ODDRX2D_0_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(1), DB0=>db0(1), DA1=>da1(1), DB1=>db1(1),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1);
+
+ Inst_ODDRX2D_0_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(0), DB0=>db0(0), DA1=>da1(0), DB1=>db1(0),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0);
+
+ Inst7_DQSBUFE14: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk04, DQCLK1=>dqclk14);
+
+ Inst7_DQSBUFE13: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+ Inst7_DQSBUFE12: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+ Inst7_DQSBUFE11: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+ Inst7_DQSBUFE10: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst6_CLKDIVB: CLKDIVB
+ port map (CLKI=>eclk, RST=>reset, RELEASE=>scuba_vhi,
+ CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+ Inst5_ECLKSYNCA: ECLKSYNCA
+ port map (ECLKI=>clkop, STOP=>reset_d2, ECLKO=>eclk);
+
+ Inst4_FD1S3BX: FD1S3BX
+ port map (D=>reset_d1, CK=>clkok, PD=>reset, Q=>reset_d2);
+
+ Inst3_FD1S3BX: FD1S3BX
+ port map (D=>reset, CK=>clkok, PD=>reset, Q=>reset_d1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst2_EHXPLLF: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOS", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FIN=> "240.000000")
+ port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>clkop, CLKOS=>clkos,
+ CLKOK=>clkok, CLKOK2=>clkok2, LOCK=>pll_lock,
+ CLKINTFB=>clkintfb);
+
+ Inst1_OB19: OB
+ port map (I=>buf_qo19, O=>q(19));
+
+ Inst1_OB18: OB
+ port map (I=>buf_qo18, O=>q(18));
+
+ Inst1_OB17: OB
+ port map (I=>buf_qo17, O=>q(17));
+
+ Inst1_OB16: OB
+ port map (I=>buf_qo16, O=>q(16));
+
+ Inst1_OB15: OB
+ port map (I=>buf_qo15, O=>q(15));
+
+ Inst1_OB14: OB
+ port map (I=>buf_qo14, O=>q(14));
+
+ Inst1_OB13: OB
+ port map (I=>buf_qo13, O=>q(13));
+
+ Inst1_OB12: OB
+ port map (I=>buf_qo12, O=>q(12));
+
+ Inst1_OB11: OB
+ port map (I=>buf_qo11, O=>q(11));
+
+ Inst1_OB10: OB
+ port map (I=>buf_qo10, O=>q(10));
+
+ Inst1_OB9: OB
+ port map (I=>buf_qo9, O=>q(9));
+
+ Inst1_OB8: OB
+ port map (I=>buf_qo8, O=>q(8));
+
+ Inst1_OB7: OB
+ port map (I=>buf_qo7, O=>q(7));
+
+ Inst1_OB6: OB
+ port map (I=>buf_qo6, O=>q(6));
+
+ Inst1_OB5: OB
+ port map (I=>buf_qo5, O=>q(5));
+
+ Inst1_OB4: OB
+ port map (I=>buf_qo4, O=>q(4));
+
+ Inst1_OB3: OB
+ port map (I=>buf_qo3, O=>q(3));
+
+ Inst1_OB2: OB
+ port map (I=>buf_qo2, O=>q(2));
+
+ Inst1_OB1: OB
+ port map (I=>buf_qo1, O=>q(1));
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ddr_20 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+ for all:ODDRX2D use entity ecp3.ODDRX2D(V); end for;
+ for all:DQSBUFE1 use entity ecp3.DQSBUFE1(V); end for;
+ for all:ECLKSYNCA use entity ecp3.ECLKSYNCA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n ddr_20 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode out -io_type LVDS25 -width 20 -freq_in 480 -gear 2 -clk eclk -aligned -num_clk 2
+
+-- Fri Jul 3 11:01:17 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ddr_20 is
+ port (
+ clk: in std_logic;
+ pll_lock: out std_logic;
+ pll_reset: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ da0: in std_logic_vector(19 downto 0);
+ da1: in std_logic_vector(19 downto 0);
+ db0: in std_logic_vector(19 downto 0);
+ db1: in std_logic_vector(19 downto 0);
+ q: out std_logic_vector(19 downto 0));
+end ddr_20;
+
+architecture Structure of ddr_20 is
+
+ -- internal signal declarations
+ signal buf_clkout: std_logic;
+ signal dqclk17: std_logic;
+ signal dqclk07: std_logic;
+ signal dqclk16: std_logic;
+ signal dqclk06: std_logic;
+ signal dqclk15: std_logic;
+ signal dqclk05: std_logic;
+ signal dqclk14: std_logic;
+ signal dqclk04: std_logic;
+ signal dqclk13: std_logic;
+ signal dqclk03: std_logic;
+ signal dqclk12: std_logic;
+ signal dqclk02: std_logic;
+ signal dqclk11: std_logic;
+ signal dqclk01: std_logic;
+ signal dqclk10: std_logic;
+ signal dqclk00: std_logic;
+ signal cdiv8: std_logic;
+ signal cdiv4: std_logic;
+ signal cdiv1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal eclk: std_logic;
+ signal reset_d2: std_logic;
+ signal reset_d1: std_logic;
+ signal clkok2: std_logic;
+ signal clkok: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal scuba_vlo: std_logic;
+ signal clkintfb: std_logic;
+ signal buf_qo19: std_logic;
+ signal buf_qo18: std_logic;
+ signal buf_qo17: std_logic;
+ signal buf_qo16: std_logic;
+ signal buf_qo15: std_logic;
+ signal buf_qo14: std_logic;
+ signal buf_qo13: std_logic;
+ signal buf_qo12: std_logic;
+ signal buf_qo11: std_logic;
+ signal buf_qo10: std_logic;
+ signal buf_qo9: std_logic;
+ signal buf_qo8: std_logic;
+ signal buf_qo7: std_logic;
+ signal buf_qo6: std_logic;
+ signal buf_qo5: std_logic;
+ signal buf_qo4: std_logic;
+ signal buf_qo3: std_logic;
+ signal buf_qo2: std_logic;
+ signal buf_qo1: std_logic;
+ signal buf_qo0: std_logic;
+ signal sclk_t: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RST: in std_logic; RSTK: in std_logic;
+ WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic;
+ DRPAI0: in std_logic; DFPAI3: in std_logic;
+ DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic;
+ FDA2: in std_logic; FDA1: in std_logic;
+ FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic;
+ CLKOK2: out std_logic; LOCK: out std_logic;
+ CLKINTFB: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component CLKDIVB
+ port (CLKI: in std_logic; RST: in std_logic;
+ RELEASE: in std_logic; CDIV1: out std_logic;
+ CDIV2: out std_logic; CDIV4: out std_logic;
+ CDIV8: out std_logic);
+ end component;
+ component ODDRX2D
+ generic (MEMMODE : in String; ISI_CAL : in String);
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; SCLK: in std_logic;
+ DQCLK1: in std_logic; DQCLK0: in std_logic;
+ Q: out std_logic);
+ end component;
+ component DQSBUFE1
+ generic (DYNDEL_CNTL : in String; DYNDEL_VAL : in Integer;
+ DYNDEL_TYPE : in String);
+ port (ECLKW: in std_logic; RST: in std_logic;
+ DYNDELPOL: in std_logic; DYNDELAY6: in std_logic;
+ DYNDELAY5: in std_logic; DYNDELAY4: in std_logic;
+ DYNDELAY3: in std_logic; DYNDELAY2: in std_logic;
+ DYNDELAY1: in std_logic; DYNDELAY0: in std_logic;
+ DQCLK0: out std_logic; DQCLK1: out std_logic);
+ end component;
+ component ECLKSYNCA
+ port (ECLKI: in std_logic; STOP: in std_logic;
+ ECLKO: out std_logic);
+ end component;
+ attribute ODDRAPPS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOK : string;
+ attribute IO_TYPE : string;
+ attribute ODDRAPPS of Inst_ODDRX2D_3_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_3_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_2_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_1_0 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_4 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_3 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED";
+ attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED";
+ attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "480.000000";
+ attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "240.000000";
+ attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "240.000000";
+ attribute IO_TYPE of Inst1_OB19 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB18 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB17 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB16 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB15 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB14 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB13 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB12 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB11 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB10 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB9 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB8 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS25";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS25";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+
+ Inst_ODDRX2D_3_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(19), DB0=>db0(19), DA1=>da1(19), DB1=>db1(19),
+ SCLK=>sclk_t, DQCLK1=>dqclk16, DQCLK0=>dqclk06, Q=>buf_qo19);
+
+ Inst_ODDRX2D_3_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(18), DB0=>db0(18), DA1=>da1(18), DB1=>db1(18),
+ SCLK=>sclk_t, DQCLK1=>dqclk17, DQCLK0=>dqclk07, Q=>buf_qo18);
+
+ Inst_ODDRX2D_3_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(17), DB0=>db0(17), DA1=>da1(17), DB1=>db1(17),
+ SCLK=>sclk_t, DQCLK1=>dqclk17, DQCLK0=>dqclk07, Q=>buf_qo17);
+
+ Inst_ODDRX2D_3_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(16), DB0=>db0(16), DA1=>da1(16), DB1=>db1(16),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo16);
+
+ Inst_ODDRX2D_3_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(15), DB0=>db0(15), DA1=>da1(15), DB1=>db1(15),
+ SCLK=>sclk_t, DQCLK1=>dqclk16, DQCLK0=>dqclk06, Q=>buf_qo15);
+
+ Inst_ODDRX2D_2_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(14), DB0=>db0(14), DA1=>da1(14), DB1=>db1(14),
+ SCLK=>sclk_t, DQCLK1=>dqclk16, DQCLK0=>dqclk06, Q=>buf_qo14);
+
+ Inst_ODDRX2D_2_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(13), DB0=>db0(13), DA1=>da1(13), DB1=>db1(13),
+ SCLK=>sclk_t, DQCLK1=>dqclk15, DQCLK0=>dqclk05, Q=>buf_qo13);
+
+ Inst_ODDRX2D_2_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(12), DB0=>db0(12), DA1=>da1(12), DB1=>db1(12),
+ SCLK=>sclk_t, DQCLK1=>dqclk14, DQCLK0=>dqclk04, Q=>buf_qo12);
+
+ Inst_ODDRX2D_2_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(11), DB0=>db0(11), DA1=>da1(11), DB1=>db1(11),
+ SCLK=>sclk_t, DQCLK1=>dqclk14, DQCLK0=>dqclk04, Q=>buf_qo11);
+
+ Inst_ODDRX2D_2_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(10), DB0=>db0(10), DA1=>da1(10), DB1=>db1(10),
+ SCLK=>sclk_t, DQCLK1=>dqclk14, DQCLK0=>dqclk04, Q=>buf_qo10);
+
+ Inst_ODDRX2D_1_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(9), DB0=>db0(9), DA1=>da1(9), DB1=>db1(9),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo9);
+
+ Inst_ODDRX2D_1_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(8), DB0=>db0(8), DA1=>da1(8), DB1=>db1(8),
+ SCLK=>sclk_t, DQCLK1=>dqclk13, DQCLK0=>dqclk03, Q=>buf_qo8);
+
+ Inst_ODDRX2D_1_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(7), DB0=>db0(7), DA1=>da1(7), DB1=>db1(7),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo7);
+
+ Inst_ODDRX2D_1_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(6), DB0=>db0(6), DA1=>da1(6), DB1=>db1(6),
+ SCLK=>sclk_t, DQCLK1=>dqclk12, DQCLK0=>dqclk02, Q=>buf_qo6);
+
+ Inst_ODDRX2D_1_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(5), DB0=>db0(5), DA1=>da1(5), DB1=>db1(5),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo5);
+
+ Inst_ODDRX2D_0_4: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(4), DB0=>db0(4), DA1=>da1(4), DB1=>db1(4),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo4);
+
+ Inst_ODDRX2D_0_3: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(3), DB0=>db0(3), DA1=>da1(3), DB1=>db1(3),
+ SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo3);
+
+ Inst_ODDRX2D_0_2: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(2), DB0=>db0(2), DA1=>da1(2), DB1=>db1(2),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo2);
+
+ Inst_ODDRX2D_0_1: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(1), DB0=>db0(1), DA1=>da1(1), DB1=>db1(1),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1);
+
+ Inst_ODDRX2D_0_0: ODDRX2D
+ generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
+ port map (DA0=>da0(0), DB0=>db0(0), DA1=>da1(0), DB1=>db1(0),
+ SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0);
+
+ Inst7_DQSBUFE17: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk07, DQCLK1=>dqclk17);
+
+ Inst7_DQSBUFE16: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk06, DQCLK1=>dqclk16);
+
+ Inst7_DQSBUFE15: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk05, DQCLK1=>dqclk15);
+
+ Inst7_DQSBUFE14: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk04, DQCLK1=>dqclk14);
+
+ Inst7_DQSBUFE13: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+ Inst7_DQSBUFE12: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+ Inst7_DQSBUFE11: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+ Inst7_DQSBUFE10: DQSBUFE1
+ generic map (DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC",
+ DYNDEL_TYPE=> "NORMAL")
+ port map (ECLKW=>eclk, RST=>reset, DYNDELPOL=>scuba_vlo,
+ DYNDELAY6=>scuba_vlo, DYNDELAY5=>scuba_vlo,
+ DYNDELAY4=>scuba_vlo, DYNDELAY3=>scuba_vlo,
+ DYNDELAY2=>scuba_vlo, DYNDELAY1=>scuba_vlo,
+ DYNDELAY0=>scuba_vlo, DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst6_CLKDIVB: CLKDIVB
+ port map (CLKI=>eclk, RST=>reset, RELEASE=>scuba_vhi,
+ CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+ Inst5_ECLKSYNCA: ECLKSYNCA
+ port map (ECLKI=>clkop, STOP=>reset_d2, ECLKO=>eclk);
+
+ Inst4_FD1S3BX: FD1S3BX
+ port map (D=>reset_d1, CK=>clkok, PD=>reset, Q=>reset_d2);
+
+ Inst3_FD1S3BX: FD1S3BX
+ port map (D=>reset, CK=>clkok, PD=>reset, Q=>reset_d1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ Inst2_EHXPLLF: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOS", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FIN=> "240.000000")
+ port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>clkop, CLKOS=>clkos,
+ CLKOK=>clkok, CLKOK2=>clkok2, LOCK=>pll_lock,
+ CLKINTFB=>clkintfb);
+
+ Inst1_OB19: OB
+ port map (I=>buf_qo19, O=>q(19));
+
+ Inst1_OB18: OB
+ port map (I=>buf_qo18, O=>q(18));
+
+ Inst1_OB17: OB
+ port map (I=>buf_qo17, O=>q(17));
+
+ Inst1_OB16: OB
+ port map (I=>buf_qo16, O=>q(16));
+
+ Inst1_OB15: OB
+ port map (I=>buf_qo15, O=>q(15));
+
+ Inst1_OB14: OB
+ port map (I=>buf_qo14, O=>q(14));
+
+ Inst1_OB13: OB
+ port map (I=>buf_qo13, O=>q(13));
+
+ Inst1_OB12: OB
+ port map (I=>buf_qo12, O=>q(12));
+
+ Inst1_OB11: OB
+ port map (I=>buf_qo11, O=>q(11));
+
+ Inst1_OB10: OB
+ port map (I=>buf_qo10, O=>q(10));
+
+ Inst1_OB9: OB
+ port map (I=>buf_qo9, O=>q(9));
+
+ Inst1_OB8: OB
+ port map (I=>buf_qo8, O=>q(8));
+
+ Inst1_OB7: OB
+ port map (I=>buf_qo7, O=>q(7));
+
+ Inst1_OB6: OB
+ port map (I=>buf_qo6, O=>q(6));
+
+ Inst1_OB5: OB
+ port map (I=>buf_qo5, O=>q(5));
+
+ Inst1_OB4: OB
+ port map (I=>buf_qo4, O=>q(4));
+
+ Inst1_OB3: OB
+ port map (I=>buf_qo3, O=>q(3));
+
+ Inst1_OB2: OB
+ port map (I=>buf_qo2, O=>q(2));
+
+ Inst1_OB1: OB
+ port map (I=>buf_qo1, O=>q(1));
+
+ Inst1_OB0: OB
+ port map (I=>buf_qo0, O=>q(0));
+
+ sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ddr_20 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:OB use entity ecp3.OB(V); end for;
+ for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+ for all:ODDRX2D use entity ecp3.ODDRX2D(V); end for;
+ for all:DQSBUFE1 use entity ecp3.DQSBUFE1(V); end for;
+ for all:ECLKSYNCA use entity ecp3.ECLKSYNCA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
-c 1
-e 2
#-g guidefile.ncd
-#-m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+
+# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
+PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_tx_full" ;
+
+MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_right 20 ns;
+MULTICYCLE FROM CLKNET clk_sys TO CLKNET THE_PULSER/clk_slow_left 20 ns;
+
+
+BLOCK PATH TO CELL "THE_PULSER/period*" ;
+BLOCK PATH TO CELL "THE_PULSER/length*" ;
+BLOCK PATH TO CELL "THE_PULSER/offset*" ;
+
+
+
+# REGION "REGION_PULSER_LEFT" "R2C2D" 114 36 DEVSIZE;
+UGROUP "Pulser_left" BBOX 114 20
+ BLKNAME THE_PULSER/multi_ch_pulser_left.0.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.1.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.2.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.3.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.4.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.5.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.6.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.7.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.8.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.9.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.10.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.11.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.12.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.13.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.14.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.15.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.16.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.17.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.18.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_left.19.pulser
+ ;
+LOCATE UGROUP "Pulser_left" SITE "R2C2D";
+
+# REGION "REGION_PULSER_RIGHT" "R2C147D" 114 35 DEVSIZE;
+UGROUP "Pulser_right" BBOX 114 20
+ BLKNAME THE_PULSER/multi_ch_pulser_right.0.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.1.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.2.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.3.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.4.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.5.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.6.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.7.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.8.pulser
+ BLKNAME THE_PULSER/multi_ch_pulser_right.9.pulser
+ ;
+LOCATE UGROUP "Pulser_right" SITE "R2C152D";
\ No newline at end of file
# compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3sc_basic"
+set_option -top_module "trb3sc_pulser"
set_option -resource_sharing false
# map options
# set result format/file last
project -result_format "edif"
-project -result_file "workdir/trb3sc_basic.edf"
+project -result_file "workdir/trb3sc_pulser.edf"
#implementation attributes
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+add_file -vhdl -lib work "./cores/ddr_10_manual.vhd"
+add_file -vhdl -lib work "./cores/ddr_20_manual.vhd"
+add_file -vhdl -lib work "./code/single_channel_pulser.vhd"
+add_file -vhdl -lib work "./code/pulser.vhd"
-
-add_file -vhdl -lib work "./trb3sc_basic.vhd"
+add_file -vhdl -lib work "./trb3sc_pulser.vhd"
#add_file -fpga_constraint "./synplify.fdc"
use work.trb_net_gbe_components.all;
use work.med_sync_define.all;
-entity trb3sc_basic is
+entity trb3sc_pulser is
port(
CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
+ CLK_CORE_PLL_LEFT : in std_logic;
+ CLK_CORE_PLL_RIGHT : in std_logic;
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
- --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
- --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
- --CLK_CORE_PLL_LEFT : in std_logic; --not used
- --CLK_CORE_PLL_RIGHT : in std_logic; --not used
- --CLK_EXT_PCLK : in std_logic; --not used
- --CLK_EXT_PLL_RIGHT : in std_logic; --not used
-
TRIG_LEFT : in std_logic; --Trigger Input
- --TRIG_PLL : in std_logic; --not used
- --TRIG_RIGHT : in std_logic; --not used
- --Backplane, all lines
- BACK_GPIO : inout std_logic_vector(15 downto 0);
- BACK_LVDS : inout std_logic_vector( 1 downto 0);
- BACK_3V3 : inout std_logic_vector( 3 downto 0);
--Backplane for slaves on trbv3scbp1
-- BACK_GPIO : inout std_logic_vector(3 downto 0);
--AddOn Connector
- --to be added
+ OUTP : out std_logic_vector(16 downto 1);
+ OUTP_FAN : out std_logic_vector(3 downto 0);
+ OUTP_ANA : out std_logic_vector(9 downto 0);
+
+ INP : in std_logic_vector(3 downto 0);
+
+ SEL1 : out std_logic_vector(3 downto 0);
+ SEL2 : out std_logic_vector(3 downto 0);
+ SELO1 : out std_logic_vector(1 downto 0);
+ SELO2 : out std_logic_vector(1 downto 0);
+
+ LED_PULSER : out std_logic_vector(4 downto 0);
+
+ MOSI : out std_logic;
+ MISO : in std_logic;
+ SCK : out std_logic;
+ SCS : out std_logic;
+
+ PULSER_TRIG_OUT : out std_logic;
--KEL Connector
-- KEL : inout std_logic_vector(40 downto 1);
end entity;
-architecture trb3sc_arch of trb3sc_basic is
+architecture trb3sc_arch of trb3sc_pulser is
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 0);
- signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, buspulse_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, buspulse_tx : CTRLBUS_TX;
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0),
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
BUS_RX(1) => bussci_rx, --SCI Serdes
BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => buspulse_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bussci_tx,
BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => buspulse_tx,
STAT_DEBUG => open
);
DEBUG_OUT => open
);
+
+THE_PULSER : entity work.pulser
+ port map(
+ SYSCLK => clk_sys,
+ CLK_FAST_LEFT => CLK_CORE_PLL_LEFT,
+ CLK_FAST_RIGHT => CLK_CORE_PLL_RIGHT,
+ RESET => reset_i,
+
+ --Slowcontrol
+ BUS_RX => buspulse_rx,
+ BUS_TX => buspulse_tx,
+
+ --AddOn Connector
+ OUTP => OUTP,
+ OUTP_FAN => OUTP_FAN,
+ OUTP_ANA => OUTP_ANA,
+
+ INP => INP,
+
+ SEL1 => SEL1,
+ SEL2 => SEL2,
+ SELO1 => SELO1,
+ SELO2 => SELO2,
+
+ TRIG => PULSER_TRIG_OUT,
+
+ LED_PULSER => LED_PULSER,
+
+ DEBUG_OUT => open
+ );
+
+
---------------------------------------------------------------------------
-- Switches
---------------------------------------------------------------------------
HDR_IO(10 downto 7) <= (others => '0');
RJ_IO <= "0000";
-
- BACK_GPIO <= (others => 'Z');
- BACK_LVDS <= (others => '0');
- BACK_3V3 <= (others => 'Z');
+
---------------------------------------------------------------------------
-- LED
jspc29 / trb3sc.git / commitdiff