signal reset_via_gbe : std_logic;
signal reboot_from_gbe : std_logic;
- signal ctrlbus_rx, bustools_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX;
- signal ctrlbus_tx, bustools_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
signal bus_master_active : std_logic;
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: fifo_data
- type dl_rx_data_t is array(0 to 10) of std_logic_vector(10 downto 0);
- signal dl_rx_data : dl_rx_data_t;
- signal dl_rx_frame_req : std_logic_vector(10 downto 0);
- signal dl_rx_frame_ack : std_logic_vector(10 downto 0);
- signal dl_rx_frame_avail : std_logic_vector(10 downto 0);
- signal dl_tx_fifofull : std_logic_vector(10 downto 0);
+ type dl_rx_data_t is array(0 to 9) of std_logic_vector(10 downto 0);
+ signal dl_rx_data : dl_rx_data_t; -- DL (RX) to 1:n MUX
+ signal dl_rx_frame_req : std_logic_vector(9 downto 0);
+ signal dl_rx_frame_ack : std_logic_vector(9 downto 0);
+ signal dl_rx_frame_avail : std_logic_vector(9 downto 0);
+ signal dl_rx_fifofull : std_logic_vector(9 downto 0);
+ signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
+ signal dl_tx_fifofull : std_logic_vector(9 downto 0);
-- 10: frame_start
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: data
- signal ul_rx_data : std_logic_vector(10 downto 0);
- signal ul_tx_data : std_logic_vector(10 downto 0);
- signal ul_tx_data_q : std_logic_vector(10 downto 0);
- signal ul_tx_fifofull : std_logic;
+ signal ul_rx_data : std_logic_vector(10 downto 0); -- UL (RX) to 1:2 MUXes
signal ul_rx_frame_avail : std_logic;
signal ul_rx_frame_req : std_logic;
signal ul_rx_frame_ack : std_logic;
signal ul_rx_fifofull : std_logic;
-
- signal port_sel : std_logic_vector(10 downto 0);
+ signal ul_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to UL (TX)
+ signal ul_tx_fifofull : std_logic;
+ -- these signals go from multiplexer to UL (TX)
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal local_rx_data : std_logic_vector(10 downto 0); -- CPU (RX) to 1:2 MUXes
+ signal local_rx_frame_avail : std_logic;
+ signal local_rx_frame_req : std_logic;
+ signal local_rx_frame_ack : std_logic;
+ signal local_rx_fifofull : std_logic;
+ signal local_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to CPU (TX)
+ signal local_tx_fifofull : std_logic;
+ -- these signals go from multiplexer to UL (TX)
+
+ signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
+
+ signal dl_rx_port_sel : std_logic_vector(9 downto 0);
+ signal ul_tx_port_sel : std_logic;
+ signal dl_tx_port_sel : std_logic;
+ signal local_tx_port_sel : std_logic;
signal pcs_an_ready : std_logic;
signal link_active : std_logic;
signal debug : std_logic_vector(31 downto 0);
- signal sniffer_data : std_logic_vector(7 downto 0);
+ signal sniffer_data : std_logic_vector(7 downto 0); -- SCTRL endpoint
signal sniffer_wr : std_logic;
signal sniffer_eof : std_logic;
signal sniffer_error : std_logic;
---------------------------------------------------------------------------
--- scattering: data from uplink is distributed to downlinks
---------------------------------------------------------------------------
- THE_SCATTER: entity scatter_ports
+ THE_SGL_CTRL: entity sgl_ctrl
port map(
- CLK => clk_sys,
- RESET => reset_i,
+ CLK => clk_sys,
+ RESET => reset_i,
+ -- UL port
+ UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full
+ UL_FRAME_AVAIL_IN => ul_rx_frame_avail, -- UL RX has frames for DL/LOCAL
+ UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
+ UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
+ -- DL ports (includes SCTRL)
+ DL_FIFOFULL_IN(9 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
+ DL_FRAME_AVAIL_IN(9 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
+ DL_FRAME_REQ_OUT(9 downto 0) => dl_rx_frame_req, -- DL RXn request to send
+ DL_FRAME_ACK_IN(9 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
+ -- CPU port
+ LOCAL_FIFOFULL_IN => local_tx_fifofull, -- LOCAL TX FIFO is full
+ LOCAL_FRAME_AVAIL_IN => local_rx_frame_avail, -- LOCAL RX has frames for UL/DL
+ LOCAL_FRAME_REQ_OUT => local_rx_frame_req, -- LOCAL RX request to send
+ LOCAL_FRAME_ACK_IN => local_rx_frame_ack, -- LOCAL RX sent acknowledge
+ --
+ DL_RX_PORT_SEL_OUT(9 downto 0) => dl_rx_port_sel,
+ DL_RX_PORT_MUX_OUT => open,
+ DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
+ LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
+ UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
--
- FIFO_FULL_IN(10 downto 1) => dl_tx_fifofull(10 downto 1),
- FIFO_FULL_OUT => ul_rx_fifofull,
- FRAME_AVAIL_IN => ul_rx_frame_avail,
- FRAME_REQ_OUT => ul_rx_frame_req,
- FRAME_ACK_IN => ul_rx_frame_ack,
- CYCLE_DONE_OUT => open,
- --
- DEBUG => open
+ DEBUG => open
);
---------------------------------------------------------------------------
--- gathering: data from downlink ports is forwarded
+-- Multiplexers for data streams
---------------------------------------------------------------------------
- THE_GATHER: entity gather_ports
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- --
- FRAME_AVAIL_IN(10 downto 0) => dl_rx_frame_avail(10 downto 0),
- FRAME_REQ_OUT(10 downto 0) => dl_rx_frame_req(10 downto 0),
- FRAME_ACK_IN(10 downto 0) => dl_rx_frame_ack(10 downto 0),
- PORT_SELECT_OUT(10 downto 0) => port_sel(10 downto 0),
- PORT_MUX_OUT => open,
- CYCLE_DONE_OUT => open,
- --
- DEBUG => open
- );
-
- THE_QUICK_MUX: process( port_sel, dl_rx_data )
+ THE_DL_RX_MUX: process( dl_rx_port_sel, dl_rx_data )
begin
- case port_sel is
- when b"00000000001" => ul_tx_data <= dl_rx_data(0);
- when b"00000000010" => ul_tx_data <= dl_rx_data(1);
- when b"00000000100" => ul_tx_data <= dl_rx_data(2);
- when b"00000001000" => ul_tx_data <= dl_rx_data(3);
- when b"00000010000" => ul_tx_data <= dl_rx_data(4);
- when b"00000100000" => ul_tx_data <= dl_rx_data(5);
- when b"00001000000" => ul_tx_data <= dl_rx_data(6);
- when b"00010000000" => ul_tx_data <= dl_rx_data(7);
- when b"00100000000" => ul_tx_data <= dl_rx_data(8);
- when b"01000000000" => ul_tx_data <= dl_rx_data(9);
- when b"10000000000" => ul_tx_data <= dl_rx_data(10);
- when others => ul_tx_data <= (others => '0');
+ case dl_rx_port_sel is
+ when b"0000000001" => switch_rx_data <= dl_rx_data(0);
+ when b"0000000010" => switch_rx_data <= dl_rx_data(1);
+ when b"0000000100" => switch_rx_data <= dl_rx_data(2);
+ when b"0000001000" => switch_rx_data <= dl_rx_data(3);
+ when b"0000010000" => switch_rx_data <= dl_rx_data(4);
+ when b"0000100000" => switch_rx_data <= dl_rx_data(5);
+ when b"0001000000" => switch_rx_data <= dl_rx_data(6);
+ when b"0010000000" => switch_rx_data <= dl_rx_data(7);
+ when b"0100000000" => switch_rx_data <= dl_rx_data(8);
+ when b"1000000000" => switch_rx_data <= dl_rx_data(9);
+ when others => switch_rx_data <= (others => '0');
end case;
- end process THE_QUICK_MUX;
+ end process THE_DL_RX_MUX;
+
+ ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data;
+
+ local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data;
+
+ dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data;
- ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
+---------------------------------------------------------------------------
+-- Debug pins
+---------------------------------------------------------------------------
-- 10: frame_start
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: data
- DBG(3 downto 0) <= port_sel(3 downto 0);
- DBG(11 downto 4) <= ul_rx_data(7 downto 0);
- DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0);
- DBG(20) <= ul_rx_frame_avail;
- DBG(21) <= ul_rx_frame_req;
- DBG(22) <= ul_rx_frame_ack;
- DBG(23) <= dl_rx_data(0)(9);
- DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0);
- DBG(28) <= debug(0); --ul_rx_data(8);
- DBG(29) <= ul_rx_data(9);
- DBG(30) <= debug(1); --ul_rx_data(10);
- DBG(31) <= ul_rx_fifofull;
- DBG(32) <= debug(2); --dl_rx_data(0)(8);
- DBG(33) <= clk_sys;
+-- DBG(3 downto 0) <= port_sel(3 downto 0);
+-- DBG(11 downto 4) <= ul_rx_data(7 downto 0);
+-- DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0);
+-- DBG(20) <= ul_rx_frame_avail;
+-- DBG(21) <= ul_rx_frame_req;
+-- DBG(22) <= ul_rx_frame_ack;
+-- DBG(23) <= dl_rx_data(0)(9);
+-- DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0);
+-- DBG(28) <= debug(0); --ul_rx_data(8);
+-- DBG(29) <= ul_rx_data(9);
+-- DBG(30) <= debug(1); --ul_rx_data(10);
+-- DBG(31) <= ul_rx_fifofull;
+-- DBG(32) <= debug(2); --dl_rx_data(0)(8);
+-- DBG(33) <= clk_sys;
---------------------------------------------------------------------------
-- GbE wrapper without med interface
---------------------------------------------------------------------------
GBE : entity work.gbe_wrapper_fifo
generic map(
- LINK_HAS_READOUT => '0',
LINK_HAS_SLOWCTRL => '1',
LINK_HAS_DHCP => '1',
LINK_HAS_ARP => '1',
CLK_125_IN => clk_sys,
RESET => reset_i,
GSR_N => reset_n_i,
- -- Trigger
- TRIGGER_IN => '0',
-- we connect to FIFO interface directly
-- FIFO interface TX (send frames)
FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
--
PCS_AN_READY_IN => link_active,
LINK_ACTIVE_IN => link_active,
- --
-- unique adresses
MC_UNIQUE_ID_IN => timer.uid,
MY_TRBNET_ADDRESS_IN => timer.network_address,
GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
GSC_REPLY_READ_OUT => gsc_reply_read,
GSC_BUSY_IN => gsc_busy,
- -- readout
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
-- reset
MAKE_RESET_OUT => reset_via_gbe,
-- debug
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 8, 2 => 8, others => 0),
+ PORT_NUMBER => 1,
+ PORT_ADDRESSES => (0 => x"d000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
REGIO_TX => ctrlbus_tx,
--
BUS_RX(0) => bustools_rx, -- Flash, SPI, UART, ADC, SED
- BUS_RX(1) => busgbeip_rx,
- BUS_RX(2) => busgbereg_rx,
BUS_TX(0) => bustools_tx,
- BUS_TX(1) => busgbeip_tx,
- BUS_TX(2) => busgbereg_tx,
STAT_DEBUG => open
);
CLK_125 => clk_sys,
-- SerDes 0 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(0) => ul_tx_fifofull,
- FIFO_WR_OUT(0) => dl_rx_data(10)(9),
- FIFO_DATA_OUT(8 downto 0) => dl_rx_data(10)(8 downto 0),
- FRAME_START_OUT(0) => dl_rx_data(10)(10),
- FRAME_REQ_IN(0) => dl_rx_frame_req(10),
- FRAME_ACK_OUT(0) => dl_rx_frame_ack(10),
- FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(10),
+ FIFO_FULL_IN(0) => '0', -- BUG
+ FIFO_WR_OUT(0) => dl_rx_data(9)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(9)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(9)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(9),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(9),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(9),
-- FIFO interface TX
- FIFO_WR_IN(0) => ul_rx_data(9),
- FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
- FRAME_START_IN(0) => ul_rx_data(10),
- FIFO_FULL_OUT(0) => dl_tx_fifofull(10),
+ FIFO_WR_IN(0) => dl_tx_data(9),
+ FIFO_DATA_IN(8 downto 0) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(0) => dl_tx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(9),
-- SerDes 1 -- UNUSED
-- SerDes 2 -- UNUSED
-- SerDes 3 -- UNUSED
CLK_125 => clk_sys,
-- SerDes 0 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(0) => ul_tx_fifofull,
- FIFO_WR_OUT(0) => dl_rx_data(8)(9),
- FIFO_DATA_OUT(8 downto 0) => dl_rx_data(8)(8 downto 0),
- FRAME_START_OUT(0) => dl_rx_data(8)(10),
- FRAME_REQ_IN(0) => dl_rx_frame_req(8),
- FRAME_ACK_OUT(0) => dl_rx_frame_ack(8),
- FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(8),
+ FIFO_FULL_IN(0) => '0', -- BUG
+ FIFO_WR_OUT(0) => dl_rx_data(7)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(7)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(7)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(7),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(7),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(7),
-- FIFO interface TX
- FIFO_WR_IN(0) => ul_rx_data(9),
- FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
- FRAME_START_IN(0) => ul_rx_data(10),
- FIFO_FULL_OUT(0) => dl_tx_fifofull(8),
+ FIFO_WR_IN(0) => dl_tx_data(9),
+ FIFO_DATA_IN(8 downto 0) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(0) => dl_tx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(7),
-- SerDes 1 - DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(1) => ul_tx_fifofull,
- FIFO_WR_OUT(1) => dl_rx_data(9)(9),
- FIFO_DATA_OUT(17 downto 9) => dl_rx_data(9)(8 downto 0),
- FRAME_START_OUT(1) => dl_rx_data(9)(10),
- FRAME_REQ_IN(1) => dl_rx_frame_req(9),
- FRAME_ACK_OUT(1) => dl_rx_frame_ack(9),
- FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(9),
+ FIFO_FULL_IN(1) => '0', -- BUG
+ FIFO_WR_OUT(1) => dl_rx_data(8)(9),
+ FIFO_DATA_OUT(17 downto 9) => dl_rx_data(8)(8 downto 0),
+ FRAME_START_OUT(1) => dl_rx_data(8)(10),
+ FRAME_REQ_IN(1) => dl_rx_frame_req(8),
+ FRAME_ACK_OUT(1) => dl_rx_frame_ack(8),
+ FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(8),
-- FIFO interface TX
- FIFO_WR_IN(1) => ul_rx_data(9),
- FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
- FRAME_START_IN(1) => ul_rx_data(10),
- FIFO_FULL_OUT(1) => dl_tx_fifofull(9),
+ FIFO_WR_IN(1) => dl_tx_data(9),
+ FIFO_DATA_IN(17 downto 9) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(1) => dl_tx_data(10),
+ FIFO_FULL_OUT(1) => dl_tx_fifofull(8),
-- SerDes 2 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(2) => ul_tx_fifofull,
- FIFO_WR_OUT(2) => dl_rx_data(3)(9),
- FIFO_DATA_OUT(26 downto 18) => dl_rx_data(3)(8 downto 0),
- FRAME_START_OUT(2) => dl_rx_data(3)(10),
- FRAME_REQ_IN(2) => dl_rx_frame_req(3),
- FRAME_ACK_OUT(2) => dl_rx_frame_ack(3),
- FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(3),
+ FIFO_FULL_IN(2) => '0', -- BUG
+ FIFO_WR_OUT(2) => dl_rx_data(2)(9),
+ FIFO_DATA_OUT(26 downto 18) => dl_rx_data(2)(8 downto 0),
+ FRAME_START_OUT(2) => dl_rx_data(2)(10),
+ FRAME_REQ_IN(2) => dl_rx_frame_req(2),
+ FRAME_ACK_OUT(2) => dl_rx_frame_ack(2),
+ FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(2),
-- FIFO interface TX
- FIFO_WR_IN(2) => ul_rx_data(9),
- FIFO_DATA_IN(26 downto 18) => ul_rx_data(8 downto 0),
- FRAME_START_IN(2) => ul_rx_data(10),
- FIFO_FULL_OUT(2) => dl_tx_fifofull(3),
+ FIFO_WR_IN(2) => dl_tx_data(9),
+ FIFO_DATA_IN(26 downto 18) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(2) => dl_tx_data(10),
+ FIFO_FULL_OUT(2) => dl_tx_fifofull(2),
-- SerDes 3 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(3) => ul_tx_fifofull,
- FIFO_WR_OUT(3) => dl_rx_data(2)(9),
- FIFO_DATA_OUT(35 downto 27) => dl_rx_data(2)(8 downto 0),
- FRAME_START_OUT(3) => dl_rx_data(2)(10),
- FRAME_REQ_IN(3) => dl_rx_frame_req(2),
- FRAME_ACK_OUT(3) => dl_rx_frame_ack(2),
- FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(2),
+ FIFO_FULL_IN(3) => '0', -- BUG
+ FIFO_WR_OUT(3) => dl_rx_data(1)(9),
+ FIFO_DATA_OUT(35 downto 27) => dl_rx_data(1)(8 downto 0),
+ FRAME_START_OUT(3) => dl_rx_data(1)(10),
+ FRAME_REQ_IN(3) => dl_rx_frame_req(1),
+ FRAME_ACK_OUT(3) => dl_rx_frame_ack(1),
+ FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(1),
-- FIFO interface TX
- FIFO_WR_IN(3) => ul_rx_data(9),
- FIFO_DATA_IN(35 downto 27) => ul_rx_data(8 downto 0),
- FRAME_START_IN(3) => ul_rx_data(10),
- FIFO_FULL_OUT(3) => dl_tx_fifofull(2),
+ FIFO_WR_IN(3) => dl_tx_data(9),
+ FIFO_DATA_IN(35 downto 27) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(3) => dl_tx_data(10),
+ FIFO_FULL_OUT(3) => dl_tx_fifofull(1),
-- SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(5),
SD_PRSNT_N_IN(1) => HUB_MOD0(6),
CLK_125 => clk_sys,
-- SerDes 0 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(0) => ul_tx_fifofull,
- FIFO_WR_OUT(0) => dl_rx_data(6)(9),
- FIFO_DATA_OUT(8 downto 0) => dl_rx_data(6)(8 downto 0),
- FRAME_START_OUT(0) => dl_rx_data(6)(10),
- FRAME_REQ_IN(0) => dl_rx_frame_req(6),
- FRAME_ACK_OUT(0) => dl_rx_frame_ack(6),
- FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(6),
+ FIFO_FULL_IN(0) => '0', -- BUG
+ FIFO_WR_OUT(0) => dl_rx_data(5)(9),
+ FIFO_DATA_OUT(8 downto 0) => dl_rx_data(5)(8 downto 0),
+ FRAME_START_OUT(0) => dl_rx_data(5)(10),
+ FRAME_REQ_IN(0) => dl_rx_frame_req(5),
+ FRAME_ACK_OUT(0) => dl_rx_frame_ack(5),
+ FRAME_AVAIL_OUT(0) => dl_rx_frame_avail(5),
-- FIFO interface TX
- FIFO_WR_IN(0) => ul_rx_data(9),
- FIFO_DATA_IN(8 downto 0) => ul_rx_data(8 downto 0),
- FRAME_START_IN(0) => ul_rx_data(10),
- FIFO_FULL_OUT(0) => dl_tx_fifofull(6),
+ FIFO_WR_IN(0) => dl_tx_data(9),
+ FIFO_DATA_IN(8 downto 0) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(0) => dl_tx_data(10),
+ FIFO_FULL_OUT(0) => dl_tx_fifofull(5),
-- SerDes 1 - DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(1) => ul_tx_fifofull,
- FIFO_WR_OUT(1) => dl_rx_data(7)(9),
- FIFO_DATA_OUT(17 downto 9) => dl_rx_data(7)(8 downto 0),
- FRAME_START_OUT(1) => dl_rx_data(7)(10),
- FRAME_REQ_IN(1) => dl_rx_frame_req(7),
- FRAME_ACK_OUT(1) => dl_rx_frame_ack(7),
- FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(7),
+ FIFO_FULL_IN(1) => '0', -- BUG
+ FIFO_WR_OUT(1) => dl_rx_data(6)(9),
+ FIFO_DATA_OUT(17 downto 9) => dl_rx_data(6)(8 downto 0),
+ FRAME_START_OUT(1) => dl_rx_data(6)(10),
+ FRAME_REQ_IN(1) => dl_rx_frame_req(6),
+ FRAME_ACK_OUT(1) => dl_rx_frame_ack(6),
+ FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(6),
-- FIFO interface TX
- FIFO_WR_IN(1) => ul_rx_data(9),
- FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
- FRAME_START_IN(1) => ul_rx_data(10),
- FIFO_FULL_OUT(1) => dl_tx_fifofull(7),
+ FIFO_WR_IN(1) => dl_tx_data(9),
+ FIFO_DATA_IN(17 downto 9) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(1) => dl_tx_data(10),
+ FIFO_FULL_OUT(1) => dl_tx_fifofull(6),
-- SerDes 2 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(2) => ul_tx_fifofull,
- FIFO_WR_OUT(2) => dl_rx_data(4)(9),
- FIFO_DATA_OUT(26 downto 18) => dl_rx_data(4)(8 downto 0),
- FRAME_START_OUT(2) => dl_rx_data(4)(10),
- FRAME_REQ_IN(2) => dl_rx_frame_req(4),
- FRAME_ACK_OUT(2) => dl_rx_frame_ack(4),
- FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(4),
+ FIFO_FULL_IN(2) => '0', -- BUG
+ FIFO_WR_OUT(2) => dl_rx_data(3)(9),
+ FIFO_DATA_OUT(26 downto 18) => dl_rx_data(3)(8 downto 0),
+ FRAME_START_OUT(2) => dl_rx_data(3)(10),
+ FRAME_REQ_IN(2) => dl_rx_frame_req(3),
+ FRAME_ACK_OUT(2) => dl_rx_frame_ack(3),
+ FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(3),
-- FIFO interface TX
- FIFO_WR_IN(2) => ul_rx_data(9),
- FIFO_DATA_IN(26 downto 18) => ul_rx_data(8 downto 0),
- FRAME_START_IN(2) => ul_rx_data(10),
- FIFO_FULL_OUT(2) => dl_tx_fifofull(4),
+ FIFO_WR_IN(2) => dl_tx_data(9),
+ FIFO_DATA_IN(26 downto 18) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(2) => dl_tx_data(10),
+ FIFO_FULL_OUT(2) => dl_tx_fifofull(3),
-- SerDes 3 -- DOWNLINK
-- FIFO interface RX
- FIFO_FULL_IN(3) => ul_tx_fifofull,
- FIFO_WR_OUT(3) => dl_rx_data(5)(9),
- FIFO_DATA_OUT(35 downto 27) => dl_rx_data(5)(8 downto 0),
- FRAME_START_OUT(3) => dl_rx_data(5)(10),
- FRAME_REQ_IN(3) => dl_rx_frame_req(5),
- FRAME_ACK_OUT(3) => dl_rx_frame_ack(5),
- FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(5),
+ FIFO_FULL_IN(3) => '0', -- BUG
+ FIFO_WR_OUT(3) => dl_rx_data(4)(9),
+ FIFO_DATA_OUT(35 downto 27) => dl_rx_data(4)(8 downto 0),
+ FRAME_START_OUT(3) => dl_rx_data(4)(10),
+ FRAME_REQ_IN(3) => dl_rx_frame_req(4),
+ FRAME_ACK_OUT(3) => dl_rx_frame_ack(4),
+ FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(4),
-- FIFO interface TX
- FIFO_WR_IN(3) => ul_rx_data(9),
- FIFO_DATA_IN(35 downto 27) => ul_rx_data(8 downto 0),
- FRAME_START_IN(3) => ul_rx_data(10),
- FIFO_FULL_OUT(3) => dl_tx_fifofull(5),
+ FIFO_WR_IN(3) => dl_tx_data(9),
+ FIFO_DATA_IN(35 downto 27) => dl_tx_data(8 downto 0),
+ FRAME_START_IN(3) => dl_tx_data(10),
+ FIFO_FULL_OUT(3) => dl_tx_fifofull(4),
-- SFP Connection
SD_PRSNT_N_IN(0) => HUB_MOD0(3),
SD_PRSNT_N_IN(1) => HUB_MOD0(4),
CLK_125 => clk_sys,
-- SerDes 0 -- UPLINK
-- FIFO interface RX
- FIFO_FULL_IN(0) => ul_rx_fifofull,
+ FIFO_FULL_IN(0) => '0', -- BUG
FIFO_WR_OUT(0) => ul_rx_data(9),
FIFO_DATA_OUT(8 downto 0) => ul_rx_data(8 downto 0),
FRAME_START_OUT(0) => ul_rx_data(10),
FRAME_ACK_OUT(0) => ul_rx_frame_ack,
FRAME_AVAIL_OUT(0) => ul_rx_frame_avail,
-- FIFO interface TX
- FIFO_WR_IN(0) => ul_tx_data_q(9),
- FIFO_DATA_IN(8 downto 0) => ul_tx_data_q(8 downto 0),
- FRAME_START_IN(0) => ul_tx_data_q(10),
+ FIFO_WR_IN(0) => ul_tx_data(9),
+ FIFO_DATA_IN(8 downto 0) => ul_tx_data(8 downto 0),
+ FRAME_START_IN(0) => ul_tx_data(10),
FIFO_FULL_OUT(0) => ul_tx_fifofull,
- -- SerDes 1 - DOWNLINK
+ -- SerDes 1 - LOCAL
-- FIFO interface RX
- FIFO_FULL_IN(1) => ul_tx_fifofull,
- FIFO_WR_OUT(1) => dl_rx_data(1)(9),
- FIFO_DATA_OUT(17 downto 9) => dl_rx_data(1)(8 downto 0),
- FRAME_START_OUT(1) => dl_rx_data(1)(10),
- FRAME_REQ_IN(1) => dl_rx_frame_req(1),
- FRAME_ACK_OUT(1) => dl_rx_frame_ack(1),
- FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(1),
+ FIFO_FULL_IN(1) => '0', -- BUG
+ FIFO_WR_OUT(1) => local_rx_data(9),
+ FIFO_DATA_OUT(17 downto 9) => local_rx_data(8 downto 0),
+ FRAME_START_OUT(1) => local_rx_data(10),
+ FRAME_REQ_IN(1) => local_rx_frame_req,
+ FRAME_ACK_OUT(1) => local_rx_frame_ack,
+ FRAME_AVAIL_OUT(1) => local_rx_frame_avail,
-- FIFO interface TX
- FIFO_WR_IN(1) => ul_rx_data(9),
- FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0),
- FRAME_START_IN(1) => ul_rx_data(10),
- FIFO_FULL_OUT(1) => dl_tx_fifofull(1),
+ FIFO_WR_IN(1) => local_tx_data(9),
+ FIFO_DATA_IN(17 downto 9) => local_tx_data(8 downto 0),
+ FRAME_START_IN(1) => local_tx_data(10),
+ FIFO_FULL_OUT(1) => local_tx_fifofull,
-- SerDes 2 -- UNUSED
-- SerDes 3 -- UNUSED
-- SFP Connection
jspc29 / trb3sc.git / commitdiff