conflict fix

diff --cc hadesstart/trb3_periph_hadesstart.vhd
index 383892d010e06ce99c941cd6bf379a9050c51c25,460d3f644d22af3535e9e50053d9407f4d7ff8a0..d5f18bede1b8589c7a1785edc4a6e8e3459a102f
--- 1/hadesstart/trb3_periph_hadesstart.vhd
--- 2/hadesstart/trb3_periph_hadesstart.vhd
+++ b/hadesstart/trb3_periph_hadesstart.vhd
@@@ -253,30 -245,29 +253,29 @@@ architecture trb3_periph_hadesstart_arc
    signal trig_out   : std_logic_vector(3 downto 0);
    signal trig_din   : std_logic_vector(31 downto 0);
    signal trig_dout  : std_logic_vector(31 downto 0);
 -  signal trig_write : std_logic := '0';
 -  signal trig_read  : std_logic := '0';
 -  signal trig_ack   : std_logic := '0';
 -  signal trig_nack  : std_logic := '0';
 +  signal trig_write : std_logic                     := '0';
 +  signal trig_read  : std_logic                     := '0';
 +  signal trig_ack   : std_logic                     := '0';
 +  signal trig_nack  : std_logic                     := '0';
    signal trig_addr  : std_logic_vector(15 downto 0) := (others => '0');
  
-   signal stat_out   : std_logic_vector(3 downto 0);
    signal stat_din   : std_logic_vector(31 downto 0);
    signal stat_dout  : std_logic_vector(31 downto 0);
 -  signal stat_write : std_logic := '0';
 -  signal stat_read  : std_logic := '0';
 -  signal stat_ack   : std_logic := '0';
 -  signal stat_nack  : std_logic := '0';
 -  signal stat_addr  : std_logic_vector(15 downto 0) := (others => '0');  
 -
 -  signal sed_error  : std_logic;
 -  signal sed_din    : std_logic_vector(31 downto 0);
 -  signal sed_dout   : std_logic_vector(31 downto 0);
 -  signal sed_write  : std_logic := '0';
 -  signal sed_read   : std_logic := '0';
 -  signal sed_ack    : std_logic := '0';
 -  signal sed_nack   : std_logic := '0';
 -  signal sed_addr   : std_logic_vector(15 downto 0) := (others => '0');  
 -  
 +  signal stat_write : std_logic                     := '0';
 +  signal stat_read  : std_logic                     := '0';
 +  signal stat_ack   : std_logic                     := '0';
 +  signal stat_nack  : std_logic                     := '0';
 +  signal stat_addr  : std_logic_vector(15 downto 0) := (others => '0');
 +
 +  signal sed_error : std_logic;
 +  signal sed_din   : std_logic_vector(31 downto 0);
 +  signal sed_dout  : std_logic_vector(31 downto 0);
 +  signal sed_write : std_logic                     := '0';
 +  signal sed_read  : std_logic                     := '0';
 +  signal sed_ack   : std_logic                     := '0';
 +  signal sed_nack  : std_logic                     := '0';
 +  signal sed_addr  : std_logic_vector(15 downto 0) := (others => '0');
 +
    --TDC
    signal hit_in_i         : std_logic_vector(64 downto 1);
    signal inputs_i         : std_logic_vector(63 downto 0);
@@@ -796,28 -772,20 +795,20 @@@ begi
  ---------------------------------------------------------------------------
  -- SED Detection
  ---------------------------------------------------------------------------
 -THE_SED : entity work.sedcheck
 -  port map(
 -    CLK        => clk_100_i,
 -    ERROR_OUT  => sed_error,
 -    
 -    DATA_IN    => sed_din,
 -    DATA_OUT   => sed_dout, 
 -    WRITE_IN   => sed_write,
 -    READ_IN    => sed_read,
 -    ACK_OUT    => sed_ack,  
 -    NACK_OUT   => sed_nack, 
 -    ADDR_IN    => sed_addr
 -    );
 +  THE_SED : entity work.sedcheck
 +    port map(
 +      CLK       => clk_100_i,
 +      ERROR_OUT => sed_error,
 +
 +      DATA_IN  => sed_din,
 +      DATA_OUT => sed_dout,
 +      WRITE_IN => sed_write,
 +      READ_IN  => sed_read,
 +      ACK_OUT  => sed_ack,
 +      NACK_OUT => sed_nack,
 +      ADDR_IN  => sed_addr
 +      );
  
- -- THE_SED : entity work.sedcheck 
- --   port map(
- --     CLK        => clk_100_i,
- --     ERROR_OUT  => sed_error,
- --     i_rst_p    => i_rst_p,
- --     STATUS_OUT => TEST_LINE(11 downto 0)
- --     ); 
- 
  ---------------------------------------------------------------------------
  -- LED
  ---------------------------------------------------------------------------