added project file

diff --git a/pulser/design/padiwa.ldf b/pulser/design/padiwa.ldf
new file mode 100644 (file)
index 0000000..0621c38
--- /dev/null
+++ b/pulser/design/padiwa.ldf
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.0" title="padiwa" device="LCMXO2-4000HC-6FTG256C" default_implementation="pulser">
+    <Options/>
+    <Implementation title="pulser" dir="pulser" description="pulser" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="panda_dirc_wasa"/>
+        <Source name="../padiwa_pulser.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../lcd_config.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../lcd/padiwalcd.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../source/uart_rec.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../source/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../source/uart_trans.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../source/lcd.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../cores/pll.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../pinout/padiwa_amps.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="padiwa1.sty"/>
+</BaliProject>