#
# conditions
#
-set expression {bus(:uut_1:LVL2:APL_DATA_OUT[7], :uut_1:LVL2:APL_DATA_OUT[6], :uut_1:LVL2:APL_DATA_OUT[5], :uut_1:LVL2:APL_DATA_OUT[4], :uut_1:LVL2:APL_DATA_OUT[3], :uut_1:LVL2:APL_DATA_OUT[2], :uut_1:LVL2:APL_DATA_OUT[1], :uut_1:LVL2:APL_DATA_OUT[0])}
+set expression {bus(:uut_lvl2:APL_DATA_OUT[7], :uut_lvl2:APL_DATA_OUT[6], :uut_lvl2:APL_DATA_OUT[5], :uut_lvl2:APL_DATA_OUT[4], :uut_lvl2:APL_DATA_OUT[3], :uut_lvl2:APL_DATA_OUT[2], :uut_lvl2:APL_DATA_OUT[1], :uut_lvl2:APL_DATA_OUT[0])}
if {[catch {condition new -name DATA_OUT -expr $expression}] != ""} {
condition set -using DATA_OUT -expr $expression
}
window target "Design Browser 1" on
browser using {Design Browser 1}
browser set \
- -scope :uut_1:LVL2 \
+ -scope :uut_lvl2 \
-showassertions 0 \
-showfibers 0 \
-showinouts 0 \
-showinputs 0 \
-showinternals 0
-browser yview see :uut_1:LVL2
+browser yview see :uut_lvl2
browser timecontrol set -lock 0
#
cursor set -using TimeA -time 43,545,000,000fs
waveform baseline set -time 10,250,000,000fs
-set id [waveform add -signals [list :uut_1:LVL1:CLK_EN \
- :uut_1:LVL1:CLK \
- :uut_1:LVL1:RESET \
- :uut_1:LVL1:OLD_T \
- :uut_1:LVL1:OLD_TS \
- :uut_1:LVL1:OLD_TD \
- :uut_1:LVL1:OLD_TB \
- :uut_1:LVL1:OLD_TE \
- :uut_1:LVL1:present_state \
- :uut_1:LVL1:next_state \
- :uut_1:LVL1:APL_SEND_OUT \
- :uut_1:LVL1:APL_READ_OUT \
- :uut_1:LVL1:APL_RUN_IN \
- :uut_1:LVL1:APL_SEQNR_IN \
- :uut_1:LVL1:APL_DTYPE_OUT \
+set id [waveform add -signals [list :uut_lvl1:CLK_EN \
+ :uut_lvl1:CLK \
+ :uut_lvl1:RESET \
+ :uut_lvl1:OLD_T \
+ :uut_lvl1:OLD_TS \
+ :uut_lvl1:OLD_TD \
+ :uut_lvl1:OLD_TB \
+ :uut_lvl1:OLD_TE \
+ :uut_lvl1:present_state \
+ :uut_lvl1:next_state \
+ :uut_lvl1:APL_SEND_OUT \
+ :uut_lvl1:APL_READ_OUT \
+ :uut_lvl1:APL_RUN_IN \
+ :uut_lvl1:APL_SEQNR_IN \
+ :uut_lvl1:APL_DTYPE_OUT \
DATA_OUT \
- :uut_1:LVL2:CLK \
- :uut_1:LVL2:CLK \
- :uut_1:LVL2:RESET \
- :uut_1:LVL2:OLD_T \
- :uut_1:LVL2:OLD_TS \
- :uut_1:LVL2:OLD_TD \
- :uut_1:LVL2:OLD_TB \
- :uut_1:LVL2:OLD_TE \
- :uut_1:LVL2:DVAL_i \
- :uut_1:LVL2:present_state \
- :uut_1:LVL2:next_state \
- :uut_1:LVL2:APL_SEND_OUT \
- :uut_1:LVL2:APL_READ_OUT \
- :uut_1:LVL2:APL_RUN_IN \
- :uut_1:LVL2:APL_DTYPE_OUT \
+ :uut_lvl2:CLK \
+ :uut_lvl2:CLK \
+ :uut_lvl2:RESET \
+ :uut_lvl2:OLD_T \
+ :uut_lvl2:OLD_TS \
+ :uut_lvl2:OLD_TD \
+ :uut_lvl2:OLD_TB \
+ :uut_lvl2:OLD_TE \
+ :uut_lvl2:DVAL_i \
+ :uut_lvl2:present_state \
+ :uut_lvl2:next_state \
+ :uut_lvl2:APL_SEND_OUT \
+ :uut_lvl2:APL_READ_OUT \
+ :uut_lvl2:APL_RUN_IN \
+ :uut_lvl2:APL_DTYPE_OUT \
DATA_OUT ]]
waveform xview limits 0 120000ns
-- File : trb_net_old_to_new_testbench.vhd
-- Author : Tiago Perez (tiago.perez@uni-giessen.de)
-- Created : 2007/02/26 T. Perez
--- Last modified :
+-- Last modified : 2007/02/27 T. Perez
-------------------------------------------------------------------------------
-- Description : Testbench for the "trb_net_old_to_new" and the "OLD" trigger
-- bus in general
--
-------------------------------------------------------------------------------
-- Modification history :
--- 2007/01/12 : created
+-- 2007/02/26 : created
+-- 2007/02/27 : T. Perez
+-- Removed intermidiate dudu.vhd file. Now trb_net_old_to_new
+-- instatiated twice (LVL1 + LVL2). The .tcl and .tcl.sv were also
+-- modified because they were still pointing to old directories.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
signal SIM_END : boolean := false;
signal CLK : std_logic := '0';
+ signal CLK_EN : std_logic := '1';
signal RESET : std_logic;
signal APL_DATA_OUT_LVL1 : std_logic_vector (47 downto 0);
signal APL_WRITE_OUT_LVL1 : std_logic;
signal OLD_TD_LVL2 : std_logic_vector (3 downto 0);
signal OLD_TB_LVL2 : std_logic;
signal OLD_TE_LVL2 : std_logic;
+
-----------------------------------------------------------------------------
-- componet to test
-----------------------------------------------------------------------------
- component dudu
+ component trb_net_old_to_new
+ generic (
+ TRIGGER_LEVEL : integer);
port (
- CLK : in std_logic;
- RESET : in std_logic;
- APL_DATA_OUT : out std_logic_vector (47 downto 0);
- APL_WRITE_OUT : out std_logic;
- APL_FIFO_FULL_IN : in std_logic;
- APL_SHORT_TRANSFER_OUT : out std_logic;
- APL_DTYPE_OUT : out std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- APL_SEND_OUT : out std_logic;
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- APL_DATA_IN : in std_logic_vector (47 downto 0);
- APL_TYP_IN : in std_logic_vector (2 downto 0);
- APL_DATAREADY_IN : in std_logic;
- APL_READ_OUT : out std_logic;
- APL_RUN_IN : in std_logic;
- APL_SEQNR_IN : in std_logic_vector (7 downto 0);
- OLD_T : in std_logic;
- OLD_TS : in std_logic;
- OLD_TD : in std_logic_vector (3 downto 0);
- OLD_TB : out std_logic;
- OLD_TE : out std_logic;
- APL_DATA_OUT_LVL2 : out std_logic_vector (47 downto 0);
- APL_WRITE_OUT_LVL2 : out std_logic;
- APL_SHORT_TRANSFER_OUT_LVL2 : out std_logic;
- APL_DTYPE_OUT_LVL2 : out std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_OUT_LVL2 : out std_logic_vector (31 downto 0);
- APL_SEND_OUT_LVL2 : out std_logic;
- APL_TARGET_ADDRESS_OUT_LVL2 : out std_logic_vector (15 downto 0);
- APL_DATA_IN_LVL2 : in std_logic_vector (47 downto 0);
- APL_DATAREADY_IN_LVL2 : in std_logic;
- APL_READ_OUT_LVL2 : out std_logic;
- APL_RUN_IN_LVL2 : in std_logic;
- APL_SEQNR_IN_LVL2 : in std_logic_vector (7 downto 0);
- OLD_T_LVL2 : in std_logic;
- OLD_TS_LVL2 : in std_logic;
- OLD_TD_LVL2 : in std_logic_vector (3 downto 0);
- OLD_TB_LVL2 : out std_logic;
- OLD_TE_LVL2 : out std_logic);
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ APL_DATA_OUT : out std_logic_vector (47 downto 0);
+ APL_WRITE_OUT : out std_logic;
+ APL_FIFO_FULL_IN : in std_logic;
+ APL_SHORT_TRANSFER_OUT : out std_logic;
+ APL_DTYPE_OUT : out std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
+ APL_SEND_OUT : out std_logic;
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ APL_DATA_IN : in std_logic_vector (47 downto 0);
+ APL_TYP_IN : in std_logic_vector (2 downto 0);
+ APL_DATAREADY_IN : in std_logic;
+ APL_READ_OUT : out std_logic;
+ APL_RUN_IN : in std_logic;
+ APL_SEQNR_IN : in std_logic_vector (7 downto 0);
+ OLD_T : in std_logic;
+ OLD_TS : in std_logic;
+ OLD_TD : in std_logic_vector (3 downto 0);
+ OLD_TB : out std_logic;
+ OLD_TE : out std_logic);
end component;
-
+
+ -----------------------------------------------------------------------------
+ -- auxiliar component for simulations
+ -----------------------------------------------------------------------------
component trb_reply
port (
SEND_OUT : in std_logic;
-- Generate CLK
-- CLK <= not CLK after PERIOD/8 when SIM_END = false else '0';
CLK <= not CLK after 5 ns; -- 100 MHz
--- clock: process
--- begin -- process clock
--- end process clock;
-- Instantiate the block under test
- uut_1 : dudu
+ uut_lvl1: trb_net_old_to_new
+ generic map (
+ TRIGGER_LEVEL => 1)
port map (
- CLK => CLK,
- RESET => RESET,
- APL_DATA_OUT => APL_DATA_OUT_LVL1,
- APL_WRITE_OUT => APL_WRITE_OUT_LVL1,
- APL_FIFO_FULL_IN => APL_FIFO_FULL_IN_LVL1,
- APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_OUT_LVL1,
- APL_DTYPE_OUT => APL_DTYPE_OUT_LVL1,
- APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT_LVL1,
- APL_SEND_OUT => APL_SEND_OUT_LVL1,
- APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_OUT_LVL1,
- APL_DATA_IN => APL_DATA_IN_LVL1,
- APL_TYP_IN => APL_TYP_IN_LVL1,
- APL_DATAREADY_IN => APL_DATAREADY_IN_LVL1,
- APL_READ_OUT => APL_READ_OUT_LVL1,
- APL_RUN_IN => APL_RUN_IN_LVL1,
- APL_SEQNR_IN => APL_SEQNR_IN_LVL1,
- OLD_T => OLD_T_LVL1,
- OLD_TS => OLD_TS_LVL1,
- OLD_TD => OLD_TD_LVL1,
- OLD_TB => OLD_TB_LVL1,
- OLD_TE => OLD_TE_LVL1,
- APL_DATA_OUT_LVL2 => APL_DATA_OUT_LVL2,
- APL_WRITE_OUT_LVL2 => APL_WRITE_OUT_LVL2,
- APL_SHORT_TRANSFER_OUT_LVL2 => APL_SHORT_TRANSFER_OUT_LVL2,
- APL_DTYPE_OUT_LVL2 => APL_DTYPE_OUT_LVL2,
- APL_ERROR_PATTERN_OUT_LVL2 => APL_ERROR_PATTERN_OUT_LVL2,
- APL_SEND_OUT_LVL2 => APL_SEND_OUT_LVL2,
- APL_TARGET_ADDRESS_OUT_LVL2 => APL_TARGET_ADDRESS_OUT_LVL2,
- APL_DATA_IN_LVL2 => APL_DATA_IN_LVL2,
- APL_DATAREADY_IN_LVL2 => APL_DATAREADY_IN_LVL2,
- APL_READ_OUT_LVL2 => APL_READ_OUT_LVL2,
- APL_RUN_IN_LVL2 => APL_RUN_IN_LVL2,
- APL_SEQNR_IN_LVL2 => APL_SEQNR_IN_LVL2,
- OLD_T_LVL2 => OLD_T_LVL2,
- OLD_TS_LVL2 => OLD_TS_LVL2,
- OLD_TD_LVL2 => OLD_TD_LVL2,
- OLD_TB_LVL2 => OLD_TB_LVL2,
- OLD_TE_LVL2 => OLD_TE_LVL2);
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_OUT_LVL1,
+ APL_WRITE_OUT => APL_WRITE_OUT_LVL1,
+ APL_FIFO_FULL_IN => APL_FIFO_FULL_IN_LVL1,
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_OUT_LVL1,
+ APL_DTYPE_OUT => APL_DTYPE_OUT_LVL1,
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT_LVL1,
+ APL_SEND_OUT => APL_SEND_OUT_LVL1,
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_OUT_LVL1,
+ APL_DATA_IN => APL_DATA_IN_LVL1,
+ APL_TYP_IN => APL_TYP_IN_LVL1,
+ APL_DATAREADY_IN => APL_DATAREADY_IN_LVL1,
+ APL_READ_OUT => APL_READ_OUT_LVL1,
+ APL_RUN_IN => APL_RUN_IN_LVL1,
+ APL_SEQNR_IN => APL_SEQNR_IN_LVL1,
+ OLD_T => OLD_T_LVL1,
+ OLD_TS => OLD_TS_LVL1,
+ OLD_TD => OLD_TD_LVL1,
+ OLD_TB => OLD_TB_LVL1,
+ OLD_TE => OLD_TE_LVL1);
+
+ uut_lvl2: trb_net_old_to_new
+ generic map (
+ TRIGGER_LEVEL => 2)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_OUT_LVL2,
+ APL_WRITE_OUT => APL_WRITE_OUT_LVL2,
+ APL_FIFO_FULL_IN => '0',
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_OUT_LVL2,
+ APL_DTYPE_OUT => APL_DTYPE_OUT_LVL2,
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT_LVL2,
+ APL_SEND_OUT => APL_SEND_OUT_LVL2,
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_OUT_LVL2,
+ APL_DATA_IN => (others => '0'),
+ APL_TYP_IN => (others => '0'),
+ APL_DATAREADY_IN => APL_DATAREADY_IN_LVL2,
+ APL_READ_OUT => APL_READ_OUT_LVL2,
+ APL_RUN_IN => APL_RUN_IN_LVL2,
+ APL_SEQNR_IN => APL_SEQNR_IN_LVL2,
+ OLD_T => OLD_T_LVL2,
+ OLD_TS => OLD_TS_LVL2,
+ OLD_TD => OLD_TD_LVL2,
+ OLD_TB => OLD_TB_LVL2,
+ OLD_TE => OLD_TE_LVL2);
+
trb_LVL1 : trb_reply
port map (
SEND_OUT => APL_SEND_OUT_LVL1,
READ_OUT => APL_READ_OUT_LVL1,
RUN_IN => APL_RUN_IN_LVL1,
SEQNR_IN => APL_SEQNR_IN_LVL1);
+
trb_LVL2 : trb_reply
port map (
SEND_OUT => APL_SEND_OUT_LVL2,
jspc29 / trbnet.git / commitdiff