tidy-up

diff --git a/releases/tdc_v2.1.4/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.1.4/trb3_periph_32PinAddOn.vhd
index 056c81da20a24157da78fef8b96ed47e58d06a24..255a911740b2c5da4c27e857676c3cfacebe5860 100644 (file)
--- a/releases/tdc_v2.1.4/trb3_periph_32PinAddOn.vhd
+++ b/releases/tdc_v2.1.4/trb3_periph_32PinAddOn.vhd
@@ -316,12 +316,6 @@ begin
       LOCK  => pll_lock
       );
 
-  --pll_calibration: entity work.pll_in125_out100
-  --  port map (
-  --    CLK   => CLK_GPLL_LEFT,
-  --    CLKOP => osc_int,
-  --    LOCK  => open);
-  
   pll_calibration: entity work.pll_in125_out33
     port map (
       CLK   => CLK_GPLL_LEFT,

diff --git a/releases/tdc_v2.1.6/TDC_record.vhd b/releases/tdc_v2.1.6/TDC_record.vhd
index 7645f3446a865a936470f6a813c54d52db4e103a..11c476e7ca63bfc04943e977e1a21ceebb0d1717 100644 (file)
--- a/releases/tdc_v2.1.6/TDC_record.vhd
+++ b/releases/tdc_v2.1.6/TDC_record.vhd
@@ -17,40 +17,20 @@ entity TDC_record is
     DEBUG          : integer range 0 to 1  := c_NO;
     SIMULATION     : integer range 0 to 1  := c_NO);
   port (
-    RESET          : in  std_logic;
-    CLK_TDC        : in  std_logic;
-    CLK_READOUT    : in  std_logic;
-    REFERENCE_TIME : in  std_logic;
-    HIT_IN         : in  std_logic_vector(CHANNEL_NUMBER-1 downto 1);
-    HIT_CAL_IN     : in  std_logic;
---Readout
-    READOUT_RX     : in  READOUT_RX;
-    READOUT_TX     : out READOUT_TX;
-
----- Trigger signals from handler
---    TRG_DATA_VALID_IN     : in  std_logic                     := '0';
---    VALID_TIMING_TRG_IN   : in  std_logic                     := '0';
---    VALID_NOTIMING_TRG_IN : in  std_logic                     := '0';
---    INVALID_TRG_IN        : in  std_logic                     := '0';
---    TMGTRG_TIMEOUT_IN     : in  std_logic                     := '0';
---    SPIKE_DETECTED_IN     : in  std_logic                     := '0';
---    MULTI_TMG_TRG_IN      : in  std_logic                     := '0';
---    SPURIOUS_TRG_IN       : in  std_logic                     := '0';
-----
---    TRG_NUMBER_IN         : in  std_logic_vector(15 downto 0) := (others => '0');
---    TRG_CODE_IN           : in  std_logic_vector(7 downto 0)  := (others => '0');
---    TRG_INFORMATION_IN    : in  std_logic_vector(23 downto 0) := (others => '0');
---    TRG_TYPE_IN           : in  std_logic_vector(3 downto 0)  := (others => '0');
-----Response to handler
---    TRG_RELEASE_OUT       : out std_logic;
---    TRG_STATUSBIT_OUT     : out std_logic_vector(31 downto 0);
---    DATA_OUT              : out std_logic_vector(31 downto 0);
---    DATA_WRITE_OUT        : out std_logic;
---    DATA_FINISHED_OUT     : out std_logic;
---
-    LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
+    RESET              : in  std_logic;
+    CLK_TDC            : in  std_logic;
+    CLK_READOUT        : in  std_logic;
+    REFERENCE_TIME     : in  std_logic;
+    HIT_IN             : in  std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+    HIT_CAL_IN         : in  std_logic;
+    --Readout
+    READOUT_RX         : in  READOUT_RX;
+    READOUT_TX         : out READOUT_TX;
+    --Slow Control
     BUS_RX             : in  CTRLBUS_RX;
-    BUS_TX             : out CTRLBUS_TX
+    BUS_TX             : out CTRLBUS_TX;
+    --Debug
+    LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0)
     );
 end TDC_record;
 
@@ -720,20 +700,6 @@ begin
       DATA_IN  => ch_level_hit_number,
       DATA_OUT => open);
 
-  --TheHitCounterBus : BusHandler
-  --  generic map (
-  --    BUS_LENGTH => CHANNEL_NUMBER-1)
-  --  port map (
-  --    RESET            => reset_rdo,
-  --    CLK              => CLK_READOUT,
-  --    DATA_IN          => ch_level_hit_number,
-  --    READ_EN_IN       => HCB_READ_EN_IN,
-  --    WRITE_EN_IN      => HCB_WRITE_EN_IN,
-  --    ADDR_IN          => HCB_ADDR_IN,
-  --    DATA_OUT         => HCB_DATA_OUT,
-  --    DATAREADY_OUT    => HCB_DATAREADY_OUT,
-  --    UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT);
-
   ch_level_hit_number(0)(31)          <= REFERENCE_TIME                          when rising_edge(CLK_READOUT);
   ch_level_hit_number(0)(30 downto 0) <= std_logic_vector(ch_hit_detect_cntr(0)) when rising_edge(CLK_READOUT);
   GenHitDetectNumber : for i in 1 to CHANNEL_NUMBER-1 generate
@@ -753,20 +719,6 @@ begin
       DATA_IN  => status_registers_bus,
       DATA_OUT => open);
 
-  --TheStatusRegistersBus : BusHandler
-  --  generic map (
-  --    BUS_LENGTH => STATUS_REG_NR - 1)
-  --  port map (
-  --    RESET            => reset_rdo,
-  --    CLK              => CLK_READOUT,
-  --    DATA_IN          => status_registers_bus,
-  --    READ_EN_IN       => SRB_READ_EN_IN,
-  --    WRITE_EN_IN      => SRB_WRITE_EN_IN,
-  --    ADDR_IN          => SRB_ADDR_IN,
-  --    DATA_OUT         => SRB_DATA_OUT,
-  --    DATAREADY_OUT    => SRB_DATAREADY_OUT,
-  --    UNKNOWN_ADDR_OUT => SRB_UNKNOWN_ADDR_OUT);
-
   -- basic info
   status_registers_bus(0)(3 downto 0)   <= readout_debug(3 downto 0);  -- rd_fsm
   status_registers_bus(0)(7 downto 4)   <= readout_debug(7 downto 4);  -- wr_fsm
@@ -819,22 +771,6 @@ begin
       DATA_IN  => ch_200_debug,
       DATA_OUT => open);
 
-  --TheChannelDebugBus : BusHandler
-  --  generic map (
-  --    BUS_LENGTH => CHANNEL_NUMBER - 1)
-  --  port map (
-  --    RESET            => reset_rdo,
-  --    CLK              => CLK_READOUT,
-  --    DATA_IN          => ch_200_debug,
-  --    READ_EN_IN       => CDB_READ_EN_IN,
-  --    WRITE_EN_IN      => CDB_WRITE_EN_IN,
-  --    ADDR_IN          => CDB_ADDR_IN,
-  --    DATA_OUT         => CDB_DATA_OUT,
-  --    DATAREADY_OUT    => CDB_DATAREADY_OUT,
-  --    UNKNOWN_ADDR_OUT => CDB_UNKNOWN_ADDR_OUT);
-
-
-
 -------------------------------------------------------------------------------
 -- Debug
 -------------------------------------------------------------------------------