--Begin of design configuration
------------------------------------------------------------------------------
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 1000; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
constant USE_EXTERNAL_CLOCK : integer := c_NO;
- constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
+ constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
--set to 0 for backplane serdes, set to 3 for front SFP serdes
constant SERDES_NUM : integer := 3;
- constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_UART : integer := c_NO;
constant INCLUDE_SPI : integer := c_YES;
- constant INCLUDE_LCD : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
--input monitor and trigger generation logic
------------------------------------------------------------------------------
type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
- constant LCD_DATA : data_t := (
- x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
- x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
- x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
-
- x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
- x"0a",
- x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
- x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
- x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
- others => x"00");
+ constant LCD_DATA : data_t := ( others => x"00");
------------------------------------------------------------------------------
TOPNAME => "trb3sc_adc",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.7_x64',
-synplify_path => '/d/jspc29/lattice/synplify/L-2016.03/',
+lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
+synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
+# lattice_path => '/d/jspc29/lattice/diamond/3.7_x64',
+# synplify_path => '/d/jspc29/lattice/synplify/L-2016.03/',
# synplify_path => '/d/jspc29/lattice/synplify/J-2015.03-SP1/',
# synplify_path => '/d/jspc29/lattice/synplify/I-2013.09-SP1/',
# synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
-l 5
-y
-s 12
--t 1
+-t 2
-c 1
-e 2
-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
#Basic Infrastructure
add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
-#add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out40.vhd"
-add_file -vhdl -lib work "../../trb3/base/cores/pll_in240_out40.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out40.vhd"
+#add_file -vhdl -lib work "../../trb3/base/cores/pll_in240_out40.vhd"
add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib "work" "../../trb3/base/cores/dqsinput_5x5.vhd"
add_file -vhdl -lib "work" "../../trb3/base/cores/fifo_cdt_200_50.vhd"
add_file -vhdl -lib "work" "../../trb3/ADC/cores/mulacc2.vhd"
+add_file -vhdl -lib "work" "../../trb3/ADC/cores/mulaccsub3.vhd"
add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_package.vhd"
add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_processor.vhd"
add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_ad9219.vhd"
NET_CLK_FULL_IN => med2int(0).clk_full,
NET_CLK_HALF_IN => med2int(0).clk_half,
RESET_FROM_NET => med2int(0).stat_op(13),
+ SEND_RESET_IN => med2int(0).stat_op(15),
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
CTRL_DEBUG => open
);
-
--- THE_MEDIA_INTERFACE_OLD : trb_net16_med_ecp3_sfp
--- generic map(
--- SERDES_NUM => 0, --number of serdes in quad
--- EXT_CLOCK => c_NO, --use internal clock
--- USE_200_MHZ => c_YES, --run on 200 MHz clock
--- USE_125_MHZ => c_NO,
--- USE_CTC => c_YES
--- )
--- port map(
--- CLK => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- CLK_EN => '1',
--- --Internal Connection
--- MED_DATA_IN => int2med(0).data,
--- MED_PACKET_NUM_IN => int2med(0).packet_num,
--- MED_DATAREADY_IN => int2med(0).dataready,
--- MED_READ_OUT => med2int(0).tx_read,
--- MED_DATA_OUT => med2int(0).data,
--- MED_PACKET_NUM_OUT => med2int(0).packet_num,
--- MED_DATAREADY_OUT => med2int(0).dataready,
--- MED_READ_IN => '1',
--- REFCLK2CORE_OUT => open,
--- --SFP Connection
--- SD_RXD_P_IN => s(0),
--- SD_RXD_N_IN => s(1),
--- SD_TXD_P_OUT => s(2),
--- SD_TXD_N_OUT => s(3),
--- SD_REFCLK_P_IN => open,
--- SD_REFCLK_N_IN => open,
--- SD_PRSNT_N_IN => SFP_MOD0(0),
--- SD_LOS_IN => SFP_LOS(0),
--- SD_TXDIS_OUT => SFP_TX_DIS(0),
--- -- Status and control port
--- STAT_OP => med2int(0).stat_op,
--- CTRL_OP => int2med(0).ctrl_op,
--- STAT_DEBUG => med_stat_debug(63 downto 0),
--- CTRL_DEBUG => (others => '0')
--- );
-
SFP_TX_DIS(0) <= '1';
gen_sfp_con : if SERDES_NUM = 3 generate
sfp_los_i <= SFP_LOS(1);
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 12,
- DATA_BUFFER_DEPTH => 10,
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**10-511,
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
gen_reallogic : if USE_DUMMY_READOUT = 0 generate
THE_ADC : entity work.adc_handler
generic map(
- IS_TRB3 = 0
+ IS_TRB3 => 0
)
port map(
CLK => clk_sys,
- CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc,
+ CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc, --not used
CLK_RAW_LEFT => CLK_CORE_PLL_LEFT,
CLK_RAW_RIGHT=> CLK_CORE_PLL_RIGHT,
end generate;
- THE_ADC_REF : entity work.pll_in240_out40
+ THE_ADC_REF : entity work.pll_in200_out40
port map(
CLK => CLK_CORE_PCLK,
CLKOP => P_CLOCK,
--Header
HEADER_IO => HDR_IO,
--LCD
- LCD_DATA_IN => lcd_data,
+ LCD_DATA_IN => (others => '0'),
--ADC
ADC_CS => ADC_CS,
ADC_MOSI => ADC_DIN,
case spi_cs(2 downto 0) is
when b"110" =>
FPGA_CS <= b"00";
+ FPGA_SCK(0) <= spi_clk(0);
+ FPGA_SDI(0) <= spi_mosi(0);
when b"101" =>
FPGA_CS <= b"01";
+ FPGA_SCK(0) <= spi_clk(1);
+ FPGA_SDI(0) <= spi_mosi(1);
when b"011" =>
FPGA_CS <= b"10";
+ FPGA_SCK(0) <= spi_clk(2);
+ FPGA_SDI(0) <= spi_mosi(2);
when others =>
FPGA_CS <= b"11";
+ FPGA_SCK(0) <= '1';
+ FPGA_SDI(0) <= '0';
end case;
end process FPGA_CS_mux;
- FPGA_SCK(0) <= spi_clk(0) when spi_cs(2 downto 0) /= b"111" else '1';
- FPGA_SDI(0) <= spi_mosi(0) when spi_cs(2 downto 0) /= b"111" else '0';
spi_miso(0) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0';
spi_miso(1) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0';
spi_miso(2) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0';
SPI_ADC_SDIO <= spi_mosi(3) when spi_cs(3) = '0' else adcspi_ctrl(5);
FPGA_SCK(1) <= '0' when spi_cs(3) = '0' else adcspi_ctrl(6); --CSB
- LMK_CLK <= spi_clk(4) when spi_cs(5 downto 4) /= b"11" else '1' ;
- LMK_DATA <= spi_mosi(4) when spi_cs(5 downto 4) /= b"11" else '0' ;
+ LMK_CLK <= (spi_clk(4) and not spi_cs(4)) or (spi_clk(5) and not spi_cs(5)) or (spi_cs(4) and spi_cs(5));
+ LMK_DATA <= (spi_mosi(4) and not spi_cs(4)) or (spi_mosi(5) and not spi_cs(5));
LMK_LE_1 <= spi_cs(4); -- active low
LMK_LE_2 <= spi_cs(5); -- active low
-- BACK_LVDS <= (others => '0');
-- BACK_3V3 <= (others => 'Z');
-
----------------------------------------------------------------------------
--- LCD Data to display
----------------------------------------------------------------------------
- lcd_data(15 downto 0) <= timer.network_address;
- lcd_data(47 downto 16) <= timer.microsecond;
- lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
- lcd_data(511 downto 80) <= (others => '0');
-
+
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
jspc29 / trb3sc.git / commitdiff