Changes the pinout (and some of the code) of the dirich5d_piggy to make it compatible...

The LVDS output pin-pair of channel 5 was changed to a true-LVDS pair, and one more pin was declared. An input signal was declared in the VHDL code.

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf
index 5d413252bc51eb5b1de266446be6be97a2b1b6da..e83209bbbfd2a0cef8e6ccc606fd4748a55f33b0 100644 (file)
--- a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf
@@ -1,13 +1,15 @@
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
-LOCATE COMP "IN_MISC1" SITE "G5" ;
-IOBUF PORT "IN_MISC1" IO_TYPE=LVDS25 ;
+LOCATE COMP "IN_MISC[1]" SITE "T11" ;
+LOCATE COMP "IN_MISC[2]" SITE "N10" ;
+LOCATE COMP "OUT_MISC1" SITE "F7" ;
+IOBUF PORT "OUT_MISC1" IO_TYPE=LVDS25 ;
 LOCATE COMP "PIGGY_CS" SITE "T15" ;
 LOCATE COMP "TRIG_OUT[1]" SITE "F9" ;
 LOCATE COMP "TRIG_OUT[2]" SITE "C12" ;
 LOCATE COMP "TRIG_OUT[3]" SITE "B13" ;
 LOCATE COMP "TRIG_OUT[4]" SITE "B11" ;
-LOCATE COMP "TRIG_OUT[5]" SITE "A9" ;
+LOCATE COMP "TRIG_OUT[5]" SITE "F8" ;
 LOCATE COMP "TRIG_OUT[6]" SITE "B7" ;
 LOCATE COMP "TRIG_OUT[7]" SITE "A5" ;
 LOCATE COMP "TRIG_OUT[8]" SITE "C4" ;
@@ -23,7 +25,7 @@ IOBUF PORT "TRIG_OUT[1]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[2]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[3]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[4]" IO_TYPE=LVDS25 ;
-IOBUF PORT "TRIG_OUT[5]" IO_TYPE=LVDS25E ;
+IOBUF PORT "TRIG_OUT[5]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[6]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[7]" IO_TYPE=LVDS25 ;
 IOBUF PORT "TRIG_OUT[8]" IO_TYPE=LVDS25 ;

diff --git a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd
index 0785e4c627c7eea42eca72da73b1af5ffd4a4f66..e9c6593f140fdac1a6b7bcb6674b8f88e133545a 100644 (file)
--- a/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd
+++ b/dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd
@@ -9,7 +9,8 @@ use machXO3lf.all;
 
 entity top is
   PORT (
-    IN_MISC1    : in    std_logic;
+    IN_MISC     : in    std_logic_vector(2 downto 1);
+    OUT_MISC1   : out   std_logic;
     TRIG_OUT    : out   std_logic_vector(16 downto 1);
     TRIG_IN     : in    std_logic_vector(16 downto 1);
     PIGGY_CS    : out   std_logic
@@ -50,7 +51,7 @@ internal_oscillator: OSCH
   );    
 
 
-i_in_misc1 <= IN_MISC1;
+i_in_misc1 <= IN_MISC(1);
 
 PIGGY_CS <= i_in_misc1;
 TRIG_OUT(16 downto 1) <= TRIG_IN(16 downto 1);