changed hdmi ports

diff --git a/mimosis/config.vhd b/mimosis/config.vhd
index 5374934e43a88833193a2a8ca1b8955d38831711..cd1c9d363b0b0691a5adb5329f95f293b90eaae6 100644 (file)
--- a/mimosis/config.vhd
+++ b/mimosis/config.vhd
@@ -53,7 +53,7 @@ package config is
     constant INCLUDE_SPI            : integer  := c_NO;
     constant INCLUDE_ADC            : integer  := c_YES; 
     constant INCLUDE_I2C            : integer  := c_YES;
-    constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO;
+    constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES;
 
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;

diff --git a/mimosis/par.p2t b/mimosis/par.p2t
index f9898477d58fb4e982d3e657cb048d8d1e3db24f..2ce03814717be0456d58e05b92e61d59f03108c2 100644 (file)
--- a/mimosis/par.p2t
+++ b/mimosis/par.p2t
@@ -4,7 +4,7 @@
 #-m nodelist.txt       # Controlled by the compile.pl script.
 #-n 1                          # Controlled by the compile.pl script.
 -s 10
--t 6
+-t 10
 -c 2
 -e 2
 -i 10

diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj
index df0bfb1fe85a56ac9310c6a85c001c8b7611197a..d9a4295cd77eff33f61b6757aef543dac086f6c1 100644 (file)
--- a/mimosis/trb5sc_mimosis.prj
+++ b/mimosis/trb5sc_mimosis.prj
@@ -131,6 +131,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"

diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd
index 1f7e0ceae6e6e26ac1fd4677e4849472eccc5c74..9814b6631b6d68bdcc8bdd06c1b0bf8f89d0db2d 100644 (file)
--- a/mimosis/trb5sc_mimosis.vhd
+++ b/mimosis/trb5sc_mimosis.vhd
@@ -42,7 +42,7 @@ entity trb5sc_mimosis is
     RJ : inout std_logic_vector(3 downto 0);\r
     H1 : inout std_logic_vector(4 downto 0);\r
     H2 : inout std_logic_vector(4 downto 0);\r
-    H3 : inout std_logic_vector(4 downto 0);\r
+    H3 : inout std_logic_vector(3 downto 0);\r
     H4 : inout std_logic_vector(4 downto 0);\r
     H5 : inout std_logic_vector(3 downto 0);\r
     H6 : inout std_logic_vector(4 downto 0);\r
@@ -200,8 +200,12 @@ begin
       CLKOS3=> clk_80\r
       );\r
 \r
-  H5(3) <= clk_320;\r
-  RJ(0) <= clk_40;\r
+  H3(3) <= clk_320;\r
+\r
+  -- For IPHC Proxy\r
+  -- RJ(0) <= clk_40;\r
+  -- For IKF Proxy\r
+  H1(4) <= clk_40;\r
 \r
 ---------------------------------------------------------------------------\r
 -- TrbNet Uplink\r
@@ -210,7 +214,7 @@ begin
   THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
     generic map(\r
       SERDES_NUM    => SERDES_NUM,\r
-      USE_NEW_ECP5_RESET => 0,\r
+      USE_NEW_ECP5_RESET => 1,\r
       IS_SYNC_SLAVE => c_YES\r
       )\r
     port map(\r
@@ -330,7 +334,7 @@ begin
       BUS_RX(2) => bustc_rx,            --Clock switch\r
       BUS_RX(3) => busmimosis_rx,\r
       BUS_RX(4) => busi2c_rx,\r
-      BUS_RX(5) => busgbtcore_rx,\r
+      -- BUS_RX(5) => busgbtcore_rx,\r
       -- BUS_RX(5) => busgbeip_rx,\r
       -- BUS_RX(6) => busgbereg_rx,\r
       -- BUS_RX(7) => busfwd_rx,\r
@@ -339,7 +343,7 @@ begin
       BUS_TX(2) => bustc_tx,\r
       BUS_TX(3) => busmimosis_tx,\r
       BUS_TX(4) => busi2c_tx,\r
-      BUS_TX(5) => busgbtcore_tx,\r
+      -- BUS_TX(5) => busgbtcore_tx,\r
       -- BUS_TX(5) => busgbeip_tx,\r
       -- BUS_TX(6) => busgbereg_tx,\r
       -- BUS_TX(7) => busfwd_tx,\r
@@ -377,6 +381,8 @@ begin
       --HEADER_IO         => open,\r
       HEADER_IO(7) => HDR_IO(6),\r
       HEADER_IO(8) => HDR_IO(7),\r
+      HEADER_IO(9) => HDR_IO(8), -- 8, RX\r
+      HEADER_IO(10) => HDR_IO(9), -- 9, TX\r
       ADDITIONAL_REG    => add_reg,\r
       --ADC\r
       ADC_CS            => ADC_NCS,\r
@@ -407,6 +413,8 @@ begin
   -- COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
   -- COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
 \r
+  PIN(5) <= '0' when (add_reg(30) = '0') else 'Z';\r
+\r
   FLASH_HOLD <= '1';\r
   FLASH_WP   <= '1';\r
 \r
@@ -449,7 +457,7 @@ begin
   MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
   MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
 \r
-  H5(1)  <= i2c_reg_5_40(0);  --MIMOSIS_SYNC\r
+  H3(1)  <= i2c_reg_5_40(0);  --MIMOSIS_SYNC\r
   PIN(1) <= i2c_reg_5_40(4);  --MIMOSIS_START\r
   PIN(2) <= i2c_reg_5_40(8);  --MIMOSIS_RESET\r
 \r
@@ -549,6 +557,8 @@ begin
   LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
   LED_ADDON_SFP_ORANGE(1) <= '0';\r
 \r
+\r
+\r
 -----------------------------------------------------------------------------\r
 ---- GbE\r
 -----------------------------------------------------------------------------\r
@@ -688,38 +698,38 @@ begin
 ---------------------------------------------------------------------------\r
 -- Output stage\r
 ---------------------------------------------------------------------------\r
-  THE_OUT : entity work.testout\r
-    port map(\r
-      clkout => open,\r
-      refclk => clk_160,\r
-      reset  => reset_i,\r
-      data   => out_data,\r
-      data_cflag => open,\r
-      data_direction => (others => '0'),\r
-      data_loadn     => (others => '1'),\r
-      data_move      => (others => '0'),\r
-      dout           => out_i\r
-      );\r
-\r
-  PROC_OUT : process\r
-    variable cnt : integer range 0 to 7;\r
-  begin\r
-    wait until rising_edge(clk_160);\r
-    cnt := cnt + 1;\r
-    case cnt is\r
-      when 0 => out_data <= x"ffff";\r
-      when 1 => out_data <= x"ffff";\r
-      when 2 => out_data <= x"ffff";\r
-      when 3 => out_data <= x"0000";\r
-      when 4 => out_data <= x"5555";\r
-      when 5 => out_data <= x"5555";\r
-      when 6 => out_data <= x"5555";\r
-      when 7 => out_data <= x"5555";\r
-    end case;\r
-  end process;\r
-\r
-  H3(3 downto 0) <= out_i(3 downto 0);\r
-  H4(3 downto 0) <= out_i(7 downto 4);\r
+  -- THE_OUT : entity work.testout\r
+  --   port map(\r
+  --     clkout => open,\r
+  --     refclk => clk_160,\r
+  --     reset  => reset_i,\r
+  --     data   => out_data,\r
+  --     data_cflag => open,\r
+  --     data_direction => (others => '0'),\r
+  --     data_loadn     => (others => '1'),\r
+  --     data_move      => (others => '0'),\r
+  --     dout           => out_i\r
+  --     );\r
+\r
+  -- PROC_OUT : process\r
+  --   variable cnt : integer range 0 to 7;\r
+  -- begin\r
+  --   wait until rising_edge(clk_160);\r
+  --   cnt := cnt + 1;\r
+  --   case cnt is\r
+  --     when 0 => out_data <= x"ffff";\r
+  --     when 1 => out_data <= x"ffff";\r
+  --     when 2 => out_data <= x"ffff";\r
+  --     when 3 => out_data <= x"0000";\r
+  --     when 4 => out_data <= x"5555";\r
+  --     when 5 => out_data <= x"5555";\r
+  --     when 6 => out_data <= x"5555";\r
+  --     when 7 => out_data <= x"5555";\r
+  --   end case;\r
+  -- end process;\r
+\r
+  -- H3(3 downto 0) <= out_i(3 downto 0);\r
+  -- H4(3 downto 0) <= out_i(7 downto 4);\r
 \r
 \r
 ---------------------------------------------------------------------------\r

diff --git a/pinout/trb5sc_hdmi.lpf b/pinout/trb5sc_hdmi.lpf
index 5d7a426f5d1ed64f87a9cfba0deaf6bea87ab795..6c89d07bcdf29487b56bd90102a11d3632a5222d 100644 (file)
--- a/pinout/trb5sc_hdmi.lpf
+++ b/pinout/trb5sc_hdmi.lpf
@@ -88,8 +88,10 @@ LOCATE COMP "H5[3]" SITE "R32" ;    #was "FE_DIFF[6]"
 LOCATE COMP "H7[3]" SITE "W30" ;    #was "FE_DIFF[7]" 
 #LOCATE COMP "H5[4]" SITE "T32" ;    #was "FE_DIFF[8]" 
 
-LOCATE COMP "MIMOSIS_SCL" SITE "U32" ;    #was "FE_DIFF[8]" 
-LOCATE COMP "MIMOSIS_SDA" SITE "T32" ;    #was "FE_DIFF[8]" 
+# LOCATE COMP "MIMOSIS_SCL" SITE "U32" ;    #was "FE_DIFF[8]"
+# LOCATE COMP "MIMOSIS_SDA" SITE "T32" ;    #was "FE_DIFF[8]"
+LOCATE COMP "MIMOSIS_SCL" SITE "C2" ;    #was "FE_DIFF[8]"
+LOCATE COMP "MIMOSIS_SDA" SITE "B1" ;    #was "FE_DIFF[8]"
 IOBUF  PORT  "MIMOSIS_SCL"      IO_TYPE=LVCMOS25 ;
 IOBUF  PORT  "MIMOSIS_SDA"      IO_TYPE=LVCMOS25 ;