signal dbg_ft : std_logic_vector(63 downto 0);
signal dbg_q : std_logic_vector(15 downto 0);
signal make_reset : std_logic;
+ signal frame_pause : std_logic_vector(31 downto 0);
begin
reset_sync : process(GSR_N, CLK_SYS_IN)
CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
- CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
- CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+ CFG_AUTO_THROTTLE_IN => '0', --CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
TSM_HADDR_OUT => open, --mac_haddr,
TSM_HDATA_OUT => open, --mac_hdataout,
TSM_HCS_N_OUT => open, --mac_hcs,
FLAGS_OFFSET_IN => fc_flags_offset,
TTL_IN => fc_ttl,
PROTOCOL_IN => fc_protocol,
- FRAME_DELAY_IN => (others => '0'),
+ FRAME_DELAY_IN => frame_pause, --(others => '0'),
RD_CLK => CLK_125_IN,
FT_DATA_OUT => ft_data,
FT_TX_EMPTY_OUT => ft_tx_empty,
MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
MONITOR_TX_FRAMES_OUT => monitor_tx_frames
);
+
+ frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
MAC_TX_DATA_OUT <= ft_data(7 downto 0);
mac_rx_write(0) <='0';
mac_rx_eof(0) <= '0';
+
+ wait for 10 us;
+
+-- ETHERNET PAUSE FRAME
+
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '1';
+ -- dest mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"80";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c2";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- src mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- frame type
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"88";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+
+ for empty_b_ctr in 0 to 40 loop
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ end loop;
+ mac_rx_eof(0) <= '1';
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <='0';
+ mac_rx_eof(0) <= '0';
+
wait;
end process testbench_proc;
if rising_edge(CLK_GBE) then
if (load_current_state = IDLE) then
trigger_type <= x"0";
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then
+ --elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then
+ elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
trigger_type <= pc_data(7 downto 4);
else
trigger_type <= trigger_type;
reg_tx_rx_ctrl1(6) <= '1'; -- drop control
reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en
reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast
-reg_tx_rx_ctrl1(3) <= '1'; -- receive pause
+reg_tx_rx_ctrl1(3) <= '0'; -- receive pause
reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS
reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding
reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode