]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
Copied from Nxyter/Start MuPix
authorTobias Weber <webert@kph.uni-mainz.de>
Thu, 1 Aug 2013 14:52:44 +0000 (16:52 +0200)
committerTobias Weber <webert@kph.uni-mainz.de>
Thu, 1 Aug 2013 14:55:17 +0000 (16:55 +0200)
50 files changed:
mupix/.gitignore [new file with mode: 0644]
mupix/compile_GSI.pl [new file with mode: 0755]
mupix/cores/fifo_32_data.ipx [new file with mode: 0644]
mupix/cores/fifo_32_data.lpc [new file with mode: 0644]
mupix/cores/fifo_32_data.vhd [new file with mode: 0644]
mupix/cores/fifo_ts_32to32_dc.ipx [new file with mode: 0644]
mupix/cores/fifo_ts_32to32_dc.lpc [new file with mode: 0644]
mupix/cores/fifo_ts_32to32_dc.vhd [new file with mode: 0644]
mupix/cores/pll_adc_clk192.ipx [new file with mode: 0644]
mupix/cores/pll_adc_clk192.lpc [new file with mode: 0644]
mupix/cores/pll_adc_clk192.vhd [new file with mode: 0644]
mupix/cores/pll_adc_clk32.ipx [new file with mode: 0644]
mupix/cores/pll_adc_clk32.lpc [new file with mode: 0644]
mupix/cores/pll_adc_clk32.vhd [new file with mode: 0644]
mupix/cores/pll_nx_clk250.ipx [new file with mode: 0644]
mupix/cores/pll_nx_clk250.lpc [new file with mode: 0644]
mupix/cores/pll_nx_clk250.vhd [new file with mode: 0644]
mupix/cores/pll_nx_clk256.ipx [new file with mode: 0644]
mupix/cores/pll_nx_clk256.lpc [new file with mode: 0644]
mupix/cores/pll_nx_clk256.vhd [new file with mode: 0644]
mupix/source/adc_spi_master.vhd [new file with mode: 0644]
mupix/source/adc_spi_readbyte.vhd [new file with mode: 0644]
mupix/source/adc_spi_sendbyte.vhd [new file with mode: 0644]
mupix/source/gray_decoder.vhd [new file with mode: 0644]
mupix/source/gray_encoder.vhd [new file with mode: 0644]
mupix/source/level_to_pulse.vhd [new file with mode: 0644]
mupix/source/nx_data_receiver.vhd [new file with mode: 0644]
mupix/source/nx_data_validate.vhd [new file with mode: 0644]
mupix/source/nx_event_buffer.vhd [new file with mode: 0644]
mupix/source/nx_fpga_timestamp.vhd [new file with mode: 0644]
mupix/source/nx_histograms.vhd [new file with mode: 0644]
mupix/source/nx_i2c_master.vhd [new file with mode: 0644]
mupix/source/nx_i2c_readbyte.vhd [new file with mode: 0644]
mupix/source/nx_i2c_sendbyte.vhd [new file with mode: 0644]
mupix/source/nx_i2c_startstop.vhd [new file with mode: 0644]
mupix/source/nx_setup.vhd [new file with mode: 0644]
mupix/source/nx_timer.vhd [new file with mode: 0644]
mupix/source/nx_timestamp_sim.vhd [new file with mode: 0644]
mupix/source/nx_trigger_generator.vhd [new file with mode: 0644]
mupix/source/nx_trigger_handler.vhd [new file with mode: 0644]
mupix/source/nx_trigger_validate.vhd [new file with mode: 0644]
mupix/source/nxyter_components.vhd [new file with mode: 0644]
mupix/source/nxyter_fee_board.vhd [new file with mode: 0644]
mupix/source/nxyter_registers.vhd [new file with mode: 0644]
mupix/source/pulse_to_level.vhd [new file with mode: 0644]
mupix/source/registers.txt [new file with mode: 0644]
mupix/trb3_periph.p2t [new file with mode: 0644]
mupix/trb3_periph.prj [new file with mode: 0644]
mupix/trb3_periph.vhd [new file with mode: 0644]
mupix/trb3_periph_constraints.lpf [new file with mode: 0644]

diff --git a/mupix/.gitignore b/mupix/.gitignore
new file mode 100644 (file)
index 0000000..8507be3
--- /dev/null
@@ -0,0 +1 @@
+version.vhd
diff --git a/mupix/compile_GSI.pl b/mupix/compile_GSI.pl
new file mode 100755 (executable)
index 0000000..7b37ca2
--- /dev/null
@@ -0,0 +1,163 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
+my $lattice_path                 = '/opt/lattice/diamond/2.01/';
+my $synplify_path                = '/opt/synplicity/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+
+
+
+# source the standard lattice environment
+open my $SOURCE, "bash -c 'cd $lattice_path/ispfpga && . ../bin/lin/diamond_env >& /dev/null; env'|" or
+  die "Can't fork: $!";
+while (<$SOURCE>) {
+  if (/^(.*)=(.*)/) {
+    $ENV{$1} = ${2} ;
+  }
+}
+close $SOURCE;
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+       print "\n";
+       $c="cat $TOPNAME.srr | grep \"\@E\"";
+       system($c);
+        print "\n\n";
+       exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+       print "$!";
+       if($op ne "do_not_exit") {
+           exit;
+       }
+    }
+
+    return $r;
+
+}
diff --git a/mupix/cores/fifo_32_data.ipx b/mupix/cores/fifo_32_data.ipx
new file mode 100644 (file)
index 0000000..7199cca
--- /dev/null
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_32_data" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 06 23 23:52:13.976" version="4.8" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="fifo_32_data.lpc" type="lpc" modified="2013 06 23 23:52:12.000"/>
+               <File name="fifo_32_data.vhd" type="top_level_vhdl" modified="2013 06 23 23:52:12.000"/>
+               <File name="fifo_32_data_tmpl.vhd" type="template_vhdl" modified="2013 06 23 23:52:12.000"/>
+               <File name="tb_fifo_32_data_tmpl.vhd" type="testbench_vhdl" modified="2013 06 23 23:52:12.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/fifo_32_data.lpc b/mupix/cores/fifo_32_data.lpc
new file mode 100644 (file)
index 0000000..db39e4e
--- /dev/null
@@ -0,0 +1,45 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=4.8
+ModuleName=fifo_32_data
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/23/2013
+Time=23:52:12
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=1
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+EnECC=0
+EnFWFT=0
diff --git a/mupix/cores/fifo_32_data.vhd b/mupix/cores/fifo_32_data.vhd
new file mode 100644 (file)
index 0000000..df7e846
--- /dev/null
@@ -0,0 +1,837 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 4.8
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe 1 -pf -1 -fill -e 
+
+-- Sun Jun 23 23:52:12 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_32_data is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        WCNT: out  std_logic_vector(10 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic);
+end fifo_32_data;
+
+architecture Structure of fifo_32_data is
+
+    -- internal signal declarations
+    signal invout_2: std_logic;
+    signal invout_1: std_logic;
+    signal rden_i_inv: std_logic;
+    signal invout_0: std_logic;
+    signal cnt_con_inv: std_logic;
+    signal r_nw_inv: std_logic;
+    signal fcnt_en_inv_inv: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal co5: std_logic;
+    signal cnt_con: std_logic;
+    signal co4: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal co0_2: std_logic;
+    signal co1_2: std_logic;
+    signal co2_2: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal co5_1: std_logic;
+    signal wcount_10: std_logic;
+    signal co4_3: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co0_4: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co1_4: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co2_4: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co3_4: std_logic;
+    signal ircount_10: std_logic;
+    signal co5_2: std_logic;
+    signal rcount_10: std_logic;
+    signal co4_4: std_logic;
+    signal scuba_vhi: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal fcnt_en_inv: std_logic;
+    signal r_nw: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_5: std_logic;
+    signal fcount_10: std_logic;
+    signal ae_d: std_logic;
+    signal ae_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component ALEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; LE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component CB2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CON: in  std_logic; CO: out  std_logic; NC0: out  std_logic; 
+            NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_32_data.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_32_data.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t4: AND2
+        port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+    INV_8: INV
+        port map (A=>full_i, Z=>invout_2);
+
+    AND2_t3: AND2
+        port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+    INV_7: INV
+        port map (A=>empty_i, Z=>invout_1);
+
+    AND2_t2: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t1: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_6: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_5: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    AND2_t0: AND2
+        port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+    INV_4: INV
+        port map (A=>wren_i, Z=>invout_0);
+
+    INV_3: INV
+        port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+    INV_2: INV
+        port map (A=>cnt_con, Z=>cnt_con_inv);
+
+    INV_1: INV
+        port map (A=>r_nw, Z=>r_nw_inv);
+
+    INV_0: INV
+        port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
+    pdp_ram_0_0_1: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), 
+            DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), 
+            DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), 
+            DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, 
+            ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0, 
+            ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3, 
+            ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6, 
+            ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9, 
+            CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, 
+            CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rcount_0, 
+            ADB5=>rcount_1, ADB6=>rcount_2, ADB7=>rcount_3, 
+            ADB8=>rcount_4, ADB9=>rcount_5, ADB10=>rcount_6, 
+            ADB11=>rcount_7, ADB12=>rcount_8, ADB13=>rcount_9, 
+            CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), 
+            DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), 
+            DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>Q(12), 
+            DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), DOB16=>Q(16), 
+            DOB17=>Q(17));
+
+    pdp_ram_0_1_0: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  18, 
+        DATA_WIDTH_A=>  18)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>Data(27), DIA10=>Data(28), DIA11=>Data(29), 
+            DIA12=>Data(30), DIA13=>Data(31), DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, 
+            ADA3=>scuba_vlo, ADA4=>wcount_0, ADA5=>wcount_1, 
+            ADA6=>wcount_2, ADA7=>wcount_3, ADA8=>wcount_4, 
+            ADA9=>wcount_5, ADA10=>wcount_6, ADA11=>wcount_7, 
+            ADA12=>wcount_8, ADA13=>wcount_9, CEA=>wren_i, CLKA=>Clock, 
+            OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1, 
+            ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4, 
+            ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7, 
+            ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock, 
+            OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(18), 
+            DOB1=>Q(19), DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), 
+            DOB5=>Q(23), DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), 
+            DOB9=>Q(27), DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), 
+            DOB13=>Q(31), DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    FF_35: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_34: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_33: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_32: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_31: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_30: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_29: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_28: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_27: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_26: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_25: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_24: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_23: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_22: FD1P3DX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_0);
+
+    FF_21: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_20: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_19: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_18: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_17: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_16: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_15: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_14: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_13: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_12: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_11: FD1P3DX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_0);
+
+    FF_10: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_9: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_8: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_7: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_6: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_5: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_4: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_3: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_2: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_1: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_0: FD1S3BX
+        port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
+
+    bdcnt_bctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+    bdcnt_bctr_0: CB2
+        port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, 
+            CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+    bdcnt_bctr_1: CB2
+        port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, 
+            CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+    bdcnt_bctr_2: CB2
+        port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, 
+            CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+    bdcnt_bctr_3: CB2
+        port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, 
+            CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+    bdcnt_bctr_4: CB2
+        port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, 
+            CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+    bdcnt_bctr_5: CB2
+        port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con, 
+            CO=>co5, NC0=>ifcount_10, NC1=>open);
+
+    e_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, 
+            S1=>open);
+
+    e_cmp_0: ALEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, 
+            CI=>cmp_ci, LE=>co0_1);
+
+    e_cmp_1: ALEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+    e_cmp_2: ALEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+    e_cmp_3: ALEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+    e_cmp_4: ALEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+    e_cmp_5: ALEB2
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, 
+            S1=>open);
+
+    g_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, 
+            S1=>open);
+
+    g_cmp_0: AGEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            CI=>cmp_ci_1, GE=>co0_2);
+
+    g_cmp_1: AGEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            CI=>co0_2, GE=>co1_2);
+
+    g_cmp_2: AGEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            CI=>co1_2, GE=>co2_2);
+
+    g_cmp_3: AGEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            CI=>co2_2, GE=>co3_2);
+
+    g_cmp_4: AGEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            CI=>co3_2, GE=>co4_2);
+
+    g_cmp_5: AGEB2
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, 
+            B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, 
+            S1=>open);
+
+    w_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, 
+            S1=>open);
+
+    w_ctr_0: CU2
+        port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_ctr_1: CU2
+        port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_ctr_2: CU2
+        port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_ctr_3: CU2
+        port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_ctr_4: CU2
+        port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_ctr_5: CU2
+        port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1, 
+            NC0=>iwcount_10, NC1=>open);
+
+    r_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, 
+            S1=>open);
+
+    r_ctr_0: CU2
+        port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_ctr_1: CU2
+        port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_ctr_2: CU2
+        port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_ctr_3: CU2
+        port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_ctr_4: CU2
+        port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_ctr_5: CU2
+        port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2, 
+            NC0=>ircount_10, NC1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    ae_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, 
+            S1=>open);
+
+    ae_cmp_0: ALEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv, B1=>r_nw, 
+            CI=>cmp_ci_2, LE=>co0_5);
+
+    ae_cmp_1: ALEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co0_5, LE=>co1_5);
+
+    ae_cmp_2: ALEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co1_5, LE=>co2_5);
+
+    ae_cmp_3: ALEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co2_5, LE=>co3_5);
+
+    ae_cmp_4: ALEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co3_5, LE=>co4_5);
+
+    ae_cmp_5: ALEB2
+        port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co4_5, LE=>ae_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_32_data is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:CB2 use entity ecp3.CB2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/cores/fifo_ts_32to32_dc.ipx b/mupix/cores/fifo_ts_32to32_dc.ipx
new file mode 100644 (file)
index 0000000..a05b4f1
--- /dev/null
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_ts_32to32_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 06 02 03:59:34.210" version="5.4" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="fifo_ts_32to32_dc.lpc" type="lpc" modified="2013 06 02 03:59:31.000"/>
+               <File name="fifo_ts_32to32_dc.vhd" type="top_level_vhdl" modified="2013 06 02 03:59:31.000"/>
+               <File name="fifo_ts_32to32_dc_tmpl.vhd" type="template_vhdl" modified="2013 06 02 03:59:31.000"/>
+               <File name="tb_fifo_ts_32to32_dc_tmpl.vhd" type="testbench_vhdl" modified="2013 06 02 03:59:31.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/fifo_ts_32to32_dc.lpc b/mupix/cores/fifo_ts_32to32_dc.lpc
new file mode 100644 (file)
index 0000000..996fcfb
--- /dev/null
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_ts_32to32_dc
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/02/2013
+Time=03:59:31
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=32
+Width=32
+RDepth=32
+RWidth=32
+regout=1
+CtrlByRdEn=1
+EmpFlg=1
+PeMode=Dynamic - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
diff --git a/mupix/cores/fifo_ts_32to32_dc.vhd b/mupix/cores/fifo_ts_32to32_dc.vhd
new file mode 100644 (file)
index 0000000..8a4c217
--- /dev/null
@@ -0,0 +1,1125 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32 -width 32 -depth 32 -rdata_width 32 -regout -pe 0 -pf -1 -e 
+
+-- Sun Jun  2 03:59:31 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_ts_32to32_dc is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        AmEmptyThresh: in  std_logic_vector(4 downto 0); 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic);
+end fifo_ts_32to32_dc;
+
+architecture Structure of fifo_ts_32to32_dc is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal rcnt_reg_4_inv: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal ffidata_0: std_logic;
+    signal ffidata_1: std_logic;
+    signal ffidata_2: std_logic;
+    signal ffidata_3: std_logic;
+    signal ffidata_4: std_logic;
+    signal ffidata_5: std_logic;
+    signal ffidata_6: std_logic;
+    signal ffidata_7: std_logic;
+    signal ffidata_8: std_logic;
+    signal ffidata_9: std_logic;
+    signal ffidata_10: std_logic;
+    signal ffidata_11: std_logic;
+    signal ffidata_12: std_logic;
+    signal ffidata_13: std_logic;
+    signal ffidata_14: std_logic;
+    signal ffidata_15: std_logic;
+    signal ffidata_16: std_logic;
+    signal ffidata_17: std_logic;
+    signal ffidata_18: std_logic;
+    signal ffidata_19: std_logic;
+    signal ffidata_20: std_logic;
+    signal ffidata_21: std_logic;
+    signal ffidata_22: std_logic;
+    signal ffidata_23: std_logic;
+    signal ffidata_24: std_logic;
+    signal ffidata_25: std_logic;
+    signal ffidata_26: std_logic;
+    signal ffidata_27: std_logic;
+    signal ffidata_28: std_logic;
+    signal ffidata_29: std_logic;
+    signal ffidata_30: std_logic;
+    signal ffidata_31: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal rcnt_reg_5: std_logic;
+    signal empty_i: std_logic;
+    signal full_i: std_logic;
+    signal rRst: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co2: std_logic;
+    signal wcount_5: std_logic;
+    signal co1: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co2_1: std_logic;
+    signal rcount_5: std_logic;
+    signal co1_1: std_logic;
+    signal rcnt_sub_0: std_logic;
+    signal scuba_vhi: std_logic;
+    signal rcnt_sub_1: std_logic;
+    signal rcnt_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal rcnt_sub_3: std_logic;
+    signal rcnt_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal rcnt_sub_5: std_logic;
+    signal co2_2: std_logic;
+    signal rcnt_sub_msb: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_4: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_w4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_4: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal rcnt_reg_0: std_logic;
+    signal rcnt_reg_1: std_logic;
+    signal co0_5: std_logic;
+    signal rcnt_reg_2: std_logic;
+    signal rcnt_reg_3: std_logic;
+    signal co1_5: std_logic;
+    signal rcnt_reg_4: std_logic;
+    signal ae_clrsig: std_logic;
+    signal ae_setsig: std_logic;
+    signal ae_d: std_logic;
+    signal ae_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_32to32_dc.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t15: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_2: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t14: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_1: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t13: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t8: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r4);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
+            AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w4);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
+            AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+    XOR2_t2: XOR2
+        port map (A=>w_gcount_r25, B=>rcount_5, Z=>rcnt_sub_msb);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    INV_0: INV
+        port map (A=>rcnt_reg_4, Z=>rcnt_reg_4_inv);
+
+    AND2_t1: AND2
+        port map (A=>rcnt_reg_5, B=>rcnt_reg_4_inv, Z=>ae_clrsig);
+
+    AND2_t0: AND2
+        port map (A=>rcnt_reg_5, B=>rcnt_reg_4, Z=>ae_setsig);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, 
+            ADW4=>wptr_4, ADW5=>scuba_vlo, ADW6=>scuba_vlo, 
+            ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, 
+            BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, 
+            CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, 
+            CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, 
+            ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, 
+            ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, 
+            ADR9=>rptr_4, ADR10=>scuba_vlo, ADR11=>scuba_vlo, 
+            ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, 
+            DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, 
+            DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24, 
+            DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27, 
+            DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30, 
+            DO13=>ffidata_31, DO14=>open, DO15=>open, DO16=>open, 
+            DO17=>open, DO18=>ffidata_0, DO19=>ffidata_1, 
+            DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4, 
+            DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7, 
+            DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10, 
+            DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13, 
+            DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, 
+            DO35=>ffidata_17);
+
+    FF_100: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_99: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_98: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_97: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_96: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_95: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_94: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_93: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_92: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_91: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_90: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_89: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_88: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_87: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_86: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_85: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_84: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_83: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_82: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_75: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_74: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_73: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_72: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_71: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_70: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_69: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_68: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_67: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_66: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_65: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_64: FD1P3DX
+        port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0));
+
+    FF_63: FD1P3DX
+        port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1));
+
+    FF_62: FD1P3DX
+        port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2));
+
+    FF_61: FD1P3DX
+        port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3));
+
+    FF_60: FD1P3DX
+        port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4));
+
+    FF_59: FD1P3DX
+        port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5));
+
+    FF_58: FD1P3DX
+        port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6));
+
+    FF_57: FD1P3DX
+        port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7));
+
+    FF_56: FD1P3DX
+        port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8));
+
+    FF_55: FD1P3DX
+        port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9));
+
+    FF_54: FD1P3DX
+        port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(10));
+
+    FF_53: FD1P3DX
+        port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(11));
+
+    FF_52: FD1P3DX
+        port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(12));
+
+    FF_51: FD1P3DX
+        port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(13));
+
+    FF_50: FD1P3DX
+        port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(14));
+
+    FF_49: FD1P3DX
+        port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(15));
+
+    FF_48: FD1P3DX
+        port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(16));
+
+    FF_47: FD1P3DX
+        port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(17));
+
+    FF_46: FD1P3DX
+        port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(18));
+
+    FF_45: FD1P3DX
+        port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(19));
+
+    FF_44: FD1P3DX
+        port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(20));
+
+    FF_43: FD1P3DX
+        port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(21));
+
+    FF_42: FD1P3DX
+        port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(22));
+
+    FF_41: FD1P3DX
+        port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(23));
+
+    FF_40: FD1P3DX
+        port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(24));
+
+    FF_39: FD1P3DX
+        port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(25));
+
+    FF_38: FD1P3DX
+        port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(26));
+
+    FF_37: FD1P3DX
+        port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(27));
+
+    FF_36: FD1P3DX
+        port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(28));
+
+    FF_35: FD1P3DX
+        port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(29));
+
+    FF_34: FD1P3DX
+        port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(30));
+
+    FF_33: FD1P3DX
+        port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, 
+            Q=>Q(31));
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_28: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_27: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_20: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_19: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_18: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_16: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_15: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_14: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_13: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_12: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_11: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_10: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_9: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_8: FD1S3DX
+        port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
+
+    FF_7: FD1S3DX
+        port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
+
+    FF_6: FD1S3DX
+        port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
+
+    FF_5: FD1S3DX
+        port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
+
+    FF_4: FD1S3DX
+        port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
+
+    FF_3: FD1S3DX
+        port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
+
+    FF_2: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_1: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_0: FD1S3BX
+        port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    rcnt_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, 
+            B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, 
+            S1=>rcnt_sub_0);
+
+    rcnt_1: FSUB2B
+        port map (A0=>wcount_r1, A1=>w_g2b_xor_cluster_0, B0=>rcount_1, 
+            B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, 
+            S1=>rcnt_sub_2);
+
+    rcnt_2: FSUB2B
+        port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_3, 
+            B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, 
+            S1=>rcnt_sub_4);
+
+    rcnt_3: FSUB2B
+        port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, BI=>co2_2, BOUT=>open, S0=>rcnt_sub_5, 
+            S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4, 
+            B1=>empty_cmp_clr, CI=>co1_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4, 
+            B1=>full_cmp_clr, CI=>co1_4, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    ae_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    ae_cmp_0: AGEB2
+        port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), 
+            B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5);
+
+    ae_cmp_1: AGEB2
+        port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), 
+            B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5);
+
+    ae_cmp_2: AGEB2
+        port map (A0=>AmEmptyThresh(4), A1=>ae_setsig, B0=>rcnt_reg_4, 
+            B1=>ae_clrsig, CI=>co1_5, GE=>ae_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_ts_32to32_dc is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/cores/pll_adc_clk192.ipx b/mupix/cores/pll_adc_clk192.ipx
new file mode 100644 (file)
index 0000000..1a132a6
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc_clk192" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 15 22:18:00.823" version="5.3" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="pll_adc_clk192.lpc" type="lpc" modified="2013 04 15 22:17:56.000"/>
+               <File name="pll_adc_clk192.vhd" type="top_level_vhdl" modified="2013 04 15 22:17:56.000"/>
+               <File name="pll_adc_clk192_tmpl.vhd" type="template_vhdl" modified="2013 04 15 22:17:56.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/pll_adc_clk192.lpc b/mupix/cores/pll_adc_clk192.lpc
new file mode 100644 (file)
index 0000000..244167c
--- /dev/null
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_adc_clk192
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/15/2013
+Time=22:17:56
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=25
+ClkOPBp=0
+Post=4
+U_OFrq=192
+OP_Tol=0.0
+OFrq=192.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=24
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.141439
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/mupix/cores/pll_adc_clk192.vhd b/mupix/cores/pll_adc_clk192.vhd
new file mode 100644 (file)
index 0000000..bc30248
--- /dev/null
@@ -0,0 +1,97 @@
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module  Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk192 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 192 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Mon Apr 15 22:17:56 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc_clk192 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc_clk192 : entity is true;
+end pll_adc_clk192;
+
+architecture Structure of pll_adc_clk192 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "192.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  24, CLKI_DIV=>  25, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc_clk192 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/cores/pll_adc_clk32.ipx b/mupix/cores/pll_adc_clk32.ipx
new file mode 100644 (file)
index 0000000..890c7f3
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc_clk32" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 14 23:13:37.959" version="5.3" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="pll_adc_clk32.lpc" type="lpc" modified="2013 04 14 23:13:35.000"/>
+               <File name="pll_adc_clk32.vhd" type="top_level_vhdl" modified="2013 04 14 23:13:35.000"/>
+               <File name="pll_adc_clk32_tmpl.vhd" type="template_vhdl" modified="2013 04 14 23:13:35.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/pll_adc_clk32.lpc b/mupix/cores/pll_adc_clk32.lpc
new file mode 100644 (file)
index 0000000..2d97f85
--- /dev/null
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_adc_clk32
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/14/2013
+Time=23:13:35
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=25
+ClkOPBp=0
+Post=16
+U_OFrq=32
+OP_Tol=0.0
+OFrq=32.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=4
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.712159
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/mupix/cores/pll_adc_clk32.vhd b/mupix/cores/pll_adc_clk32.vhd
new file mode 100644 (file)
index 0000000..a293257
--- /dev/null
@@ -0,0 +1,97 @@
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module  Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk32 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 32 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Sun Apr 14 23:13:35 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc_clk32 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc_clk32 : entity is true;
+end pll_adc_clk32;
+
+architecture Structure of pll_adc_clk32 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "32.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  16, CLKFB_DIV=>  4, CLKI_DIV=>  25, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc_clk32 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/cores/pll_nx_clk250.ipx b/mupix/cores/pll_nx_clk250.ipx
new file mode 100644 (file)
index 0000000..b01a100
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 28 16:45:26.723" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 03 28 16:45:22.000"/>
+               <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 03 28 16:45:22.000"/>
+               <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 03 28 16:45:22.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/pll_nx_clk250.lpc b/mupix/cores/pll_nx_clk250.lpc
new file mode 100644 (file)
index 0000000..dffc8d9
--- /dev/null
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_nx_clk250
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=03/28/2013
+Time=16:45:21
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=125
+Div=1
+ClkOPBp=0
+Post=4
+U_OFrq=250
+OP_Tol=0.0
+OFrq=250.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=2
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/mupix/cores/pll_nx_clk250.vhd b/mupix/cores/pll_nx_clk250.vhd
new file mode 100644 (file)
index 0000000..a72a6bd
--- /dev/null
@@ -0,0 +1,97 @@
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module  Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Thu Mar 28 16:45:22 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_nx_clk250 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_nx_clk250 : entity is true;
+end pll_nx_clk250;
+
+architecture Structure of pll_nx_clk250 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  2, CLKI_DIV=>  1, 
+        FIN=> "125.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_nx_clk250 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/cores/pll_nx_clk256.ipx b/mupix/cores/pll_nx_clk256.ipx
new file mode 100644 (file)
index 0000000..e14fe9e
--- /dev/null
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_nx_clk256" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 13 17:24:25.693" version="5.3" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="pll_nx_clk256.lpc" type="lpc" modified="2013 04 13 17:24:24.000"/>
+               <File name="pll_nx_clk256.vhd" type="top_level_vhdl" modified="2013 04 13 17:24:24.000"/>
+               <File name="pll_nx_clk256_tmpl.vhd" type="template_vhdl" modified="2013 04 13 17:24:24.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/cores/pll_nx_clk256.lpc b/mupix/cores/pll_nx_clk256.lpc
new file mode 100644 (file)
index 0000000..61c089f
--- /dev/null
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_nx_clk256
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/13/2013
+Time=17:24:24
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=100
+Div=25
+ClkOPBp=0
+Post=2
+U_OFrq=256
+OP_Tol=0.0
+OFrq=256.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=64
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=0.856080
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/mupix/cores/pll_nx_clk256.vhd b/mupix/cores/pll_nx_clk256.vhd
new file mode 100644 (file)
index 0000000..1299ae5
--- /dev/null
@@ -0,0 +1,97 @@
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module  Version: 5.3
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk256 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 256 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Sat Apr 13 17:24:24 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_nx_clk256 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_nx_clk256 : entity is true;
+end pll_nx_clk256;
+
+architecture Structure of pll_nx_clk256 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "256.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  2, CLKFB_DIV=>  64, CLKI_DIV=>  25, 
+        FIN=> "100.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_nx_clk256 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/mupix/source/adc_spi_master.vhd b/mupix/source/adc_spi_master.vhd
new file mode 100644 (file)
index 0000000..504b630
--- /dev/null
@@ -0,0 +1,451 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity adc_spi_master is\r
+  generic (\r
+    SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+    );\r
+  port(\r
+    CLK_IN               : in    std_logic;\r
+    RESET_IN             : in    std_logic;\r
+\r
+    -- SPI connections\r
+    SCLK_OUT             : out   std_logic;\r
+    SDIO_INOUT           : inout std_logic;\r
+    CSB_OUT              : out   std_logic;\r
+\r
+    -- Internal Interface\r
+    INTERNAL_COMMAND_IN  : in    std_logic_vector(31 downto 0);\r
+    COMMAND_ACK_OUT      : out   std_logic;\r
+    SPI_DATA             : out   std_logic_vector(31 downto 0);\r
+    SPI_LOCK_IN          : in    std_logic;\r
+\r
+    -- Slave bus         \r
+    SLV_READ_IN          : in    std_logic;\r
+    SLV_WRITE_IN         : in    std_logic;\r
+    SLV_DATA_OUT         : out   std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in    std_logic_vector(31 downto 0);\r
+    SLV_ACK_OUT          : out   std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out   std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out   std_logic;\r
+    \r
+    -- Debug Line\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_master is\r
+\r
+  signal sdio_i        : std_logic;\r
+  signal sdio_x        : std_logic;\r
+  signal sdio          : std_logic;\r
+\r
+  signal sclk_o        : std_logic;\r
+  signal command_ack_o : std_logic;\r
+\r
+  -- SPI Master\r
+  signal csb_o                 : std_logic;\r
+  signal spi_start             : std_logic;\r
+\r
+  signal spi_busy              : std_logic;\r
+  signal takeover_sdio         : std_logic;\r
+  signal wait_timer_init       : unsigned(7 downto 0);\r
+  signal sendbyte_seq_start    : std_logic;\r
+  signal readbyte_seq_start    : std_logic;\r
+  signal sendbyte_byte         : std_logic_vector(7 downto 0);\r
+  signal read_seq_ctr          : std_logic;\r
+  signal reg_data              : std_logic_vector(31 downto 0);\r
+\r
+  signal spi_busy_x            : std_logic;\r
+  signal wait_timer_init_x     : unsigned(7 downto 0);\r
+  signal sendbyte_seq_start_x  : std_logic;\r
+  signal sendbyte_byte_x       : std_logic_vector(7 downto 0);\r
+  signal readbyte_seq_start_x  : std_logic;\r
+  signal read_seq_ctr_x        : std_logic;\r
+  signal reg_data_x            : std_logic_vector(31 downto 0);\r
+  \r
+  signal sdio_sendbyte         : std_logic;\r
+  signal sclk_sendbyte         : std_logic;\r
+  signal sendbyte_done         : std_logic;\r
+  \r
+  signal sclk_readbyte         : std_logic;\r
+  signal readbyte_byte         : std_logic_vector(7 downto 0);\r
+  signal readbyte_done         : std_logic;\r
+  \r
+  type STATES is (S_RESET,\r
+                  S_IDLE,\r
+                  S_START,\r
+                  S_START_WAIT,\r
+                  \r
+                  S_SEND_CMD_A,\r
+                  S_SEND_CMD_A_WAIT,\r
+                  S_SEND_CMD_B,\r
+                  S_SEND_CMD_B_WAIT,\r
+\r
+                  S_SEND_DATA,\r
+                  S_SEND_DATA_WAIT,\r
+                  S_GET_DATA,\r
+                  S_GET_DATA_WAIT,\r
+\r
+                  S_STOP,\r
+                  S_STOP_WAIT\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+  \r
+  -- SPI Timer\r
+  signal wait_timer_done         : std_logic;\r
+                                 \r
+  -- TRBNet Slave Bus            \r
+  signal slv_data_out_o          : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o      : std_logic;\r
+  signal slv_unknown_addr_o      : std_logic;\r
+  signal slv_ack_o               : std_logic;\r
+  signal spi_chipid              : std_logic_vector(6 downto 0);\r
+  signal spi_rw_bit              : std_logic;\r
+  signal spi_registerid          : std_logic_vector(12 downto 0);\r
+  signal spi_register_data       : std_logic_vector(7 downto 0);\r
+  signal spi_register_value_read : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 8\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+  adc_spi_sendbyte_1: adc_spi_sendbyte\r
+    generic map (\r
+      SPI_SPEED => SPI_SPEED\r
+      )\r
+    port map (\r
+      CLK_IN             => CLK_IN,\r
+      RESET_IN           => RESET_IN,\r
+      START_IN           => sendbyte_seq_start,\r
+      BYTE_IN            => sendbyte_byte,\r
+      SEQUENCE_DONE_OUT  => sendbyte_done,\r
+      SDIO_OUT           => sdio_sendbyte,\r
+      SCLK_OUT           => sclk_sendbyte\r
+      );\r
+\r
+  adc_spi_readbyte_1: adc_spi_readbyte\r
+    generic map (\r
+      SPI_SPEED => SPI_SPEED\r
+      )\r
+    port map (\r
+      CLK_IN            => CLK_IN,\r
+      RESET_IN          => RESET_IN,\r
+      START_IN          => readbyte_seq_start,\r
+      BYTE_OUT          => readbyte_byte,\r
+      SEQUENCE_DONE_OUT => readbyte_done,\r
+      SDIO_IN           => sdio,\r
+      SCLK_OUT          => sclk_readbyte\r
+      );\r
+  \r
+  -- Debug Line\r
+\r
+  DEBUG_OUT(0)           <= CLK_IN;\r
+  DEBUG_OUT(1)           <= SCLK_OUT;\r
+  DEBUG_OUT(2)           <= SDIO_INOUT;\r
+  DEBUG_OUT(3)           <= CSB_OUT;\r
+  DEBUG_OUT(4)           <= spi_busy;\r
+  DEBUG_OUT(5)           <= wait_timer_done;\r
+  DEBUG_OUT(6)           <= sendbyte_seq_start;\r
+  DEBUG_OUT(7)           <= sendbyte_done;\r
+  DEBUG_OUT(8)           <= sclk_sendbyte;\r
+  DEBUG_OUT(9)           <= sdio_sendbyte;\r
+  DEBUG_OUT(10)          <= sclk_readbyte;\r
+  DEBUG_OUT(11)          <= takeover_sdio;\r
+\r
+  -- Sync SPI SDIO Line\r
+  sdio_i <= SDIO_INOUT;\r
+\r
+  PROC_I2C_LINES_SYNC: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sdio_x <= '1';\r
+        sdio   <= '1';\r
+      else\r
+        sdio_x <= sdio_i;\r
+        sdio   <= sdio_x;\r
+      end if;\r
+    end if;\r
+  end process PROC_I2C_LINES_SYNC;\r
+\r
+  PROC_I2C_MASTER_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        spi_busy              <= '1';\r
+        sendbyte_seq_start    <= '0';\r
+        readbyte_seq_start    <= '0';\r
+        sendbyte_byte         <= (others => '0');\r
+        wait_timer_init       <= (others => '0');\r
+        reg_data              <= (others => '0');\r
+        read_seq_ctr          <= '0';\r
+        STATE                 <= S_RESET;\r
+      else\r
+        spi_busy              <= spi_busy_x;\r
+        sendbyte_seq_start    <= sendbyte_seq_start_x;\r
+        readbyte_seq_start    <= readbyte_seq_start_x;\r
+        sendbyte_byte         <= sendbyte_byte_x;\r
+        wait_timer_init       <= wait_timer_init_x;\r
+        reg_data              <= reg_data_x;\r
+        read_seq_ctr          <= read_seq_ctr_x;\r
+        STATE                 <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_I2C_MASTER_TRANSFER;\r
+  \r
+        \r
+  PROC_I2C_MASTER: process(STATE,\r
+                           spi_start,\r
+                           wait_timer_done,\r
+                           sendbyte_done,\r
+                           readbyte_done\r
+                           )\r
+\r
+  begin\r
+    -- Defaults\r
+    takeover_sdio           <= '0';\r
+    sclk_o                  <= '0';\r
+    csb_o                   <= '0';\r
+    spi_busy_x              <= '1';\r
+    sendbyte_seq_start_x    <= '0';\r
+    sendbyte_byte_x         <= (others => '0');\r
+    readbyte_seq_start_x    <= '0';\r
+    wait_timer_init_x       <= (others => '0');\r
+    reg_data_x              <= reg_data;\r
+    read_seq_ctr_x          <= read_seq_ctr;\r
+    \r
+    case STATE is\r
+\r
+      when S_RESET =>\r
+        reg_data_x <= (others => '0');\r
+        NEXT_STATE <= S_IDLE;\r
+        \r
+      when S_IDLE =>\r
+        csb_o        <= '1';\r
+        if (spi_start = '1') then\r
+          reg_data_x <= x"8000_0000";  -- Set Running , clear all other bits \r
+          NEXT_STATE <= S_START;\r
+        else\r
+          spi_busy_x     <= '0';\r
+          reg_data_x     <= reg_data and x"7fff_ffff";  -- clear running bit;\r
+          read_seq_ctr_x <= '0';\r
+          NEXT_STATE     <= S_IDLE;\r
+        end if;\r
+            \r
+        -- SPI START Sequence \r
+      when S_START =>\r
+        wait_timer_init_x <= SPI_SPEED srl 2;\r
+        NEXT_STATE        <= S_START_WAIT;\r
+        \r
+      when S_START_WAIT =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_START_WAIT;\r
+        else\r
+          takeover_sdio <= '1';\r
+          NEXT_STATE    <= S_SEND_CMD_A;\r
+        end if;\r
+                   \r
+        -- I2C SEND CMD Part1\r
+      when S_SEND_CMD_A =>\r
+        takeover_sdio               <= '1';\r
+        sendbyte_byte_x(7)          <= spi_rw_bit;\r
+        sendbyte_byte_x(6 downto 5) <= "00";\r
+        sendbyte_byte_x(4 downto 0) <= spi_registerid(12 downto 8);\r
+        sendbyte_seq_start_x        <= '1';\r
+        NEXT_STATE                  <= S_SEND_CMD_A_WAIT;\r
+        \r
+      when S_SEND_CMD_A_WAIT =>\r
+        takeover_sdio <= '1';\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_CMD_A_WAIT;\r
+        else\r
+          NEXT_STATE <= S_SEND_CMD_B;\r
+        end if;\r
+        \r
+        -- I2C SEND CMD Part1\r
+      when S_SEND_CMD_B =>\r
+        takeover_sdio               <= '1';\r
+        sendbyte_byte_x(7 downto 0) <= spi_registerid(7 downto 0);\r
+        sendbyte_seq_start_x        <= '1';\r
+        NEXT_STATE                  <= S_SEND_CMD_B_WAIT;\r
+        \r
+      when S_SEND_CMD_B_WAIT =>\r
+        takeover_sdio <= '1';\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_CMD_B_WAIT;\r
+        else\r
+          if (spi_rw_bit = '1') then\r
+            NEXT_STATE        <= S_GET_DATA;\r
+          else\r
+            NEXT_STATE        <= S_SEND_DATA;\r
+          end if;\r
+        end if;\r
+\r
+        -- I2C SEND DataWord\r
+      when S_SEND_DATA =>\r
+        takeover_sdio          <= '1';\r
+        sendbyte_byte_x        <= spi_register_data;\r
+        sendbyte_seq_start_x   <= '1';\r
+        NEXT_STATE             <= S_SEND_DATA_WAIT;\r
+        \r
+      when S_SEND_DATA_WAIT =>\r
+        takeover_sdio <= '1';\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_DATA_WAIT;\r
+        else\r
+          NEXT_STATE <= S_STOP;\r
+        end if;\r
+\r
+        -- I2C GET DataWord\r
+      when S_GET_DATA =>\r
+        readbyte_seq_start_x   <= '1';\r
+        NEXT_STATE             <= S_GET_DATA_WAIT;\r
+        \r
+      when S_GET_DATA_WAIT =>\r
+        if (readbyte_done = '0') then\r
+          NEXT_STATE <= S_GET_DATA_WAIT;\r
+        else\r
+          reg_data_x(7 downto 0) <= readbyte_byte; \r
+          NEXT_STATE             <= S_STOP;\r
+        end if;\r
+        \r
+        -- SPI STOP Sequence \r
+      when S_STOP =>\r
+        wait_timer_init_x     <= SPI_SPEED srl 2;\r
+        NEXT_STATE            <= S_STOP_WAIT;\r
+        \r
+      when S_STOP_WAIT =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_STOP_WAIT;\r
+        else\r
+          reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+        \r
+    end case;\r
+  end process PROC_I2C_MASTER;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+  --\r
+  --   Write bit definition\r
+  --   ====================\r
+  -- \r
+  --   D[31]    SPI_GO          0 => don't do anything on SPI,\r
+  --                            1 => start SPI access\r
+  --   D[30]    SPI_ACTION      0 => write byte, 1 => read byte\r
+  --   D[20:8]  SPI_CMD         SPI Register Id\r
+  --   D[7:0]   SPI_DATA        data to be written\r
+  --   \r
+  --   Read bit definition\r
+  --   ===================\r
+  --   \r
+  --   D[31]    RUNNING         whatever\r
+  --   D[30]    SPI_DONE        whatever\r
+  --   D[29:21] reserved        reserved\r
+  --   D[20:16] debug           subject to change, don't use\r
+  --   D[15:8]  reserved        reserved\r
+  --   D[7:0]   SPI_DATA        result of SPI read operation\r
+  --\r
+  \r
+  PROC_SLAVE_BUS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o     <= (others => '0');\r
+        slv_no_more_data_o <= '0';\r
+        slv_unknown_addr_o <= '0';\r
+        slv_ack_o          <= '0';\r
+        spi_start          <= '0';\r
+        command_ack_o      <= '0';\r
+        \r
+        spi_chipid              <= (others => '0');    \r
+        spi_rw_bit              <= '0';    \r
+        spi_registerid          <= (others => '0');    \r
+        spi_register_data       <= (others => '0');    \r
+        spi_register_value_read <= (others => '0');\r
+            \r
+      else\r
+        slv_data_out_o     <= (others => '0');\r
+        slv_unknown_addr_o <= '0';\r
+        slv_no_more_data_o <= '0';\r
+\r
+        spi_start          <= '0';\r
+        command_ack_o      <= '0';\r
+\r
+        --if (spi_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then\r
+        --  spi_rw_bit         <= INTERNAL_COMMAND_IN(30);\r
+        --  spi_registerid     <= INTERNAL_COMMAND_IN(20 downto 8);\r
+        --  spi_register_data  <= INTERNAL_COMMAND_IN(7 downto 0); \r
+        --  spi_start          <= '1';\r
+        --  command_ack_o      <= '1';\r
+        --  slv_ack_o          <= '1';\r
+        --\r
+        --elsif (SLV_WRITE_IN  = '1') then\r
+        if (SLV_WRITE_IN  = '1') then\r
+          if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then\r
+            spi_rw_bit        <= SLV_DATA_IN(30);\r
+            spi_registerid    <= SLV_DATA_IN(20 downto 8);\r
+            spi_register_data <= SLV_DATA_IN(7 downto 0); \r
+            spi_start         <= '1';\r
+            slv_ack_o         <= '1';\r
+          else\r
+            slv_ack_o         <= '1';\r
+          end if;\r
+          \r
+        elsif (SLV_READ_IN = '1') then\r
+          if (spi_busy = '1') then\r
+            slv_no_more_data_o <= '1';\r
+            slv_ack_o          <= '0';\r
+          else\r
+            slv_data_out_o     <= reg_data;\r
+            slv_ack_o          <= '1';\r
+          end if;\r
+\r
+        else\r
+          slv_ack_o            <= '0';\r
+        end if;\r
+        \r
+      end if;\r
+    end if;           \r
+  end process PROC_SLAVE_BUS;\r
+\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+  \r
+  -- SPI Outputs\r
+  SDIO_INOUT      <= sdio_sendbyte when (takeover_sdio = '1')\r
+                     else 'Z';\r
+  \r
+  SCLK_OUT        <= sclk_o or\r
+                     sclk_sendbyte or\r
+                     sclk_readbyte;\r
+\r
+  CSB_OUT         <= csb_o;\r
+  COMMAND_ACK_OUT <= command_ack_o;\r
+    \r
+  -- Slave Bus\r
+  SLV_DATA_OUT         <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT          <= slv_ack_o; \r
+\r
+end Behavioral;\r
diff --git a/mupix/source/adc_spi_readbyte.vhd b/mupix/source/adc_spi_readbyte.vhd
new file mode 100644 (file)
index 0000000..ab125a3
--- /dev/null
@@ -0,0 +1,172 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity adc_spi_readbyte is\r
+  generic (\r
+    SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+    );\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    START_IN             : in  std_logic;\r
+    BYTE_OUT             : out std_logic_vector(7 downto 0);\r
+    SEQUENCE_DONE_OUT    : out std_logic;\r
+\r
+    -- SPI connections\r
+    SDIO_IN              : in   std_logic;\r
+    SCLK_OUT             : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_readbyte is\r
+\r
+  -- Send Byte  \r
+  signal sclk_o            : std_logic;\r
+  signal spi_start         : std_logic;\r
+\r
+  signal sequence_done_o   : std_logic;\r
+  signal spi_byte          : unsigned(7 downto 0);\r
+  signal bit_ctr           : unsigned(3 downto 0);\r
+  signal spi_ack_o         : std_logic;\r
+  signal wait_timer_init    : unsigned(7 downto 0);\r
+\r
+  signal sequence_done_o_x : std_logic;\r
+  signal spi_byte_x        : unsigned(7 downto 0);\r
+  signal bit_ctr_x         : unsigned(3 downto 0);\r
+  signal spi_ack_o_x       : std_logic;\r
+  signal wait_timer_init_x : unsigned(7 downto 0);\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_UNSET_SCKL,\r
+                  S_UNSET_SCKL_HOLD,\r
+                  S_GET_BIT,\r
+                  S_SET_SCKL,\r
+                  S_NEXT_BIT,\r
+                  S_DONE\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+  \r
+  -- Wait Timer\r
+  signal wait_timer_done    : std_logic;\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map(\r
+      CTR_WIDTH => 8\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+\r
+  PROC_READ_BYTE_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sequence_done_o  <= '0';\r
+        bit_ctr          <= (others => '0');\r
+        spi_ack_o        <= '0';\r
+        wait_timer_init  <= (others => '0');\r
+        STATE            <= S_IDLE;\r
+      else\r
+        sequence_done_o  <= sequence_done_o_x;\r
+        spi_byte         <= spi_byte_x;\r
+        bit_ctr          <= bit_ctr_x;\r
+        spi_ack_o        <= spi_ack_o_x;\r
+        wait_timer_init  <= wait_timer_init_x;\r
+        STATE            <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_READ_BYTE_TRANSFER;  \r
+  \r
+  PROC_READ_BYTE: process(STATE,\r
+                          START_IN,\r
+                          wait_timer_done,\r
+                          bit_ctr\r
+                          )\r
+  begin \r
+    sclk_o             <= '0';\r
+    sequence_done_o_x  <= '0';\r
+    spi_byte_x         <= spi_byte;\r
+    bit_ctr_x          <= bit_ctr;       \r
+    spi_ack_o_x        <= spi_ack_o;\r
+    wait_timer_init_x  <= (others => '0');\r
+    \r
+    case STATE is\r
+      when S_IDLE =>\r
+        if (START_IN = '1') then\r
+          spi_byte_x        <= (others => '0');\r
+          bit_ctr_x         <= x"7";\r
+          wait_timer_init_x <= SPI_SPEED srl 1;\r
+          NEXT_STATE        <= S_UNSET_SCKL;\r
+        else\r
+          NEXT_STATE        <= S_IDLE;\r
+        end if;\r
+\r
+        -- SPI Read byte\r
+      when S_UNSET_SCKL =>\r
+        wait_timer_init_x <= SPI_SPEED srl 1;\r
+        NEXT_STATE        <= S_UNSET_SCKL_HOLD;\r
+\r
+      when S_UNSET_SCKL_HOLD =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_UNSET_SCKL_HOLD;\r
+        else\r
+          NEXT_STATE <= S_GET_BIT;\r
+        end if;\r
+        \r
+      when S_GET_BIT =>\r
+        spi_byte_x(0)     <= SDIO_IN;\r
+        wait_timer_init_x <= SPI_SPEED srl 1;\r
+        NEXT_STATE        <= S_SET_SCKL;\r
+\r
+      when S_SET_SCKL =>\r
+        sclk_o  <= '1';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SCKL;\r
+        else\r
+          wait_timer_init_x <= SPI_SPEED srl 1;\r
+          NEXT_STATE        <= S_NEXT_BIT;\r
+        end if;\r
+        \r
+      when S_NEXT_BIT =>\r
+        sclk_o  <= '1';\r
+        if (bit_ctr > 0) then\r
+          bit_ctr_x          <= bit_ctr - 1;\r
+          spi_byte_x         <= spi_byte sll 1;\r
+          wait_timer_init_x  <= SPI_SPEED srl 1;\r
+          NEXT_STATE         <= S_UNSET_SCKL;\r
+        else\r
+          NEXT_STATE         <= S_DONE;\r
+        end if;\r
+\r
+      when S_DONE =>\r
+        sclk_o  <= '1';\r
+        sequence_done_o_x <= '1';\r
+        NEXT_STATE        <= S_IDLE;\r
+\r
+    end case;\r
+  end process PROC_READ_BYTE;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  SEQUENCE_DONE_OUT <= sequence_done_o;\r
+  BYTE_OUT          <= spi_byte;\r
+  \r
+  -- I2c Outputs\r
+  SCLK_OUT <= sclk_o;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/adc_spi_sendbyte.vhd b/mupix/source/adc_spi_sendbyte.vhd
new file mode 100644 (file)
index 0000000..923f72d
--- /dev/null
@@ -0,0 +1,161 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity adc_spi_sendbyte is\r
+  generic (\r
+    SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+    );\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    START_IN             : in  std_logic;\r
+    BYTE_IN              : in  std_logic_vector(7 downto 0);\r
+    SEQUENCE_DONE_OUT    : out std_logic;\r
+\r
+    -- SPI connections\r
+    SCLK_OUT             : out std_logic;\r
+    SDIO_OUT             : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_sendbyte is\r
+\r
+  -- Send Byte  \r
+  signal sclk_o            : std_logic;\r
+  signal sdio_o            : std_logic;\r
+  signal spi_start         : std_logic;\r
+\r
+  signal sequence_done_o   : std_logic;\r
+  signal spi_byte          : unsigned(7 downto 0);\r
+  signal bit_ctr           : unsigned(3 downto 0);\r
+  signal wait_timer_init   : unsigned(7 downto 0);\r
+\r
+  signal sequence_done_o_x : std_logic;\r
+  signal spi_byte_x        : unsigned(7 downto 0);\r
+  signal bit_ctr_x         : unsigned(3 downto 0);\r
+  signal wait_timer_init_x : unsigned(7 downto 0);\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_SET_SDIO,\r
+                  S_SET_SCLK,\r
+                  S_NEXT_BIT,\r
+                  S_DONE\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+  \r
+  -- Wait Timer\r
+  signal wait_timer_done    : std_logic;\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 8\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+\r
+  PROC_SEND_BYTE_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sequence_done_o  <= '0';\r
+        bit_ctr          <= (others => '0');\r
+        wait_timer_init  <= (others => '0');\r
+        STATE            <= S_IDLE;\r
+      else\r
+        sequence_done_o  <= sequence_done_o_x;\r
+        spi_byte         <= spi_byte_x;\r
+        bit_ctr          <= bit_ctr_x;\r
+        wait_timer_init  <= wait_timer_init_x;\r
+        STATE            <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_SEND_BYTE_TRANSFER;  \r
+  \r
+  PROC_SEND_BYTE: process(STATE,\r
+                          START_IN,\r
+                          wait_timer_done,\r
+                          bit_ctr\r
+                          )\r
+  begin \r
+    sdio_o             <= '0';\r
+    sclk_o             <= '0';\r
+    sequence_done_o_x  <= '0';\r
+    spi_byte_x         <= spi_byte;\r
+    bit_ctr_x          <= bit_ctr;       \r
+    wait_timer_init_x  <= (others => '0');\r
+    \r
+    case STATE is\r
+      when S_IDLE =>\r
+        if (START_IN = '1') then\r
+          spi_byte_x        <= BYTE_IN;\r
+          bit_ctr_x         <= x"7";\r
+          wait_timer_init_x <= SPI_SPEED srl 1;\r
+          NEXT_STATE        <= S_SET_SDIO;\r
+        else\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+\r
+      when S_SET_SDIO =>\r
+        sdio_o <= spi_byte(7);\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SDIO;\r
+        else\r
+          wait_timer_init_x <= SPI_SPEED srl 1;\r
+          NEXT_STATE <= S_SET_SCLK;\r
+        end if;\r
+      \r
+      when S_SET_SCLK =>\r
+        sdio_o <= spi_byte(7);\r
+        sclk_o <= '1';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SCLK;\r
+        else\r
+          NEXT_STATE        <= S_NEXT_BIT;\r
+        end if;\r
+        \r
+      when S_NEXT_BIT =>\r
+        sdio_o <= spi_byte(7);\r
+        sclk_o <= '1';\r
+        if (bit_ctr > 0) then\r
+          bit_ctr_x          <= bit_ctr - 1;\r
+          spi_byte_x         <= spi_byte sll 1;\r
+          wait_timer_init_x  <= SPI_SPEED srl 1;\r
+          NEXT_STATE         <= S_SET_SDIO;\r
+        else\r
+          NEXT_STATE         <= S_DONE;\r
+        end if;\r
+\r
+      when S_DONE =>\r
+        sdio_o <= spi_byte(7);\r
+        sclk_o <= '1';\r
+        sequence_done_o_x <= '1';\r
+        NEXT_STATE        <= S_IDLE;\r
+        \r
+    end case;\r
+  end process PROC_SEND_BYTE;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  SEQUENCE_DONE_OUT <= sequence_done_o;\r
+  \r
+  -- SPI Outputs\r
+  SDIO_OUT <= sdio_o;\r
+  SCLK_OUT <= sclk_o;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/gray_decoder.vhd b/mupix/source/gray_decoder.vhd
new file mode 100644 (file)
index 0000000..fdcffd8
--- /dev/null
@@ -0,0 +1,55 @@
+-----------------------------------------------------------------------------
+--
+-- Gray Decoder
+--
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Gray_Decoder is
+  
+  generic (
+    WIDTH : integer := 12);             -- Register Width
+
+  port (
+    CLK_IN     : in std_logic;
+    RESET_IN   : in std_logic;
+    
+    -- Input
+    GRAY_IN    : in  std_logic_vector(WIDTH - 1 downto 0);
+
+    -- OUTPUT
+    BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
+    );
+
+end entity;
+
+
+architecture Gray_Decoder of Gray_Decoder is
+
+  signal binary_o : std_logic_vector(WIDTH - 1 downto 0);
+
+begin  -- Gray_Decoder
+
+  PROC_DECODER: process (CLK_IN)
+    variable b : std_logic_vector(WIDTH -1 downto 0) := (others => '0');
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        b := (others => '0');
+      else
+        b(WIDTH - 1) := GRAY_IN(WIDTH - 1);
+    
+        for I in (WIDTH - 2) downto 0 loop
+          b(I) := b(I + 1) xor GRAY_IN(I);
+        end loop;
+      end if;
+    end if;
+    binary_o <= b;
+  end process PROC_DECODER;
+
+-- Output
+  BINARY_OUT <= binary_o;
+    
+end Gray_Decoder;
diff --git a/mupix/source/gray_encoder.vhd b/mupix/source/gray_encoder.vhd
new file mode 100644 (file)
index 0000000..037a4ee
--- /dev/null
@@ -0,0 +1,52 @@
+-----------------------------------------------------------------------------
+--
+-- Gray EnCcoder
+--
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Gray_Encoder is
+  generic (
+    WIDTH : integer := 12              -- Register Width
+    );             
+
+  port (
+    CLK_IN      : in std_logic;
+    RESET_IN    : in std_logic;
+    
+    -- Input
+    BINARY_IN   : in  std_logic_vector(WIDTH - 1 downto 0);
+
+    -- OUTPUT
+    GRAY_OUT    : out std_logic_vector(WIDTH - 1 downto 0)
+    );
+
+end entity;
+
+architecture Behavioral of  Gray_Encoder is
+
+  signal gray_o : std_logic_vector(WIDTH - 1 downto 0);
+
+begin
+  
+  PROC_ENCODER: process (CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        gray_o <= (others => '0');
+      else
+        gray_o(WIDTH - 1) <= BINARY_IN(WIDTH -1);
+        for I in (WIDTH - 2) downto 0 loop
+          gray_o(I) <= BINARY_IN(I + 1) xor BINARY_IN(I);
+        end loop;
+      end if;
+    end if;
+
+  end process PROC_ENCODER;
+
+  -- Output
+  GRAY_OUT <= gray_o;
+
+end Behavioral;
diff --git a/mupix/source/level_to_pulse.vhd b/mupix/source/level_to_pulse.vhd
new file mode 100644 (file)
index 0000000..b77f4de
--- /dev/null
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity level_to_pulse is
+  
+  port (
+    CLK_IN        : in std_logic;  
+    RESET_IN      : in std_logic;
+
+    LEVEL_IN      : in std_logic;  
+    PULSE_OUT     : out std_logic
+    );
+
+end entity;
+
+architecture Behavioral of level_to_pulse is
+
+  type STATES is (IDLE,
+                  WAIT_LOW
+                );
+  signal STATE : STATES;
+
+  signal pulse_o          : std_logic;
+
+begin
+
+  PROC_CONVERT: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        pulse_o <= '0';
+        STATE   <= IDLE;
+      else
+        pulse_o <= '0';
+        case STATE is
+
+          when IDLE =>
+            if (LEVEL_IN = '1') then
+              pulse_o <= '1';
+              STATE <= WAIT_LOW;
+            else
+              STATE <= IDLE;
+            end if;
+
+          when WAIT_LOW =>
+            if (LEVEL_IN = '0') then
+              STATE <= IDLE;
+            else
+              STATE <= WAIT_LOW;
+            end if;
+
+           when others => null;
+
+        end case;
+      end if;
+    end if;
+  end process PROC_CONVERT;
+
+  PULSE_OUT <= pulse_o;
+    
+end Behavioral;
diff --git a/mupix/source/nx_data_receiver.vhd b/mupix/source/nx_data_receiver.vhd
new file mode 100644 (file)
index 0000000..df58379
--- /dev/null
@@ -0,0 +1,824 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_data_receiver is\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+    \r
+    -- nXyter Ports\r
+    NX_TIMESTAMP_CLK_IN  : in std_logic;\r
+    NX_TIMESTAMP_IN      : in std_logic_vector (7 downto 0);\r
+\r
+    -- ADC Ports\r
+    ADC_CLK_DAT_IN       : in  std_logic;\r
+    ADC_FCLK_IN          : in  std_logic_vector(1 downto 0);\r
+    ADC_DCLK_IN          : in  std_logic_vector(1 downto 0);\r
+    ADC_SAMPLE_CLK_OUT   : out std_logic;\r
+    ADC_A_IN             : in  std_logic_vector(1 downto 0);\r
+    ADC_B_IN             : in  std_logic_vector(1 downto 0);\r
+    ADC_NX_IN            : in  std_logic_vector(1 downto 0);\r
+    ADC_D_IN             : in  std_logic_vector(1 downto 0);\r
+\r
+    -- Outputs\r
+    NX_TIMESTAMP_OUT     : out std_logic_vector(31 downto 0);\r
+    ADC_DATA_OUT         : out std_logic_vector(11 downto 0);\r
+    NEW_DATA_OUT         : out std_logic;\r
+        \r
+    -- Slave bus         \r
+    SLV_READ_IN          : in  std_logic;\r
+    SLV_WRITE_IN         : in  std_logic;\r
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN          : in std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT          : out std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_data_receiver is\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- NX_TIMESTAMP_CLK Domain\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- FIFO DC Input Handler\r
+  signal nx_timestamp_reg_t       : std_logic_vector(7 downto 0);\r
+  signal nx_timestamp_reg         : std_logic_vector(7 downto 0);\r
+  signal nx_fifo_full             : std_logic;\r
+  signal nx_fifo_reset            : std_logic;\r
+  \r
+  -- NX_TIMESTAMP_IN Process\r
+  signal frame_byte_ctr           : unsigned(1 downto 0);\r
+  signal nx_frame_word            : std_logic_vector(31 downto 0);\r
+  signal nx_new_frame             : std_logic;\r
+\r
+  -- Frame Sync Process                 \r
+  signal frame_byte_pos           : unsigned(1 downto 0);\r
+\r
+  -- RS Sync FlipFlop\r
+  signal nx_frame_synced          : std_logic;\r
+  signal rs_sync_set              : std_logic;\r
+  signal rs_sync_reset            : std_logic;\r
+\r
+  -- Parity Check\r
+  signal parity_error             : std_logic;\r
+\r
+  -- Write to FIFO Handler\r
+  signal nx_fifo_data_input       : std_logic_vector(31 downto 0);\r
+  signal nx_fifo_write_enable     : std_logic;\r
+\r
+  -- NX Clock Active\r
+  signal nx_clk_active_ff_0       : std_logic;\r
+  signal nx_clk_active_ff_1       : std_logic;\r
+  signal nx_clk_active_ff_2       : std_logic;\r
+\r
+  -- ADC Ckl Generator\r
+  signal adc_clk_skip             : std_logic;\r
+  signal adc_sample_clk           : std_logic;\r
+  signal johnson_ff_0             : std_logic;\r
+  signal johnson_ff_1             : std_logic;\r
+  signal adc_clk_inv              : std_logic;\r
+  signal adc_clk_delay            : std_logic_vector(2 downto 0);\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- CLK_IN Domain\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- NX FIFO_READ\r
+  signal nx_timestamp_t           : std_logic_vector(31 downto 0);\r
+  signal nx_new_timestamp         : std_logic;\r
+  signal nx_new_timestamp_ctr     : unsigned(3 downto 0);\r
+\r
+  signal nx_fifo_delay_r          : std_logic_vector(4 downto 0);\r
+  signal nx_fifo_almost_empty     : std_logic;\r
+  \r
+  -- NX FIFO Output Handler\r
+  signal nx_fifo_data             : std_logic_vector(31 downto 0);\r
+  signal nx_fifo_empty            : std_logic;\r
+  signal nx_fifo_read_enable      : std_logic;\r
+  signal nx_fifo_data_valid_t     : std_logic;\r
+  signal nx_fifo_data_valid       : std_logic;\r
+  signal nx_read_enable_pause     : std_logic;\r
+  \r
+  -- Resync Counter Process                 \r
+  signal resync_counter           : unsigned(11 downto 0);\r
+  signal resync_ctr_inc           : std_logic;\r
+  signal nx_clk_active            : std_logic;\r
+  \r
+  -- Parity Error Counter Process                 \r
+  signal parity_error_counter     : unsigned(11 downto 0);\r
+  signal parity_error_ctr_inc     : std_logic;\r
+\r
+  signal reg_nx_frame_synced_t    : std_logic;\r
+  signal reg_nx_frame_synced      : std_logic;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- ADC Data Handler\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- ADC Handler\r
+  signal adc_reset_r       : std_logic;\r
+  signal adc_reset_l       : std_logic;\r
+  signal adc_reset         : std_logic;\r
+  \r
+  signal adc_data          : std_logic_vector(11 downto 0);\r
+  signal adc_data_valid    : std_logic;\r
+\r
+  signal adc_data_t               : std_logic_vector(11 downto 0);\r
+  signal adc_new_data             : std_logic;\r
+  signal adc_new_data_ctr         : unsigned(3 downto 0);\r
+\r
+  -- Data Output Handler\r
+  type STATES is (IDLE,\r
+                  WAIT_ADC,\r
+                  WAIT_TIMESTAMP\r
+                  );\r
+  signal STATE : STATES;\r
+  signal STATE_d                  : std_logic_vector(1 downto 0);\r
+  \r
+  signal nx_timestamp_o           : std_logic_vector(31 downto 0);\r
+  signal adc_data_o               : std_logic_vector(11 downto 0);\r
+  signal new_data_o               : std_logic;\r
+\r
+  -- Slave Bus                    \r
+  signal slv_data_out_o           : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o       : std_logic;\r
+  signal slv_unknown_addr_o       : std_logic;\r
+  signal slv_ack_o                : std_logic;\r
+\r
+  signal reset_resync_ctr         : std_logic;\r
+  signal reset_parity_error_ctr   : std_logic;\r
+  signal fifo_reset_r             : std_logic;\r
+\r
+  signal valid_data_d             : std_logic;\r
+  \r
+begin\r
+\r
+  DEBUG_OUT(0)            <= CLK_IN;\r
+  DEBUG_OUT(2 downto 1)   <= STATE_d;\r
+  DEBUG_OUT(3)            <= nx_new_timestamp;\r
+  DEBUG_OUT(4)            <= adc_new_data;\r
+  DEBUG_OUT(5)            <= new_data_o;\r
+  DEBUG_OUT(6)            <= nx_fifo_data_valid;\r
+  DEBUG_OUT(7)            <= valid_data_d;--(others => '0');\r
+  DEBUG_OUT(15 downto 8)  <= nx_timestamp_reg;\r
+  --DEBUG_OUT(15 downto 8)  <= (others => '0');\r
+\r
+  PROC_DEBUG: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        valid_data_d <= '0';\r
+      else\r
+        if ((nx_timestamp_reg /= x"7f") and\r
+            (nx_timestamp_reg /= x"06")) then\r
+         valid_data_d <= '1';\r
+        else\r
+         valid_data_d <= '0';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_DEBUG;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- ADC CLK DOMAIN\r
+  -----------------------------------------------------------------------------\r
+\r
+  adc_ad9222_1: entity work.adc_ad9222\r
+    generic map (\r
+      CHANNELS => 4,\r
+      DEVICES  => 2,\r
+      RESOLUTION => 12\r
+      )\r
+    port map (\r
+      CLK                        => CLK_IN,\r
+      CLK_ADCREF                 => adc_sample_clk,\r
+      CLK_ADCDAT                 => ADC_CLK_DAT_IN,\r
+      RESTART_IN                 => adc_reset,\r
+      ADCCLK_OUT                 => ADC_SAMPLE_CLK_OUT,\r
+\r
+      ADC_DATA(0)                => ADC_NX_IN(0), \r
+      ADC_DATA(1)                => ADC_A_IN(0),\r
+      ADC_DATA(2)                => ADC_B_IN(0), \r
+      ADC_DATA(3)                => ADC_D_IN(0), \r
+\r
+      ADC_DATA(4)                => ADC_NX_IN(1), \r
+      ADC_DATA(5)                => ADC_A_IN(1), \r
+      ADC_DATA(6)                => ADC_B_IN(1), \r
+      ADC_DATA(7)                => ADC_D_IN(1),\r
+\r
+      ADC_DCO                    => ADC_DCLK_IN,\r
+      ADC_FCO                    => ADC_FCLK_IN,\r
+\r
+      DATA_OUT(11 downto  0)     => adc_data,\r
+      DATA_OUT(95 downto 12)     => open,\r
+\r
+      FCO_OUT                    => open,\r
+      DATA_VALID_OUT(0)          => adc_data_valid,\r
+      DATA_VALID_OUT(1)          => open,\r
+      DEBUG                      => open\r
+      );\r
+\r
+  adc_reset <= adc_reset_l or RESET_IN;\r
+\r
+  pulse_to_level_1: pulse_to_level\r
+    generic map (\r
+      NUM_CYCLES => "10000"\r
+      )\r
+    port map (\r
+      CLK_IN     => CLK_IN,\r
+      RESET_IN   => RESET_IN,\r
+      PULSE_IN   => adc_reset_r,\r
+      LEVEL_OUT  => adc_reset_l\r
+      );\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- NX_TIMESTAMP_CLK_IN Domain\r
+  -----------------------------------------------------------------------------\r
+\r
+  nx_timestamp_reg   <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN);\r
+\r
+  -- Transfer 8 to 32Bit \r
+  PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        frame_byte_ctr   <= (others => '0');\r
+        nx_frame_word    <= (others => '0');\r
+        nx_new_frame     <= '0';\r
+      else\r
+        nx_new_frame     <= '0';\r
+        \r
+        case frame_byte_pos is\r
+          when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_reg;\r
+                       frame_byte_ctr              <= frame_byte_ctr + 1;\r
+                       \r
+          when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_reg;\r
+                       frame_byte_ctr              <= frame_byte_ctr + 1;\r
+                       \r
+          when "01" => nx_frame_word(15 downto  8) <= nx_timestamp_reg;\r
+                       frame_byte_ctr              <= frame_byte_ctr + 1;\r
+                       \r
+          when "00" => nx_frame_word( 7 downto  0) <= nx_timestamp_reg;\r
+                       if (frame_byte_ctr = "11") then\r
+                         nx_new_frame   <= '1';\r
+                       end if;\r
+                       frame_byte_ctr   <= (others => '0'); \r
+        end case;\r
+      end if;\r
+    end if;\r
+  end process PROC_8_TO_32_BIT;\r
+  \r
+  -- Frame Sync process\r
+  PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        frame_byte_pos   <= "11";\r
+        rs_sync_set      <= '0';\r
+        rs_sync_reset    <= '0';\r
+      else\r
+        rs_sync_set       <= '0';\r
+        rs_sync_reset     <= '0';\r
+        if (nx_new_frame = '1') then\r
+          case nx_frame_word is\r
+            when x"7f7f7f06" =>\r
+              rs_sync_set         <= '1';      \r
+              frame_byte_pos      <= frame_byte_pos - 1;\r
+              \r
+            when x"7f7f067f" =>\r
+              rs_sync_reset       <= '1';\r
+              frame_byte_pos      <= frame_byte_pos - 2;\r
+              \r
+            when x"7f067f7f" =>\r
+              rs_sync_reset       <= '1';\r
+              frame_byte_pos      <= frame_byte_pos - 3;\r
+              \r
+            when x"067f7f7f" =>\r
+              rs_sync_reset       <= '1';        \r
+              frame_byte_pos      <= frame_byte_pos - 4;\r
+              \r
+            when others =>\r
+              frame_byte_pos      <= frame_byte_pos - 1;\r
+          end case;\r
+        else\r
+          frame_byte_pos          <= frame_byte_pos - 1;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_SYNC_TO_NX_FRAME;\r
+\r
+  -- RS FlipFlop to hold Sync Status\r
+  PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if (RESET_IN = '1' or rs_sync_reset = '1') then\r
+        nx_frame_synced <= '0';\r
+      elsif (rs_sync_set = '1') then\r
+        nx_frame_synced <= '1';\r
+      end if;\r
+    end if;\r
+  end process PROC_RS_FRAME_SYNCED;\r
+\r
+  -- Check Parity\r
+  PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN)\r
+    variable parity_bits : std_logic_vector(22 downto 0);\r
+    variable parity      : std_logic;\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        parity_error   <= '0';\r
+      else\r
+        parity_error   <= '0';\r
+        if (nx_new_frame = '1' and nx_frame_synced = '1') then\r
+          -- Timestamp Bit #6 is excluded (funny nxyter-bug)\r
+          parity_bits         := nx_frame_word(31)           &\r
+                                 nx_frame_word(30 downto 24) &\r
+                                 nx_frame_word(21 downto 16) &\r
+                                 nx_frame_word(14 downto  8) &\r
+                                 nx_frame_word( 2 downto  1);\r
+          parity              := xor_all(parity_bits);\r
+\r
+          if (parity /= nx_frame_word(0)) then\r
+            parity_error   <= '1';\r
+          end if;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_PARITY_CHECK;\r
+\r
+  -- Write to FIFO\r
+  PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        nx_fifo_data_input      <= (others => '0');\r
+        nx_fifo_write_enable    <= '0';\r
+      else\r
+        nx_fifo_data_input      <= x"deadbeef";\r
+        nx_fifo_write_enable    <= '0';\r
+        if (nx_new_frame = '1' and nx_frame_synced = '1') then\r
+          nx_fifo_data_input    <= nx_frame_word; \r
+          nx_fifo_write_enable  <= '1';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_WRITE_TO_FIFO;\r
+\r
+  fifo_ts_32to32_dc_1: fifo_ts_32to32_dc\r
+    port map (\r
+      Data          => nx_fifo_data_input,\r
+      WrClock       => NX_TIMESTAMP_CLK_IN,\r
+      RdClock       => CLK_IN,\r
+      WrEn          => nx_fifo_write_enable,\r
+      RdEn          => nx_fifo_read_enable,\r
+      Reset         => nx_fifo_reset,\r
+      RPReset       => nx_fifo_reset,\r
+      AmEmptyThresh => nx_fifo_delay_r,\r
+      Q             => nx_fifo_data,\r
+      Empty         => nx_fifo_empty,\r
+      Full          => nx_fifo_full,\r
+      AlmostEmpty   => nx_fifo_almost_empty\r
+      );\r
+  \r
+  nx_fifo_reset     <= RESET_IN or fifo_reset_r;\r
+\r
+--   -- Reset NX_TIMESTAMP_CLK Domain\r
+--   PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN)\r
+--   begin\r
+--     if( rising_edge(CLK_IN) ) then\r
+--       if( RESET_IN = '1' ) then\r
+--         reset_nx_domain_ctr <= (others => '0');\r
+--         reset_nx_domain <= '1';\r
+--       else\r
+--         if (nx_clk_pulse = '1') then\r
+--           nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1;\r
+--         end if;\r
+--         \r
+--       end if;\r
+-- \r
+--     end if;\r
+--   end process PROC_NX_CLK_DOMAIN_RESET;\r
+\r
+  PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if(rising_edge(NX_TIMESTAMP_CLK_IN)) then\r
+      if(RESET_IN = '1' ) then\r
+        nx_clk_active_ff_0 <= '0';\r
+        nx_clk_active_ff_1 <= '0';\r
+        nx_clk_active_ff_2 <= '0';\r
+      else\r
+        nx_clk_active_ff_0 <= not nx_clk_active_ff_2;\r
+        nx_clk_active_ff_1 <= nx_clk_active_ff_0;\r
+        nx_clk_active_ff_2 <= nx_clk_active_ff_1;\r
+      end if;\r
+    end if;\r
+  end process PROC_NX_CLK_ACT;\r
+\r
+  -- Johnson Counter\r
+  PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if(rising_edge(NX_TIMESTAMP_CLK_IN)) then\r
+      if (RESET_IN = '1') then\r
+        johnson_ff_0  <= '0';\r
+        johnson_ff_1  <= '0';\r
+      else\r
+        if (adc_clk_skip = '0') then\r
+          johnson_ff_0 <= not johnson_ff_1;\r
+          johnson_ff_1 <= johnson_ff_0;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_ADC_CLK_GENERATOR;\r
+\r
+  PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN)\r
+  begin\r
+    if(falling_edge(NX_TIMESTAMP_CLK_IN)) then\r
+      if (RESET_IN = '1') then\r
+        adc_clk_inv <= '0';\r
+      else\r
+        adc_clk_inv <= johnson_ff_0;\r
+      end if;\r
+    end if;\r
+  end process PROC_ADC_CLK_DELAY_4NS;\r
+  \r
+  adc_sample_clk <= adc_clk_inv when adc_clk_delay(0) = '1' else johnson_ff_0;\r
+  \r
+  PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN)\r
+    variable adc_clk_state : std_logic_vector(1 downto 0);\r
+  begin\r
+    if(rising_edge(NX_TIMESTAMP_CLK_IN)) then\r
+      if (RESET_IN = '1') then\r
+        adc_clk_skip  <= '0';\r
+      else\r
+        adc_clk_state := johnson_ff_1 & johnson_ff_0;\r
+        adc_clk_skip  <= '0';\r
+\r
+        if (nx_new_frame = '1') then\r
+          if (adc_clk_state /= adc_clk_delay(2 downto 1)) then\r
+            adc_clk_skip <= '1';\r
+          end if;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_ADC_CLK_DELAY;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- NX CLK_IN Domain\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- FIFO Read Handler\r
+  PROC_NX_FIFO_READ_ENABLE: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' or fifo_reset_r = '1') then\r
+        nx_fifo_read_enable       <= '0';\r
+        nx_read_enable_pause      <= '0';\r
+        nx_fifo_data_valid_t      <= '0';\r
+        nx_fifo_data_valid        <= '0';\r
+      else\r
+        if (nx_fifo_almost_empty = '0' and nx_read_enable_pause = '0') then\r
+          nx_fifo_read_enable     <= '1';\r
+          nx_read_enable_pause    <= '1';\r
+        else\r
+          nx_fifo_read_enable     <= '0';\r
+          nx_read_enable_pause    <= '0';\r
+        end if;\r
+\r
+        -- Delay read signal by one CLK\r
+        nx_fifo_data_valid_t      <= nx_fifo_read_enable;\r
+        nx_fifo_data_valid        <= nx_fifo_data_valid_t;\r
+\r
+      end if;\r
+    end if;\r
+  end process PROC_NX_FIFO_READ_ENABLE;\r
+\r
+  PROC_NX_FIFO_READ: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or fifo_reset_r = '1') then\r
+        nx_timestamp_t         <= (others => '0');\r
+        nx_new_timestamp       <= '0';\r
+        nx_new_timestamp_ctr   <= (others => '0');\r
+      else\r
+        if (nx_fifo_data_valid = '1') then\r
+          nx_timestamp_t       <= nx_fifo_data;\r
+          nx_new_timestamp     <= '1';\r
+          nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1;\r
+        else\r
+          nx_timestamp_t       <= x"deadbeef";\r
+          nx_new_timestamp     <= '0';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_NX_FIFO_READ;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Status Counters\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- Domain Transfers\r
+  pulse_sync_1: pulse_sync\r
+    port map (\r
+      CLK_A_IN    => NX_TIMESTAMP_CLK_IN,\r
+      RESET_A_IN  => RESET_IN,\r
+      PULSE_A_IN  => rs_sync_reset,\r
+      CLK_B_IN    => CLK_IN,\r
+      RESET_B_IN  => RESET_IN,\r
+      PULSE_B_OUT => resync_ctr_inc \r
+      );\r
+\r
+  pulse_sync_2: pulse_sync\r
+    port map (\r
+      CLK_A_IN    => NX_TIMESTAMP_CLK_IN,\r
+      RESET_A_IN  => RESET_IN,\r
+      PULSE_A_IN  => parity_error,\r
+      CLK_B_IN    => CLK_IN,\r
+      RESET_B_IN  => RESET_IN,\r
+      PULSE_B_OUT => parity_error_ctr_inc\r
+      );\r
+\r
+  PROC_SYNC_FRAME_SYNC: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if(RESET_IN = '1' ) then\r
+        reg_nx_frame_synced_t <= '0';\r
+        reg_nx_frame_synced   <= '0';\r
+      else\r
+        reg_nx_frame_synced_t <= nx_frame_synced;\r
+        reg_nx_frame_synced   <= reg_nx_frame_synced_t; \r
+      end if;\r
+    end if;\r
+  end process PROC_SYNC_FRAME_SYNC;\r
+\r
+  -- Counters\r
+  PROC_RESYNC_COUNTER: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or reset_resync_ctr = '1') then\r
+        resync_counter <= (others => '0');\r
+      else\r
+        if (resync_ctr_inc = '1') then\r
+          resync_counter <= resync_counter + 1;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_RESYNC_COUNTER; \r
+\r
+  PROC_PARITY_ERROR_COUNTER: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or reset_parity_error_ctr = '1') then\r
+        parity_error_counter <= (others => '0');\r
+      else\r
+        if (parity_error_ctr_inc = '1') then\r
+          parity_error_counter <= parity_error_counter + 1;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_PARITY_ERROR_COUNTER;\r
+\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- ADC Fifo Handler\r
+  -----------------------------------------------------------------------------\r
+  PROC_ADC_DATA_READ: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or fifo_reset_r = '1') then\r
+        adc_data_t         <= (others => '0');\r
+        adc_new_data       <= '0';\r
+        adc_new_data_ctr   <= (others => '0');\r
+      else\r
+        if (adc_data_valid = '1') then\r
+          adc_data_t       <= adc_data;\r
+          adc_new_data     <= '1';\r
+          adc_new_data_ctr <= adc_new_data_ctr + 1;\r
+        else\r
+          adc_data_t       <= x"aff";\r
+          adc_new_data     <= '0';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_ADC_DATA_READ; \r
+        \r
+  -----------------------------------------------------------------------------\r
+  -- Output handler\r
+  -----------------------------------------------------------------------------\r
+  PROC_OUTPUT_HANDLER: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or fifo_reset_r = '1') then\r
+        nx_timestamp_o <= (others => '0');\r
+        adc_data_o     <= (others => '0');\r
+        new_data_o     <= '0';\r
+        STATE          <= IDLE;\r
+      else\r
+        case STATE is\r
+          \r
+          when IDLE =>\r
+            STATE_d <= "00";\r
+            if (nx_new_timestamp = '1' and adc_new_data = '1') then\r
+              nx_timestamp_o  <= nx_timestamp_t;\r
+              adc_data_o      <= adc_data_t;\r
+              new_data_o      <= '1';\r
+              STATE           <= IDLE;\r
+            elsif (nx_new_timestamp = '1') then\r
+              nx_timestamp_o  <= nx_timestamp_t;\r
+              adc_data_o      <= (others => '0');\r
+              new_data_o      <= '0';\r
+              STATE           <= WAIT_ADC;\r
+            elsif (adc_new_data = '1') then\r
+              adc_data_o      <= adc_data_t;\r
+              nx_timestamp_o  <= (others => '0');\r
+              new_data_o      <= '0';  \r
+              STATE           <= WAIT_TIMESTAMP;\r
+            else\r
+              nx_timestamp_o  <= (others => '0');\r
+              adc_data_o      <= (others => '0');\r
+              new_data_o      <= '0';  \r
+              STATE           <= IDLE;\r
+            end if;\r
+\r
+          when WAIT_ADC =>\r
+            STATE_d <= "01";\r
+            if (adc_new_data = '1') then\r
+              adc_data_o      <= adc_data_t;\r
+              new_data_o      <= '1';\r
+              STATE           <= IDLE;\r
+            else\r
+              new_data_o      <= '0';  \r
+              STATE           <= WAIT_ADC;\r
+            end if;\r
+\r
+           when WAIT_TIMESTAMP => \r
+            STATE_d <= "10";\r
+            if (nx_new_timestamp = '1') then\r
+              nx_timestamp_o  <= nx_timestamp_t;\r
+              new_data_o      <= '1';\r
+              STATE           <= IDLE;\r
+            else\r
+              new_data_o      <= '0';  \r
+              STATE           <= WAIT_TIMESTAMP;\r
+            end if; \r
+\r
+        end case;\r
+      end if;\r
+    end if;\r
+  end process PROC_OUTPUT_HANDLER;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- Give status info to the TRB Slow Control Channel\r
+  PROC_FIFO_REGISTERS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o          <= (others => '0');\r
+        slv_ack_o               <= '0';\r
+        slv_unknown_addr_o      <= '0';\r
+        slv_no_more_data_o      <= '0';\r
+        reset_resync_ctr        <= '0';\r
+        reset_parity_error_ctr  <= '0';\r
+        nx_fifo_delay_r         <= "01000";\r
+        fifo_reset_r            <= '0';\r
+        adc_clk_delay           <= "111";\r
+        adc_reset_r             <= '0';\r
+      else                      \r
+        slv_data_out_o          <= (others => '0');\r
+        slv_ack_o               <= '0';\r
+        slv_unknown_addr_o      <= '0';\r
+        slv_no_more_data_o      <= '0';\r
+        reset_resync_ctr        <= '0';\r
+        reset_parity_error_ctr  <= '0';\r
+        fifo_reset_r            <= '0';\r
+        adc_reset_r             <= '0';\r
+        \r
+        if (SLV_READ_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0000" =>\r
+              slv_data_out_o               <= nx_timestamp_t;\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0001" =>\r
+              slv_data_out_o(0)            <= nx_fifo_full;\r
+              slv_data_out_o(1)            <= nx_fifo_empty;\r
+              slv_data_out_o(2)            <= '0';\r
+              slv_data_out_o(3)            <= '0';\r
+              slv_data_out_o(4)            <= nx_fifo_data_valid;\r
+              slv_data_out_o(5)            <= adc_new_data;\r
+              slv_data_out_o(29 downto 5)  <= (others => '0');\r
+              slv_data_out_o(30)           <= '0';\r
+              slv_data_out_o(31)           <= reg_nx_frame_synced;\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0002" =>\r
+              slv_data_out_o(11 downto  0) <= resync_counter;\r
+              slv_data_out_o(31 downto 12) <= (others => '0');\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0003" =>\r
+              slv_data_out_o(11 downto  0) <= parity_error_counter;\r
+              slv_data_out_o(31 downto 12) <= (others => '0');\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0004" =>\r
+              slv_data_out_o( 4 downto 0)  <= nx_fifo_delay_r;\r
+              slv_data_out_o(31 downto 5)  <= (others => '0');\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0005" =>\r
+              case adc_clk_delay is\r
+                when "010" => slv_data_out_o(2 downto 0) <= "000";\r
+                when "011" => slv_data_out_o(2 downto 0) <= "001";\r
+                when "000" => slv_data_out_o(2 downto 0) <= "010";\r
+                when "001" => slv_data_out_o(2 downto 0) <= "011";\r
+                when "100" => slv_data_out_o(2 downto 0) <= "100";\r
+                when "101" => slv_data_out_o(2 downto 0) <= "101";\r
+                when "110" => slv_data_out_o(2 downto 0) <= "110";\r
+                when "111" => slv_data_out_o(2 downto 0) <= "111";\r
+              end case;\r
+\r
+              slv_data_out_o(31 downto 3)  <= (others => '0');\r
+              slv_ack_o                    <= '1';   \r
+\r
+            when x"0006" =>\r
+              slv_data_out_o(11 downto 0)  <= adc_data_t;\r
+              slv_data_out_o(31 downto 12) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+            \r
+            when others  =>\r
+              slv_unknown_addr_o           <= '1';\r
+          end case;\r
+          \r
+        elsif (SLV_WRITE_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0001" => \r
+              adc_reset_r                  <= '1';\r
+              slv_ack_o                    <= '1';\r
+              \r
+            when x"0002" => \r
+              reset_resync_ctr             <= '1';\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0003" => \r
+              reset_parity_error_ctr       <= '1';\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0004" => \r
+              if (SLV_DATA_IN  < x"0000_001c" and\r
+                  SLV_DATA_IN  > x"0000_0001") then\r
+                nx_fifo_delay_r            <= SLV_DATA_IN(4 downto 0);\r
+                fifo_reset_r               <= '1';\r
+              end if;\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0005" =>\r
+              if (SLV_DATA_IN  < x"0000_0008") then\r
+                case SLV_DATA_IN(2 downto 0) is\r
+                  when "000" => adc_clk_delay <= "010";\r
+                  when "001" => adc_clk_delay <= "011";\r
+                  when "010" => adc_clk_delay <= "000";\r
+                  when "011" => adc_clk_delay <= "001";\r
+                  when "100" => adc_clk_delay <= "100";\r
+                  when "101" => adc_clk_delay <= "101";\r
+                  when "110" => adc_clk_delay <= "110";\r
+                  when "111" => adc_clk_delay <= "111";\r
+                end case;\r
+                adc_reset_r                <= '1';\r
+              end if;\r
+              slv_ack_o                    <= '1';\r
+              \r
+            when others  =>\r
+              slv_unknown_addr_o           <= '1';              \r
+          end case;                \r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_FIFO_REGISTERS;\r
+\r
+  -- Output Signals\r
+\r
+  NX_TIMESTAMP_OUT      <= nx_timestamp_o;\r
+  ADC_DATA_OUT          <= adc_data_o;\r
+  NEW_DATA_OUT          <= new_data_o;\r
+  \r
+  SLV_DATA_OUT          <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT  <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT  <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT           <= slv_ack_o;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/nx_data_validate.vhd b/mupix/source/nx_data_validate.vhd
new file mode 100644 (file)
index 0000000..1bc8d71
--- /dev/null
@@ -0,0 +1,374 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_data_validate is\r
+  port (\r
+    CLK_IN               : in  std_logic;  \r
+    RESET_IN             : in  std_logic;\r
+\r
+    -- Inputs\r
+    NX_TIMESTAMP_IN      : in  std_logic_vector(31 downto 0);\r
+    ADC_DATA_IN          : in  std_logic_vector(11 downto 0);\r
+    NEW_DATA_IN          : in  std_logic;\r
+\r
+    -- Outputs\r
+    TIMESTAMP_OUT        : out std_logic_vector(13 downto 0);\r
+    CHANNEL_OUT          : out std_logic_vector(6 downto 0);\r
+    TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0);\r
+    ADC_DATA_OUT         : out std_logic_vector(11 downto 0);\r
+    DATA_VALID_OUT       : out std_logic;\r
+\r
+    NX_TOKEN_RETURN_OUT  : out std_logic;\r
+    NX_NOMORE_DATA_OUT   : out std_logic;\r
+\r
+    -- Slave bus         \r
+    SLV_READ_IN          : in  std_logic;\r
+    SLV_WRITE_IN         : in  std_logic;\r
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN          : in std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT          : out std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+    \r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+\r
+end entity;\r
+\r
+architecture Behavioral of nx_data_validate is\r
+\r
+  -- Gray Decoder\r
+  signal nx_timestamp         : std_logic_vector(13 downto 0);\r
+  signal nx_channel_id        : std_logic_vector( 6 downto 0);\r
+  \r
+  -- TIMESTAMP_BITS\r
+  signal new_timestamp        : std_logic;\r
+  signal valid_frame_bits     : std_logic_vector(3 downto 0);\r
+  signal status_bits          : std_logic_vector(1 downto 0);\r
+  signal parity_bit           : std_logic;\r
+  signal parity               : std_logic;\r
+  signal adc_data             : std_logic_vector(11 downto 0);\r
+  \r
+  -- Validate Timestamp\r
+  signal timestamp_o          : std_logic_vector(13 downto 0);\r
+  signal channel_o            : std_logic_vector(6 downto 0);\r
+  signal timestamp_status_o   : std_logic_vector(2 downto 0);\r
+  signal adc_data_o           : std_logic_vector(11 downto 0);\r
+  signal data_valid_o         : std_logic;\r
+\r
+  signal nx_token_return_o    : std_logic;\r
+  signal nx_nomore_data_o     : std_logic;\r
+  \r
+  signal invalid_frame_ctr    : unsigned(15 downto 0);\r
+  signal overflow_ctr         : unsigned(15 downto 0);\r
+  signal pileup_ctr           : unsigned(15 downto 0);\r
+  signal parity_error_ctr     : unsigned(15 downto 0);\r
+  signal nx_valid_ctr         : unsigned(19 downto 0);\r
+  signal nx_rate_timer        : unsigned(19 downto 0);\r
+\r
+  -- Config\r
+  signal readout_type         : std_logic_vector(1 downto 0);\r
+\r
+  -- Slave Bus                    \r
+  signal slv_data_out_o       : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o   : std_logic;\r
+  signal slv_unknown_addr_o   : std_logic;\r
+  signal slv_ack_o            : std_logic;\r
+  signal clear_counters       : std_logic;\r
+  signal nx_trigger_rate      : unsigned(19 downto 0);\r
+\r
+  signal invalid_adc : std_logic;\r
+  \r
+begin\r
+\r
+  -- Debug Line\r
+  DEBUG_OUT(0)                    <= CLK_IN;\r
+  DEBUG_OUT(1)                    <= nx_token_return_o;\r
+  DEBUG_OUT(2)                    <= nx_nomore_data_o;\r
+  DEBUG_OUT(3)                    <= data_valid_o;\r
+  DEBUG_OUT(4)                    <= new_timestamp;\r
+  DEBUG_OUT(8 downto 5)           <= (others => '0');\r
+  DEBUG_OUT(15 downto 9)          <= channel_o;\r
+  --DEBUG_OUT(6 downto 4)           <= timestamp_status_o;\r
+  --DEBUG_OUT(7)                    <= nx_token_return_o;\r
+  --DEBUG_OUT(8)                    <= invalid_adc;--nx_nomore_data_o;\r
+  \r
+  --DEBUG_OUT(15 downto 9)          <= channel_o;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Gray Decoder for Timestamp and Channel Id\r
+  -----------------------------------------------------------------------------\r
+\r
+  Gray_Decoder_1: Gray_Decoder          -- Decode nx_timestamp\r
+    generic map (\r
+      WIDTH => 14\r
+      )\r
+    port map (\r
+      CLK_IN               => CLK_IN,\r
+      RESET_IN             => RESET_IN,\r
+      GRAY_IN(13 downto 7) => not NX_TIMESTAMP_IN(30 downto 24),\r
+      GRAY_IN( 6 downto 0) => not NX_TIMESTAMP_IN(22 downto 16),\r
+      BINARY_OUT           => nx_timestamp\r
+      );\r
+\r
+  Gray_Decoder_2: Gray_Decoder          -- Decode Channel_ID\r
+    generic map (\r
+      WIDTH => 7\r
+      )\r
+    port map (\r
+      CLK_IN     => CLK_IN,\r
+      RESET_IN   => RESET_IN,\r
+      GRAY_IN    => NX_TIMESTAMP_IN(14 downto 8),\r
+      BINARY_OUT => nx_channel_id\r
+      );\r
+\r
+  -- Separate Status-, Parity- and Frame-bits, calculate parity\r
+  PROC_TIMESTAMP_BITS: process (CLK_IN)\r
+    variable parity_bits : std_logic_vector(22 downto 0);\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        valid_frame_bits    <= (others => '0');\r
+        status_bits         <= (others => '0');\r
+        parity_bit          <= '0';\r
+        parity              <= '0';\r
+        new_timestamp       <= '0';\r
+        adc_data            <= (others => '0');\r
+      else\r
+        -- Timestamp Bit #6 is excluded (funny nxyter-bug)\r
+        parity_bits         := NX_TIMESTAMP_IN(31 downto 24) &\r
+                               NX_TIMESTAMP_IN(21 downto 16) &\r
+                               NX_TIMESTAMP_IN(14 downto  8) &\r
+                               NX_TIMESTAMP_IN( 2 downto  1);\r
+        valid_frame_bits    <= (others => '0');\r
+        status_bits         <= (others => '0');\r
+        parity_bit          <= '0';\r
+        parity              <= '0';\r
+        new_timestamp       <= '0';\r
+        adc_data            <= (others => '0');\r
+        \r
+        if (NEW_DATA_IN = '1') then\r
+          valid_frame_bits(3) <= NX_TIMESTAMP_IN(31);\r
+          valid_frame_bits(2) <= NX_TIMESTAMP_IN(23);\r
+          valid_frame_bits(1) <= NX_TIMESTAMP_IN(15);\r
+          valid_frame_bits(0) <= NX_TIMESTAMP_IN(7);\r
+          status_bits         <= NX_TIMESTAMP_IN(2 downto 1);\r
+          parity_bit          <= NX_TIMESTAMP_IN(0);\r
+          parity              <= xor_all(parity_bits);\r
+          adc_data            <= ADC_DATA_IN;\r
+          new_timestamp       <= '1';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_TIMESTAMP_BITS;    \r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Filter only valid events\r
+  -----------------------------------------------------------------------------\r
+\r
+  PROC_VALIDATE_TIMESTAMP: process (CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        timestamp_o          <= (others => '0');\r
+        channel_o            <= (others => '0');\r
+        timestamp_status_o   <= (others => '0');\r
+        adc_data_o           <= (others => '0');\r
+        data_valid_o         <= '0';\r
+        nx_token_return_o    <= '0';\r
+        nx_nomore_data_o     <= '0';\r
+\r
+        invalid_frame_ctr    <= (others => '0');\r
+        overflow_ctr         <= (others => '0');\r
+        pileup_ctr           <= (others => '0');\r
+        parity_error_ctr     <= (others => '0');\r
+        nx_valid_ctr         <= (others => '0');\r
+        nx_trigger_rate      <= (others => '0');\r
+        nx_rate_timer        <= (others => '0');\r
+      else\r
+        timestamp_o          <= (others => '0');\r
+        channel_o            <= (others => '0');\r
+        timestamp_status_o   <= (others => '0');\r
+        adc_data_o           <= (others => '0');\r
+        data_valid_o         <= '0';\r
+       \r
+        invalid_adc <= '0';\r
+\r
+        if (new_timestamp = '1') then\r
+          case valid_frame_bits is\r
+\r
+            -- Data Frame\r
+            when "1000" =>\r
+              ---- Check Overflow\r
+              if ((status_bits(0) = '1') and (clear_counters = '0')) then\r
+                overflow_ctr <= overflow_ctr + 1;\r
+              end if;\r
+              \r
+              ---- Check Parity\r
+              if ((parity_bit /= parity) and (clear_counters = '0')) then\r
+                timestamp_status_o(0) <= '1';\r
+                parity_error_ctr      <= parity_error_ctr + 1;\r
+              end if;\r
+\r
+              -- Check PileUp\r
+              if ((status_bits(1) = '1') and (clear_counters = '0')) then\r
+                pileup_ctr <= pileup_ctr + 1;\r
+              end if;\r
+              \r
+              -- Take Timestamp\r
+              timestamp_o                    <= nx_timestamp;\r
+              channel_o                      <= nx_channel_id;\r
+              timestamp_status_o(2 downto 1) <= status_bits;\r
+              adc_data_o                     <= adc_data;\r
+              data_valid_o                   <= '1';\r
+              \r
+              -- Rate Counter\r
+              if (nx_rate_timer < x"186a0") then\r
+                nx_valid_ctr    <= nx_valid_ctr + 1;\r
+              end if;\r
+\r
+              if (adc_data = x"aff") then\r
+                invalid_adc <= '1';\r
+              end if;\r
+\r
+              nx_token_return_o   <= '0';\r
+              nx_nomore_data_o    <= '0';\r
+                            \r
+            -- Token return and nomore_data\r
+            when "0000" =>\r
+              nx_token_return_o   <= '1';\r
+              nx_nomore_data_o    <= nx_token_return_o;\r
+              \r
+            when others =>\r
+              -- Invalid frame, not empty, discard timestamp\r
+              if (clear_counters = '0') then\r
+                invalid_frame_ctr <= invalid_frame_ctr + 1;\r
+              end if;\r
+              nx_token_return_o   <= '0';\r
+              nx_nomore_data_o    <= '0';\r
+              \r
+          end case;\r
+        else\r
+          nx_token_return_o       <= nx_token_return_o;\r
+          nx_nomore_data_o        <= nx_nomore_data_o;\r
+        end if;  -- new_timestamp = '1'\r
+\r
+        -- Trigger Rate\r
+        if (nx_rate_timer < x"186a0") then\r
+          nx_rate_timer   <= nx_rate_timer + 1;\r
+        else\r
+          nx_rate_timer   <= (others => '0');\r
+          nx_trigger_rate <= nx_valid_ctr;\r
+          nx_valid_ctr    <= (others => '0');\r
+        end if;\r
+        \r
+        -- Reset Counters\r
+        if (clear_counters = '1') then\r
+          invalid_frame_ctr   <= (others => '0');\r
+          overflow_ctr        <= (others => '0');\r
+          pileup_ctr          <= (others => '0');\r
+          parity_error_ctr    <= (others => '0');\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_VALIDATE_TIMESTAMP;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- Give status info to the TRB Slow Control Channel\r
+  PROC_FIFO_REGISTERS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o         <= (others => '0');\r
+        slv_ack_o              <= '0';\r
+        slv_unknown_addr_o     <= '0';\r
+        slv_no_more_data_o     <= '0';\r
+        clear_counters         <= '0';\r
+      else\r
+        slv_data_out_o         <= (others => '0');\r
+        slv_unknown_addr_o     <= '0';\r
+        slv_no_more_data_o     <= '0';\r
+        clear_counters         <= '0';\r
+        \r
+        if (SLV_READ_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+\r
+            when x"0000" =>\r
+              slv_data_out_o(15 downto 0)  <=\r
+                std_logic_vector(invalid_frame_ctr);\r
+              slv_data_out_o(31 downto 16) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0001" =>\r
+              slv_data_out_o(15 downto 0)  <=\r
+                std_logic_vector(overflow_ctr);\r
+              slv_data_out_o(31 downto 16) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0002" =>\r
+              slv_data_out_o(15 downto 0)  <=\r
+                std_logic_vector(pileup_ctr);\r
+              slv_data_out_o(31 downto 16) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0003" =>\r
+              slv_data_out_o(15 downto 0)  <=\r
+                std_logic_vector(parity_error_ctr);\r
+              slv_data_out_o(31 downto 16) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+\r
+            when x"0004" =>\r
+              slv_data_out_o(19 downto 0)  <=\r
+                std_logic_vector(nx_trigger_rate);\r
+              slv_data_out_o(31 downto 20) <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+              \r
+            when others  =>\r
+              slv_unknown_addr_o           <= '1';\r
+              slv_ack_o                    <= '0';\r
+          end case;\r
+          \r
+        elsif (SLV_WRITE_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0000" =>\r
+              clear_counters               <= '1';\r
+              slv_ack_o                    <= '1';\r
+              \r
+            when others  =>\r
+              slv_unknown_addr_o           <= '1';\r
+              slv_ack_o                    <= '0';\r
+          end case;                \r
+        else\r
+          slv_ack_o <= '0';\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_FIFO_REGISTERS;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  TIMESTAMP_OUT         <= timestamp_o;\r
+  CHANNEL_OUT           <= channel_o;\r
+  TIMESTAMP_STATUS_OUT  <= timestamp_status_o;\r
+  ADC_DATA_OUT          <= adc_data_o;\r
+  DATA_VALID_OUT        <= data_valid_o;\r
+  NX_TOKEN_RETURN_OUT   <= nx_token_return_o;\r
+  NX_NOMORE_DATA_OUT    <= nx_nomore_data_o;\r
+  \r
+  -- Slave \r
+  SLV_DATA_OUT          <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT  <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT  <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT           <= slv_ack_o;\r
+end Behavioral;\r
diff --git a/mupix/source/nx_event_buffer.vhd b/mupix/source/nx_event_buffer.vhd
new file mode 100644 (file)
index 0000000..8abae5e
--- /dev/null
@@ -0,0 +1,477 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+use work.trb3_components.all;
+
+entity nx_event_buffer is
+  generic (
+    BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+    );
+  port (
+    CLK_IN                     : in  std_logic;  
+    RESET_IN                   : in  std_logic;
+    RESET_DATA_BUFFER_IN       : in  std_logic;
+    NXYTER_OFFLINE_IN          : in  std_logic;
+
+    -- Data Buffer FIFO        
+    DATA_IN                    : in  std_logic_vector(31 downto 0);
+    DATA_CLK_IN                : in  std_logic;
+    EVT_NOMORE_DATA_IN         : in  std_logic;
+
+    -- LVL2 Trigger
+    LVL2_TRIGGER_IN            : in  std_logic;
+    FAST_CLEAR_IN              : in  std_logic;
+    TRIGGER_BUSY_OUT           : out std_logic;
+     
+    --Response from FEE        
+    FEE_DATA_OUT               : out std_logic_vector(31 downto 0);
+    FEE_DATA_WRITE_OUT         : out std_logic;
+    FEE_DATA_FINISHED_OUT      : out std_logic;
+    FEE_DATA_ALMOST_FULL_IN    : in  std_logic;
+    
+    -- Slave bus         
+    SLV_READ_IN                : in  std_logic;
+    SLV_WRITE_IN               : in  std_logic;
+    SLV_DATA_OUT               : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN                : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN                : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT                : out std_logic;
+    SLV_NO_MORE_DATA_OUT       : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT       : out std_logic;
+                               
+    DEBUG_OUT                  : out std_logic_vector(15 downto 0)
+    );
+
+end entity;
+
+architecture Behavioral of nx_event_buffer is
+
+  --Data channel
+  signal fee_data_o           : std_logic_vector(31 downto 0);
+  signal fee_data_write_o     : std_logic;
+  signal fee_data_finished_o  : std_logic;
+  signal fee_almost_full_o    : std_logic;
+  signal trigger_busy_o       : std_logic;
+  signal evt_data_flush       : std_logic;
+  
+  type STATES is (S_IDLE,
+                  S_FLUSH_BUFFER_WAIT
+                  );
+  signal STATE : STATES; 
+
+  -- FIFO
+  signal fifo_reset         : std_logic;
+  signal fifo_read_enable   : std_logic;
+
+  -- FIFO Input Handler
+  signal fifo_next_word     : std_logic_vector(31 downto 0);
+  signal fifo_full          : std_logic;
+  signal fifo_write_enable  : std_logic;
+
+  -- NOMORE_DATA RS FlipFlop
+  signal flush_end          : std_logic;
+  
+  -- FIFO Read Handler
+  signal fifo_o             : std_logic_vector(31 downto 0);
+  signal fifo_empty         : std_logic;
+  signal fifo_write_ctr     : std_logic_vector(10 downto 0);
+  signal fifo_read_start    : std_logic;
+  signal fifo_read_enable_s : std_logic;
+  signal fifo_read_busy     : std_logic;
+  signal fifo_no_data       : std_logic;
+  signal fifo_read_done     : std_logic;
+  signal fifo_data          : std_logic_vector(31 downto 0);
+
+  type R_STATES is (R_IDLE,
+                    R_NOP1,
+                    R_NOP2,
+                    R_READ_WORD
+                    );
+
+  signal R_STATE : R_STATES;
+
+  -- Event Buffer Output Handler
+  signal evt_data_clk          : std_logic;
+  signal evt_data_flushed      : std_logic;
+  
+  signal fifo_read_enable_f    : std_logic;
+  signal fifo_read_enable_f2   : std_logic;
+  signal fifo_flush_ctr        : unsigned(10 downto 0);
+
+  signal evt_data_flushed_x    : std_logic;
+  signal fifo_flush_ctr_x      : unsigned(10 downto 0);
+  signal flush_end_reset    : std_logic;
+  signal flush_end_reset_x  : std_logic;
+
+  type F_STATES is (F_IDLE,
+                    F_FLUSH,
+                    F_END
+                    );
+
+  signal F_STATE, F_NEXT_STATE : F_STATES;
+
+  -- Slave Bus
+  signal slv_data_out_o        : std_logic_vector(31 downto 0);
+  signal slv_no_more_data_o    : std_logic;
+  signal slv_unknown_addr_o    : std_logic;
+  signal slv_ack_o             : std_logic;
+
+  signal register_fifo_status  : std_logic_vector(31 downto 0);
+
+  signal data_wait             : std_logic;
+
+  signal evt_data_flush_r      : std_logic;
+
+begin
+
+  DEBUG_OUT(0)           <= CLK_IN;
+  --DEBUG_OUT(1)           <= evt_data_flush_r;
+  DEBUG_OUT(2)           <= evt_data_clk;
+  DEBUG_OUT(3)           <= fifo_empty;
+  DEBUG_OUT(4)           <= fifo_read_enable;
+  DEBUG_OUT(5)           <= evt_data_flushed;
+  DEBUG_OUT(6)           <= '0';
+  DEBUG_OUT(7)           <= EVT_NOMORE_DATA_IN; 
+  --DEBUG_OUT(15 downto 8) <= evt_data_o(31 downto 24);
+
+  DEBUG_OUT(8)           <= LVL2_TRIGGER_IN;
+  DEBUG_OUT(11 downto 9) <= (others => '0');
+  DEBUG_OUT(13)          <= fee_data_write_o;
+  DEBUG_OUT(14)          <= fee_data_finished_o;
+  DEBUG_OUT(15)          <= FEE_DATA_ALMOST_FULL_IN;
+  
+  -----------------------------------------------------------------------------
+  -- 
+  -----------------------------------------------------------------------------
+
+  PROC_DATA_HANDLER: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        fee_data_finished_o  <= '0';
+        trigger_busy_o       <= '0';
+        STATE                <= S_IDLE;
+      else
+        fee_data_finished_o  <= '0';
+        trigger_busy_o       <= '1';
+
+        case STATE is
+          when S_IDLE =>
+            if (NXYTER_OFFLINE_IN = '1') then
+              fee_data_finished_o        <= '1';
+              trigger_busy_o             <= '0';
+              STATE                      <= S_IDLE;
+            elsif (LVL2_TRIGGER_IN = '1') then
+              evt_data_flush             <= '1';
+              STATE                      <= S_FLUSH_BUFFER_WAIT;
+            else
+              trigger_busy_o             <= '0';
+              STATE                      <= S_IDLE;
+            end if;
+            
+          when S_FLUSH_BUFFER_WAIT =>
+            if (evt_data_flushed = '0') then
+              STATE                      <= S_FLUSH_BUFFER_WAIT;
+            else                         
+              fee_data_finished_o        <= '1';
+              STATE                      <= S_IDLE;
+            end if;                      
+            
+        end case;
+      end if;
+    end if;
+
+  end process PROC_DATA_HANDLER;
+
+  -----------------------------------------------------------------------------
+  -- FIFO Input Handler
+  -----------------------------------------------------------------------------
+
+  -- Send data to FIFO
+  fifo_32_data_1: fifo_32_data
+    port map (
+      Data        => fifo_next_word,
+      Clock       => CLK_IN,
+      WrEn        => fifo_write_enable,
+      RdEn        => fifo_read_enable,
+      Reset       => fifo_reset,
+      Q           => fifo_o,
+      WCNT        => fifo_write_ctr,
+      Empty       => fifo_empty,
+      Full        => fifo_full
+      );
+
+  fifo_reset       <= RESET_IN or RESET_DATA_BUFFER_IN;
+  fifo_read_enable <= fifo_read_enable_f or fifo_read_enable_s;
+
+  PROC_FIFO_WRITE_HANDLER: process(CLK_IN)
+  begin
+    if(rising_edge(CLK_IN)) then
+      if(RESET_IN = '1' or RESET_DATA_BUFFER_IN = '1') then
+        fifo_write_enable   <= '0';
+      else
+        fifo_write_enable   <= '0';
+        fifo_next_word      <= x"deadbeef";
+        
+        if (DATA_CLK_IN = '1' and fifo_full = '0') then
+          fifo_next_word    <= DATA_IN;
+          fifo_write_enable <= '1';
+        end if;
+        
+      end if;
+    end if;
+  end process PROC_FIFO_WRITE_HANDLER;
+
+  PROC_FLUSH_END_RS: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' or flush_end_reset = '1') then
+        flush_end <= '0';
+      else
+        if (EVT_NOMORE_DATA_IN = '1') then
+          flush_end <= '1';
+        end if;
+      end if;
+    end if;
+  end process PROC_FLUSH_END_RS;
+  
+  PROC_FLUSH_BUFFER_TRANSFER: process(CLK_IN)
+  begin 
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        evt_data_clk         <= '0';
+        evt_data_flushed     <= '0';
+        fifo_flush_ctr       <= (others => '0');
+        fifo_read_enable_f2  <= '0';
+        flush_end_reset      <= '0';
+        F_STATE              <= F_IDLE;
+      else
+        evt_data_flushed     <= evt_data_flushed_x;
+        fifo_flush_ctr       <= fifo_flush_ctr_x;
+        flush_end_reset      <= flush_end_reset_x;
+        F_STATE              <= F_NEXT_STATE;
+
+        fifo_read_enable_f2  <= fifo_read_enable_f;
+        evt_data_clk         <= fifo_read_enable_f2;
+      end if;
+    end if;
+  end process PROC_FLUSH_BUFFER_TRANSFER;
+
+  PROC_FLUSH_BUFFER: process(F_STATE,
+                             evt_data_flush,
+                             fifo_empty,
+                             evt_data_clk,
+                             flush_end
+                             )
+  begin
+    -- Defaults
+    fifo_read_enable_f      <= '0';
+    fifo_flush_ctr_x        <= fifo_flush_ctr;
+    evt_data_flushed_x      <= '0';
+    flush_end_reset_x       <= '0';
+
+    -- Multiplexer fee_data_o
+    if (evt_data_clk = '1') then
+      fee_data_o                 <= fifo_o;
+      fee_data_write_o           <= '1';
+    else
+      fee_data_o                 <= (others => '1');
+      fee_data_write_o           <= '0';
+    end if;
+    
+    -- FIFO Read Handler
+    case F_STATE is 
+      when F_IDLE =>
+        if (evt_data_flush = '1') then
+          fifo_flush_ctr_x       <= (others => '0');
+          flush_end_reset_x      <= '1';
+          F_NEXT_STATE           <= F_FLUSH;
+        else
+          F_NEXT_STATE           <= F_IDLE; 
+        end if;
+            
+      when F_FLUSH =>
+        if (fifo_empty = '0') then
+          fifo_read_enable_f     <= '1';
+          fifo_flush_ctr_x       <= fifo_flush_ctr + 1; 
+          F_NEXT_STATE           <= F_FLUSH; 
+        else
+          if (flush_end = '0') then
+            F_NEXT_STATE         <= F_FLUSH;
+          else
+            F_NEXT_STATE         <= F_END;
+          end if;
+        end if;
+
+      when F_END =>
+        evt_data_flushed_x       <= '1';
+        F_NEXT_STATE             <= F_IDLE;
+        
+    end case;
+  end process PROC_FLUSH_BUFFER;
+
+  -----------------------------------------------------------------------------
+  -- FIFO Output Handler
+  -----------------------------------------------------------------------------
+  
+  PROC_FIFO_READ_WORD: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        fifo_read_enable_s    <= '0';
+        fifo_read_busy        <= '0';
+        fifo_data             <= (others => '0');
+        fifo_read_done        <= '0';
+        fifo_no_data          <= '1';
+        R_STATE               <= R_IDLE;
+      else                    
+        fifo_read_busy        <= '0';
+        fifo_no_data          <= '0';
+        fifo_read_done        <= '0';
+        fifo_data             <= (others => '0');
+        fifo_read_enable_s    <= '0';
+
+        case R_STATE is 
+          when R_IDLE =>
+            if (fifo_read_start = '1') then
+              if (fifo_empty = '0') then
+                fifo_read_enable_s <= '1';
+                fifo_read_busy     <= '1';
+                R_STATE            <= R_NOP1;
+              else
+                fifo_no_data       <= '1';
+                fifo_read_done     <= '1';
+                R_STATE            <= R_IDLE;
+              end if;
+            else
+              R_STATE              <= R_IDLE;
+            end if;
+
+          when R_NOP1 =>
+            fifo_read_busy         <= '1';
+            R_STATE                <= R_NOP2;
+                                   
+          when R_NOP2 =>           
+            fifo_read_busy         <= '1';
+            R_STATE                <= R_READ_WORD;
+                                   
+          when R_READ_WORD =>      
+            fifo_read_busy         <= '0';
+            fifo_data              <= fifo_o;
+            fifo_read_done         <= '1';
+            R_STATE                <= R_IDLE;
+            
+        end case; 
+      end if;
+    end if;
+
+  end process PROC_FIFO_READ_WORD;
+  
+  -----------------------------------------------------------------------------
+  -- Slave Bus Slow Control
+  -----------------------------------------------------------------------------
+
+  register_fifo_status(0)            <= fifo_write_enable;
+  register_fifo_status(1)            <= fifo_full;
+  register_fifo_status(3 downto 2)   <= (others => '0');
+  register_fifo_status(4)            <= fifo_read_enable;
+  register_fifo_status(5)            <= fifo_empty;
+  register_fifo_status(7 downto 6)   <= (others => '0');
+  register_fifo_status(31 downto 8)  <= (others => '0');
+
+  PROC_SLAVE_BUS: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        slv_data_out_o         <= (others => '0');
+        slv_ack_o              <= '0';
+        slv_unknown_addr_o     <= '0';
+        slv_no_more_data_o     <= '0';
+                               
+        fifo_read_start        <= '0';
+        data_wait              <= '0';
+        evt_data_flush_r       <= '0'; 
+      else                     
+        slv_data_out_o         <= (others => '0');
+        slv_ack_o              <= '0';
+        slv_unknown_addr_o     <= '0';
+        slv_no_more_data_o     <= '0';
+                               
+        fifo_read_start        <= '0';
+        data_wait              <= '0';
+        evt_data_flush_r       <= '0';
+        
+        if (data_wait = '1') then
+          if (fifo_read_done = '0') then
+            data_wait                      <= '1';
+          else
+            if (fifo_no_data = '0') then
+              slv_data_out_o               <= fifo_data;
+              slv_ack_o                    <= '1';
+            else                           
+              slv_no_more_data_o           <= '1';
+              slv_ack_o                    <= '0';
+            end if;                        
+            data_wait                      <= '0';
+          end if;
+
+        elsif (SLV_READ_IN  = '1') then
+          case SLV_ADDR_IN is
+            when x"0000" =>
+              fifo_read_start              <= '1';
+              data_wait                    <= '1';
+
+            when x"0001" =>
+              slv_data_out_o(10 downto 0)  <= fifo_write_ctr;
+              slv_data_out_o(31 downto 11) <= (others => '0');
+              slv_ack_o                    <= '1';
+
+            when x"0002" =>
+              slv_data_out_o(10 downto 0)  <= std_logic_vector(fifo_flush_ctr);
+              slv_data_out_o(31 downto 11) <= (others => '0');
+              slv_ack_o                    <= '1';
+
+            when x"0003" =>
+              slv_data_out_o               <= register_fifo_status;
+              slv_ack_o                    <= '1';
+              
+            when others  =>
+              slv_unknown_addr_o           <= '1';
+          end case;
+            
+        elsif (SLV_WRITE_IN  = '1') then
+          case SLV_ADDR_IN is
+
+            when x"0000" =>
+              evt_data_flush_r             <= '1';
+              slv_ack_o                    <= '1';
+              
+            when others  =>
+              slv_unknown_addr_o           <= '1';              
+              slv_ack_o                    <= '0';
+          end case;                
+          
+        else
+          slv_ack_o                        <= '0';
+        end if;
+      end if;
+    end if;
+  end process PROC_SLAVE_BUS;
+
+-- Output Signals
+  TRIGGER_BUSY_OUT       <= trigger_busy_o;
+  
+  FEE_DATA_OUT           <= fee_data_o;
+  FEE_DATA_WRITE_OUT     <= fee_data_write_o;
+  FEE_DATA_FINISHED_OUT  <= fee_data_finished_o;
+  
+  SLV_DATA_OUT           <= slv_data_out_o;    
+  SLV_NO_MORE_DATA_OUT   <= slv_no_more_data_o; 
+  SLV_UNKNOWN_ADDR_OUT   <= slv_unknown_addr_o;
+  SLV_ACK_OUT            <= slv_ack_o;
+
+end Behavioral;
diff --git a/mupix/source/nx_fpga_timestamp.vhd b/mupix/source/nx_fpga_timestamp.vhd
new file mode 100644 (file)
index 0000000..1262c19
--- /dev/null
@@ -0,0 +1,127 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+
+entity nx_fpga_timestamp is
+  port (
+    CLK_IN                : in  std_logic;
+    RESET_IN              : in  std_logic;
+
+    TIMESTAMP_SYNC_IN     : in  std_logic;
+    TRIGGER_IN            : in  std_logic;
+
+    TIMESTAMP_OUT         : out unsigned(11 downto 0);
+    NX_TIMESTAMP_SYNC_OUT : out std_logic;
+
+    -- Slave bus         
+    SLV_READ_IN           : in  std_logic;
+    SLV_WRITE_IN          : in  std_logic;
+    SLV_DATA_OUT          : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN           : in  std_logic_vector(31 downto 0);
+    SLV_ACK_OUT           : out std_logic;
+    SLV_NO_MORE_DATA_OUT  : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT  : out std_logic;
+    
+    -- Debug Line
+    DEBUG_OUT             : out std_logic_vector(15 downto 0)
+    );
+end entity;
+
+architecture Behavioral of nx_fpga_timestamp is
+
+  signal timestamp_ctr       : unsigned(11 downto 0);
+  signal timestamp_o         : unsigned(11 downto 0);
+  signal trigger_x           : std_logic;
+  signal trigger_l           : std_logic;
+  signal trigger             : std_logic;
+  signal timestamp_sync_x    : std_logic;
+  signal timestamp_sync_l    : std_logic;
+  signal timestamp_sync      : std_logic;
+
+  signal nx_timestamp_sync_o : std_logic;
+  
+begin
+
+  DEBUG_OUT(0)           <= CLK_IN;
+  DEBUG_OUT(1)           <= trigger;
+  DEBUG_OUT(2)           <= timestamp_sync;
+  DEBUG_OUT(3)           <= '0';
+  DEBUG_OUT(15 downto 4) <= TIMESTAMP_OUT;
+  
+  -- Cross the abyss for trigger and sync signal
+
+  PROC_SYNC: process (CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if (RESET_IN = '1') then
+        trigger_x        <= '0';
+        trigger_l        <= '0';
+        timestamp_sync_x <= '0';
+        timestamp_sync_l <= '0';
+      else
+        trigger_x        <= TRIGGER_IN;
+        trigger_l        <= trigger_x;
+        timestamp_sync_x <= TIMESTAMP_SYNC_IN;
+        timestamp_sync_l <= timestamp_sync_x;
+      end if;
+    end if;
+  end process PROC_SYNC;
+
+  -- Convert TRIGGER_IN to Pulse
+
+  level_to_pulse_1: level_to_pulse
+    port map (
+      CLK_IN    => CLK_IN,
+      RESET_IN  => RESET_IN,
+      LEVEL_IN  => trigger_l,
+      PULSE_OUT => trigger
+      );
+
+  -- Convert TIMESTAMP_SYNC_IN to Pulse
+
+  level_to_pulse_2: level_to_pulse
+    port map (
+      CLK_IN    => CLK_IN,
+      RESET_IN  => RESET_IN,
+      LEVEL_IN  => timestamp_sync_l,
+      PULSE_OUT => timestamp_sync
+      );
+
+  -- Timestamp Process + Trigger
+  
+  PROC_TIMESTAMP_CTR: process (CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        timestamp_ctr       <= (others => '0');
+        timestamp_o         <= (others => '0');
+        nx_timestamp_sync_o <= '0';
+      else
+        nx_timestamp_sync_o <= '0';
+        
+        if (timestamp_sync = '1') then
+          timestamp_ctr       <= (others => '0');
+          timestamp_o         <= (others => '0');
+          nx_timestamp_sync_o <= '1';
+        else
+          if (trigger = '1') then
+            timestamp_o       <= timestamp_ctr - 3;
+          end if;
+          timestamp_ctr       <= timestamp_ctr + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  
+  -----------------------------------------------------------------------------
+  -- Output Signals
+  -----------------------------------------------------------------------------
+
+  TIMESTAMP_OUT         <= timestamp_o;
+  NX_TIMESTAMP_SYNC_OUT <= nx_timestamp_sync_o;
+
+end Behavioral;
diff --git a/mupix/source/nx_histograms.vhd b/mupix/source/nx_histograms.vhd
new file mode 100644 (file)
index 0000000..e998cb1
--- /dev/null
@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity nx_histograms is
+  generic (
+    NUM_BINS : integer   := 7
+    );
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+                         
+    RESET_HISTS_IN       : in  std_logic;
+                         
+    CHANNEL_STAT_FILL_IN : in  std_logic;
+    CHANNEL_ID_IN        : in  std_logic_vector(NUM_BINS - 1 downto 0);
+
+    -- Slave bus         
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+    
+end entity;
+
+architecture nx_histograms of nx_histograms is
+
+  type histogram_t is array(0 to 127) of unsigned(31 downto 0);
+  signal hist_channel_stat    : histogram_t;
+
+  -- Slave Bus                    
+  signal slv_data_out_o       : std_logic_vector(31 downto 0);
+  signal slv_no_more_data_o   : std_logic;
+  signal slv_unknown_addr_o   : std_logic;
+  signal slv_ack_o            : std_logic;
+  signal reset_hists_r        : std_logic;
+  
+begin
+  
+  PROC_CHANNEL_HIST : process (CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then
+        for I in (NUM_BINS - 1) downto 0 loop
+         hist_channel_stat(I) <= (others => '0');
+        end loop;
+      else
+        if (CHANNEL_STAT_FILL_IN = '1') then
+          hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
+            hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
+        end if;
+      end if;
+    end if;
+  end process PROC_CHANNEL_HIST;  
+
+
+  -----------------------------------------------------------------------------
+  -- TRBNet Slave Bus
+  -----------------------------------------------------------------------------
+ -- Give status info to the TRB Slow Control Channel
+  PROC_HISTOGRAMS_READ: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        slv_data_out_o       <= (others => '0');
+        slv_no_more_data_o   <= '0';
+        slv_unknown_addr_o   <= '0';
+        slv_ack_o            <= '0';
+        reset_hists_r        <= '0';
+      else
+        slv_data_out_o       <= (others => '0');
+        slv_unknown_addr_o   <= '0';
+        slv_no_more_data_o   <= '0';
+        slv_ack_o            <= '0';
+
+        reset_hists_r        <= '0';
+        
+        if (SLV_READ_IN  = '1') then
+          if (unsigned(SLV_ADDR_IN) >= x"0000" and
+              unsigned(SLV_ADDR_IN) <  x"0080") then
+            slv_data_out_o           <= std_logic_vector(
+              hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
+              );
+            slv_ack_o                <= '1';
+          else
+            slv_unknown_addr_o       <= '1';
+          end if;
+                    
+        elsif (SLV_WRITE_IN  = '1') then
+
+          case SLV_ADDR_IN is
+
+            when x"0000" =>
+              reset_hists_r          <= '1';
+              slv_ack_o              <= '1';
+
+            when others =>
+              slv_unknown_addr_o     <= '1';
+
+          end case;
+        end if;
+      end if;
+    end if;     
+  end process PROC_HISTOGRAMS_READ;
+  
+  -----------------------------------------------------------------------------
+  -- Output Signals
+  -----------------------------------------------------------------------------
+
+  -- Slave 
+  SLV_DATA_OUT          <= slv_data_out_o;    
+  SLV_NO_MORE_DATA_OUT  <= slv_no_more_data_o; 
+  SLV_UNKNOWN_ADDR_OUT  <= slv_unknown_addr_o;
+  SLV_ACK_OUT           <= slv_ack_o;
+
+  end nx_histograms;
diff --git a/mupix/source/nx_i2c_master.vhd b/mupix/source/nx_i2c_master.vhd
new file mode 100644 (file)
index 0000000..2ac23de
--- /dev/null
@@ -0,0 +1,548 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_i2c_master is\r
+  generic (\r
+    I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
+    );\r
+  port(\r
+    CLK_IN               : in    std_logic;\r
+    RESET_IN             : in    std_logic;\r
+\r
+    -- I2C connections\r
+    SDA_INOUT            : inout std_logic;\r
+    SCL_INOUT            : inout std_logic;\r
+\r
+    -- Internal Interface\r
+    INTERNAL_COMMAND_IN  : in    std_logic_vector(31 downto 0);\r
+    COMMAND_BUSY_OUT     : out   std_logic;\r
+    I2C_DATA_OUT         : out   std_logic_vector(31 downto 0);\r
+    I2C_LOCK_IN          : in    std_logic;\r
+    \r
+    -- Slave bus         \r
+    SLV_READ_IN          : in    std_logic;\r
+    SLV_WRITE_IN         : in    std_logic;\r
+    SLV_DATA_OUT         : out   std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in    std_logic_vector(31 downto 0);\r
+    SLV_ACK_OUT          : out   std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out   std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out   std_logic;\r
+    \r
+    -- Debug Line\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_master is\r
+\r
+  signal sda_i                 : std_logic;\r
+  signal sda_x                 : std_logic;\r
+  signal sda                   : std_logic;\r
+                               \r
+  signal scl_i                 : std_logic;\r
+  signal scl_x                 : std_logic;\r
+  signal scl                   : std_logic;\r
+  signal command_busy_o        : std_logic;\r
+\r
+  -- I2C Master  \r
+  signal sda_o                 : std_logic;\r
+  signal scl_o                 : std_logic;\r
+  signal i2c_start             : std_logic;\r
+\r
+  signal i2c_busy              : std_logic;\r
+  signal startstop_select      : std_logic;\r
+  signal startstop_seq_start   : std_logic;\r
+  signal sendbyte_seq_start    : std_logic;\r
+  signal readbyte_seq_start    : std_logic;\r
+  signal sendbyte_byte         : std_logic_vector(7 downto 0);\r
+  signal read_seq_ctr          : std_logic;\r
+  signal i2c_data              : std_logic_vector(31 downto 0);\r
+\r
+  signal i2c_busy_x            : std_logic;\r
+  signal startstop_select_x    : std_logic;\r
+  signal startstop_seq_start_x : std_logic;\r
+  signal sendbyte_seq_start_x  : std_logic;\r
+  signal sendbyte_byte_x       : std_logic_vector(7 downto 0);\r
+  signal readbyte_seq_start_x  : std_logic;\r
+  signal read_seq_ctr_x        : std_logic;\r
+  signal i2c_data_x            : std_logic_vector(31 downto 0);\r
+  \r
+  signal sda_startstop         : std_logic;\r
+  signal scl_startstop         : std_logic;\r
+  signal i2c_notready          : std_logic;\r
+  signal startstop_done        : std_logic;\r
+\r
+  signal sda_sendbyte          : std_logic;\r
+  signal scl_sendbyte          : std_logic;\r
+  signal sendbyte_ack          : std_logic;\r
+  signal sendbyte_done         : std_logic;\r
+  \r
+  signal sda_readbyte          : std_logic;\r
+  signal scl_readbyte          : std_logic;\r
+  signal readbyte_byte         : std_logic_vector(7 downto 0);\r
+  signal readbyte_done         : std_logic;\r
+  \r
+  type STATES is (S_RESET,\r
+                  S_IDLE,\r
+                  S_START,\r
+                  S_START_WAIT,\r
+\r
+                  S_SEND_CHIP_ID,\r
+                  S_SEND_CHIP_ID_WAIT,\r
+                  S_SEND_REGISTER,\r
+                  S_SEND_REGISTER_WAIT,\r
+                  S_SEND_DATA,\r
+                  S_SEND_DATA_WAIT,\r
+                  S_GET_DATA,\r
+                  S_GET_DATA_WAIT,\r
+\r
+                  S_STOP,\r
+                  S_STOP_WAIT\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+\r
+  -- TRBNet Slave Bus            \r
+  signal slv_data_out_o          : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o      : std_logic;\r
+  signal slv_unknown_addr_o      : std_logic;\r
+  signal slv_ack_o               : std_logic;\r
+\r
+  signal i2c_chipid              : std_logic_vector(6 downto 0);\r
+  signal i2c_rw_bit              : std_logic;\r
+  signal i2c_registerid          : std_logic_vector(7 downto 0);\r
+  signal i2c_register_data       : std_logic_vector(7 downto 0);\r
+  signal i2c_register_value_read : std_logic_vector(7 downto 0);\r
+\r
+  signal disable_slave_bus       : std_logic; \r
+  signal internal_command        : std_logic;\r
+  signal internal_command_d      : std_logic;\r
+  signal i2c_data_internal_o     : std_logic_vector(31 downto 0);\r
+  signal i2c_data_slave          : std_logic_vector(31 downto 0);\r
+\r
+begin\r
+\r
+  -- Debug\r
+  DEBUG_OUT(0)            <= CLK_IN;\r
+  DEBUG_OUT(8 downto 1)   <= i2c_data(7 downto 0);\r
+  DEBUG_OUT(12 downto 9)  <= i2c_data(31 downto 28);\r
+  DEBUG_OUT(13)           <= i2c_busy;\r
+  DEBUG_OUT(14)           <= internal_command;\r
+  DEBUG_OUT(15)           <= internal_command_d;\r
+\r
+  -- Start / Stop Sequence\r
+  nx_i2c_startstop_1: nx_i2c_startstop\r
+    generic map (\r
+      I2C_SPEED => I2C_SPEED\r
+      )\r
+    port map (\r
+      CLK_IN            => CLK_IN,\r
+      RESET_IN          => RESET_IN,\r
+      START_IN          => startstop_seq_start,\r
+      SELECT_IN         => startstop_select,\r
+      SEQUENCE_DONE_OUT => startstop_done,\r
+      SDA_OUT           => sda_startstop,\r
+      SCL_OUT           => scl_startstop,\r
+      NREADY_OUT        => i2c_notready\r
+      );\r
+\r
+  nx_i2c_sendbyte_1: nx_i2c_sendbyte\r
+    generic map (\r
+      I2C_SPEED => I2C_SPEED\r
+      )\r
+    port map (\r
+      CLK_IN            => CLK_IN,\r
+      RESET_IN          => RESET_IN,\r
+      START_IN          => sendbyte_seq_start,\r
+      BYTE_IN           => sendbyte_byte,\r
+      SEQUENCE_DONE_OUT => sendbyte_done,\r
+      SDA_OUT           => sda_sendbyte,\r
+      SCL_OUT           => scl_sendbyte,\r
+      SDA_IN            => sda,\r
+      ACK_OUT           => sendbyte_ack\r
+      );\r
+\r
+  nx_i2c_readbyte_1: nx_i2c_readbyte\r
+    generic map (\r
+      I2C_SPEED => I2C_SPEED\r
+      )\r
+    port map (\r
+      CLK_IN            => CLK_IN,\r
+      RESET_IN          => RESET_IN,\r
+      START_IN          => readbyte_seq_start,\r
+      BYTE_OUT          => readbyte_byte,\r
+      SEQUENCE_DONE_OUT => readbyte_done,\r
+      SDA_OUT           => sda_readbyte,\r
+      SCL_OUT           => scl_readbyte,\r
+      SDA_IN            => sda\r
+      );\r
+  \r
+   -- Sync I2C Lines\r
+  sda_i <= SDA_INOUT;\r
+  scl_i <= SCL_INOUT;\r
+\r
+  PROC_I2C_LINES_SYNC: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sda_x <= '1';\r
+        sda   <= '1';\r
+\r
+        scl_x <= '1';\r
+        scl   <= '1';\r
+      else\r
+        sda_x <= sda_i;\r
+        sda   <= sda_x;\r
+\r
+        scl_x <= scl_i;\r
+        scl   <= scl_x;\r
+      end if;\r
+    end if;\r
+  end process PROC_I2C_LINES_SYNC;\r
+\r
+  PROC_I2C_MASTER_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        i2c_busy              <= '1';\r
+        startstop_select      <= '0';\r
+        startstop_seq_start   <= '0';\r
+        sendbyte_seq_start    <= '0';\r
+        readbyte_seq_start    <= '0';\r
+        sendbyte_byte         <= (others => '0');\r
+        i2c_data              <= (others => '0');\r
+        read_seq_ctr          <= '0';\r
+        STATE                 <= S_RESET;\r
+      else\r
+        i2c_busy              <= i2c_busy_x;\r
+        startstop_select      <= startstop_select_x;\r
+        startstop_seq_start   <= startstop_seq_start_x;\r
+        sendbyte_seq_start    <= sendbyte_seq_start_x;\r
+        readbyte_seq_start    <= readbyte_seq_start_x;\r
+        sendbyte_byte         <= sendbyte_byte_x;\r
+        i2c_data              <= i2c_data_x;\r
+        read_seq_ctr          <= read_seq_ctr_x;\r
+        STATE                 <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_I2C_MASTER_TRANSFER;\r
+  \r
+        \r
+  PROC_I2C_MASTER: process(STATE,\r
+                           i2c_start,\r
+                           startstop_done,\r
+                           read_seq_ctr,\r
+                           sendbyte_done,\r
+                           sendbyte_ack,\r
+                           readbyte_done,\r
+                           startstop_done\r
+                           )\r
+\r
+  begin\r
+    -- Defaults\r
+    sda_o                   <= '1';\r
+    scl_o                   <= '1';\r
+    i2c_busy_x              <= '1';\r
+    startstop_select_x      <= '0';\r
+    startstop_seq_start_x   <= '0';\r
+    sendbyte_seq_start_x    <= '0';\r
+    sendbyte_byte_x         <= (others => '0');\r
+    readbyte_seq_start_x    <= '0';\r
+    i2c_data_x              <= i2c_data;\r
+    read_seq_ctr_x          <= read_seq_ctr;\r
+    \r
+    case STATE is\r
+\r
+      when S_RESET =>\r
+        i2c_data_x        <= (others => '0');\r
+        NEXT_STATE        <= S_IDLE;\r
+        \r
+      when S_IDLE =>\r
+        if (i2c_start = '1') then\r
+          i2c_data_x      <= x"8000_0000"; -- Set Running, clear all other bits \r
+          NEXT_STATE      <= S_START;\r
+        else\r
+          i2c_busy_x      <= '0';\r
+          i2c_data_x      <= i2c_data and x"7fff_ffff";  -- clear running bit;\r
+          read_seq_ctr_x  <= '0';\r
+          NEXT_STATE      <= S_IDLE;\r
+        end if;\r
+            \r
+        -- I2C START Sequence \r
+      when S_START =>\r
+        startstop_select_x    <= '1';\r
+        startstop_seq_start_x <= '1';\r
+        NEXT_STATE            <= S_START_WAIT;\r
+        \r
+      when S_START_WAIT =>\r
+        if (startstop_done = '0') then\r
+          NEXT_STATE <= S_START_WAIT;\r
+        else\r
+          sda_o      <= '0';\r
+          scl_o      <= '0';\r
+          NEXT_STATE <= S_SEND_CHIP_ID;\r
+        end if;\r
+                   \r
+        -- I2C SEND ChipId Sequence\r
+      when S_SEND_CHIP_ID =>\r
+        scl_o <= '0';\r
+        sendbyte_byte_x(7 downto 1) <= i2c_chipid;\r
+        if (read_seq_ctr = '0') then\r
+          sendbyte_byte_x(0)        <= '0';\r
+        else\r
+          sendbyte_byte_x(0)        <= '1';\r
+        end if;\r
+        sendbyte_seq_start_x        <= '1';\r
+        NEXT_STATE                  <= S_SEND_CHIP_ID_WAIT;\r
+        \r
+      when S_SEND_CHIP_ID_WAIT =>\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
+        else\r
+          scl_o      <= '0';\r
+          if (sendbyte_ack = '0') then\r
+            i2c_data_x <= i2c_data or x"0100_0000";\r
+            NEXT_STATE <= S_STOP;\r
+          else\r
+            if (read_seq_ctr = '0') then\r
+              read_seq_ctr_x <= '1';\r
+              NEXT_STATE <= S_SEND_REGISTER;\r
+            else\r
+              NEXT_STATE <= S_GET_DATA;\r
+            end if;\r
+          end if;\r
+        end if;\r
+        \r
+        -- I2C SEND RegisterId\r
+      when S_SEND_REGISTER =>\r
+        scl_o <= '0';\r
+        sendbyte_byte_x       <= i2c_registerid;          \r
+        sendbyte_seq_start_x  <= '1';\r
+        NEXT_STATE            <= S_SEND_REGISTER_WAIT;\r
+        \r
+      when S_SEND_REGISTER_WAIT =>\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
+        else\r
+          scl_o      <= '0';\r
+          if (sendbyte_ack = '0') then\r
+            i2c_data_x <= i2c_data or x"0200_0000";\r
+            NEXT_STATE <= S_STOP;\r
+          else\r
+            if (i2c_rw_bit = '0') then\r
+              NEXT_STATE <= S_SEND_DATA;\r
+            else\r
+              NEXT_STATE <= S_START;\r
+            end if;\r
+          end if;\r
+        end if;\r
+\r
+        -- I2C SEND DataWord\r
+      when S_SEND_DATA =>\r
+        scl_o <= '0';\r
+        sendbyte_byte_x        <= i2c_register_data;\r
+        sendbyte_seq_start_x   <= '1';\r
+        NEXT_STATE             <= S_SEND_DATA_WAIT;\r
+        \r
+      when S_SEND_DATA_WAIT =>\r
+        if (sendbyte_done = '0') then\r
+          NEXT_STATE <= S_SEND_DATA_WAIT;\r
+        else\r
+          scl_o      <= '0';\r
+          if (sendbyte_ack = '0') then\r
+            i2c_data_x <= i2c_data or x"0400_0000";\r
+          end if;\r
+          NEXT_STATE <= S_STOP;\r
+        end if;\r
+\r
+        -- I2C GET DataWord\r
+      when S_GET_DATA =>\r
+        scl_o <= '0';\r
+        readbyte_seq_start_x   <= '1';\r
+        NEXT_STATE             <= S_GET_DATA_WAIT;\r
+        \r
+      when S_GET_DATA_WAIT =>\r
+        if (readbyte_done = '0') then\r
+          NEXT_STATE <= S_GET_DATA_WAIT;\r
+        else\r
+          scl_o                  <= '0';\r
+          i2c_data_x(7 downto 0) <= readbyte_byte; \r
+          NEXT_STATE             <= S_STOP;\r
+        end if;\r
+        \r
+        -- I2C STOP Sequence \r
+      when S_STOP =>\r
+        sda_o                 <= '0';\r
+        scl_o                 <= '0';\r
+        startstop_select_x    <= '0';\r
+        startstop_seq_start_x <= '1';\r
+        NEXT_STATE            <= S_STOP_WAIT;\r
+        \r
+      when S_STOP_WAIT =>\r
+        if (startstop_done = '0') then\r
+          NEXT_STATE <= S_STOP_WAIT;\r
+        else\r
+          i2c_data_x           <= i2c_data or x"4000_0000"; -- Set DONE Bit\r
+          NEXT_STATE           <= S_IDLE;\r
+        end if;\r
+        \r
+    end case;\r
+  end process PROC_I2C_MASTER;\r
+\r
+  PROC_I2C_DATA_MULTIPLEXER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        i2c_data_internal_o   <= (others => '0');\r
+        i2c_data_slave        <= (others => '0');\r
+        command_busy_o        <= '0';\r
+      else\r
+        if (internal_command = '0' and internal_command_d = '0') then  \r
+          i2c_data_slave      <= i2c_data;\r
+        else\r
+          i2c_data_internal_o <= i2c_data;\r
+        end if;\r
+      end if;\r
+      command_busy_o      <= i2c_busy;\r
+    end if;\r
+  end process PROC_I2C_DATA_MULTIPLEXER;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+  --\r
+  --   Write bit definition\r
+  --   ====================\r
+  -- \r
+  --   D[31]    I2C_GO          0 => don't do anything on I2C,\r
+  --                            1 => start I2C access\r
+  --   D[30]    I2C_ACTION      0 => write byte, 1 => read byte\r
+  --   D[29:24] I2C_SPEED       set all to '1'\r
+  --   D[23:16] I2C_ADDRESS     address of I2C chip\r
+  --   D[15:8]  I2C_CMD         command byte for access\r
+  --   D[7:0]   I2C_DATA        data to be written\r
+  --   \r
+  --   Read bit definition\r
+  --   ===================\r
+  --   \r
+  --   D[31]    RUNNING         whatever\r
+  --   D[30]    I2C_DONE        whatever\r
+  --   D[29]    ERROR_RADDACK   no acknowledge for repeated address byte\r
+  --   D[28]    ERROR_RSTART    generation of repeated START condition failed\r
+  --   D[27]    ERROR_DATACK    no acknowledge for data byte\r
+  --   D[26]    ERROR_CMDACK    no acknowledge for command byte\r
+  --   D[25]    ERROR_ADDACK    no acknowledge for address byte\r
+  --   D[24]    ERROR_START     generation of START condition failed\r
+  --   D[23:21] reserved        reserved\r
+  --   D[20:16] debug           subject to change, don't use\r
+  --   D[15:8]  reserved        reserved\r
+  --   D[7:0]   I2C_DATA        result of I2C read operation\r
+  --\r
+  \r
+  PROC_SLAVE_BUS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o     <= (others => '0');\r
+        slv_no_more_data_o <= '0';\r
+        slv_unknown_addr_o <= '0';\r
+        slv_ack_o          <= '0';\r
+        i2c_start          <= '0';\r
+        internal_command   <= '0';\r
+        internal_command_d <= '0';\r
+\r
+        i2c_chipid              <= (others => '0');    \r
+        i2c_rw_bit              <= '0';    \r
+        i2c_registerid          <= (others => '0');    \r
+        i2c_register_data       <= (others => '0');    \r
+        i2c_register_value_read <= (others => '0');\r
+            \r
+      else\r
+        slv_unknown_addr_o <= '0';\r
+        slv_no_more_data_o <= '0';\r
+        slv_data_out_o     <= (others => '0');\r
+        i2c_start          <= '0';\r
+\r
+        internal_command_d   <= internal_command;\r
+                \r
+        if (i2c_busy = '0' and internal_command_d = '1') then\r
+          internal_command     <= '0';\r
+          slv_ack_o            <= '0';\r
+\r
+        elsif (i2c_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then\r
+          -- Internal Interface Command\r
+          i2c_rw_bit           <= INTERNAL_COMMAND_IN(30);\r
+          i2c_chipid           <= INTERNAL_COMMAND_IN(22 downto 16);\r
+          i2c_registerid       <= INTERNAL_COMMAND_IN(15 downto 8);\r
+          i2c_register_data    <= INTERNAL_COMMAND_IN(7 downto 0); \r
+          i2c_start            <= '1';\r
+          internal_command     <= '1';\r
+          slv_ack_o            <= '0';\r
+\r
+        elsif (SLV_WRITE_IN  = '1') then\r
+          if (internal_command = '0' and\r
+              I2C_LOCK_IN      = '0' and\r
+              i2c_busy         = '0' and\r
+              SLV_DATA_IN(31)  = '1') then\r
+            i2c_rw_bit         <= SLV_DATA_IN(30);\r
+            i2c_chipid         <= SLV_DATA_IN(22 downto 16);\r
+            i2c_registerid     <= SLV_DATA_IN(15 downto 8);\r
+            i2c_register_data  <= SLV_DATA_IN(7 downto 0); \r
+            i2c_start          <= '1';\r
+            slv_ack_o          <= '1';\r
+          else\r
+            slv_no_more_data_o <= '1';\r
+            slv_ack_o          <= '0';\r
+          end if;\r
+          \r
+        elsif (SLV_READ_IN = '1') then\r
+          if (internal_command = '0' and\r
+              I2C_LOCK_IN      = '0' and\r
+              i2c_busy         = '0') then\r
+            slv_data_out_o     <= i2c_data_slave;\r
+            slv_ack_o          <= '1';\r
+          else\r
+            slv_data_out_o     <= (others => '0');\r
+            slv_no_more_data_o <= '1';\r
+            slv_ack_o          <= '0';\r
+          end if;\r
+\r
+        else\r
+          slv_ack_o            <= '0';\r
+        end if;\r
+\r
+      end if;\r
+    end if;           \r
+  end process PROC_SLAVE_BUS;\r
+\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- I2C Outputs\r
+  SDA_INOUT        <= '0' when (sda_o = '0' or\r
+                                sda_startstop = '0' or\r
+                                sda_sendbyte = '0' or\r
+                                sda_readbyte = '0')\r
+                      else 'Z';\r
+  \r
+  SCL_INOUT        <= '0' when (scl_o = '0' or\r
+                                scl_startstop = '0' or\r
+                                scl_sendbyte = '0' or\r
+                                scl_readbyte = '0')\r
+                      else 'Z';\r
+\r
+  COMMAND_BUSY_OUT <= command_busy_o;\r
+  I2C_DATA_OUT     <= i2c_data_internal_o;\r
+\r
+  -- Slave Bus\r
+  SLV_DATA_OUT         <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT          <= slv_ack_o; \r
+\r
+end Behavioral;\r
diff --git a/mupix/source/nx_i2c_readbyte.vhd b/mupix/source/nx_i2c_readbyte.vhd
new file mode 100644 (file)
index 0000000..239aea6
--- /dev/null
@@ -0,0 +1,244 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity nx_i2c_readbyte is\r
+  generic (\r
+    I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
+    );\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    START_IN             : in  std_logic;\r
+    BYTE_OUT             : out std_logic_vector(7 downto 0);\r
+    SEQUENCE_DONE_OUT    : out std_logic;\r
+\r
+    -- I2C connections\r
+    SDA_OUT              : out std_logic;\r
+    SCL_OUT              : out std_logic;\r
+    SDA_IN               : in  std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_readbyte is\r
+\r
+  -- Send Byte  \r
+  signal sda_o             : std_logic;\r
+  signal scl_o             : std_logic;\r
+  signal i2c_start         : std_logic;\r
+\r
+  signal sequence_done_o   : std_logic;\r
+  signal i2c_byte          : unsigned(7 downto 0);\r
+  signal bit_ctr           : unsigned(3 downto 0);\r
+  signal i2c_ack_o         : std_logic;\r
+  signal wait_timer_init   : unsigned(11 downto 0);\r
+\r
+  signal sequence_done_o_x : std_logic;\r
+  signal i2c_byte_x        : unsigned(7 downto 0);\r
+  signal bit_ctr_x         : unsigned(3 downto 0);\r
+  signal i2c_ack_o_x       : std_logic;\r
+  signal wait_timer_init_x : unsigned(11 downto 0);\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_INIT,\r
+                  S_INIT_WAIT,\r
+\r
+                  S_READ_BYTE,\r
+                  S_UNSET_SCL1,\r
+                  S_SET_SCL1,\r
+                  S_GET_BIT,\r
+                  S_SET_SCL2,\r
+                  S_UNSET_SCL2,\r
+                  S_NEXT_BIT,\r
+\r
+                  S_SET_ACK,\r
+                  S_ACK_SET_SCL,\r
+                  S_ACK_UNSET_SCL\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+  \r
+  -- Wait Timer\r
+  signal wait_timer_done    : std_logic;\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map(\r
+      CTR_WIDTH => 12\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+\r
+  PROC_READ_BYTE_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sequence_done_o  <= '0';\r
+        bit_ctr          <= (others => '0');\r
+        i2c_ack_o        <= '0';\r
+        wait_timer_init  <= (others => '0');\r
+        STATE            <= S_IDLE;\r
+      else\r
+        sequence_done_o  <= sequence_done_o_x;\r
+        i2c_byte         <= i2c_byte_x;\r
+        bit_ctr          <= bit_ctr_x;\r
+        i2c_ack_o        <= i2c_ack_o_x;\r
+        wait_timer_init  <= wait_timer_init_x;\r
+        STATE            <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_READ_BYTE_TRANSFER;  \r
+  \r
+  PROC_READ_BYTE: process(STATE,\r
+                          START_IN,\r
+                          wait_timer_done,\r
+                          bit_ctr\r
+                          )\r
+  begin \r
+    sda_o              <= '1';\r
+    scl_o              <= '1';\r
+    sequence_done_o_x  <= '0';\r
+    i2c_byte_x         <= i2c_byte;\r
+    bit_ctr_x          <= bit_ctr;       \r
+    i2c_ack_o_x        <= i2c_ack_o;\r
+    wait_timer_init_x  <= (others => '0');\r
+    \r
+    case STATE is\r
+      when S_IDLE =>\r
+        if (START_IN = '1') then\r
+          sda_o       <= '0';\r
+          scl_o       <= '0';\r
+          i2c_byte_x  <= (others => '0');\r
+          NEXT_STATE  <= S_INIT;\r
+        else\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+\r
+        -- INIT\r
+      when S_INIT =>\r
+        sda_o              <= '0';\r
+        scl_o              <= '0';\r
+        wait_timer_init_x  <= I2C_SPEED srl 1;\r
+        NEXT_STATE <= S_INIT_WAIT;\r
+\r
+      when S_INIT_WAIT =>\r
+        sda_o              <= '0';\r
+        scl_o              <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_INIT_WAIT;\r
+        else\r
+          NEXT_STATE <= S_READ_BYTE;\r
+        end if;\r
+        \r
+        -- I2C Read byte\r
+      when S_READ_BYTE =>\r
+        scl_o             <= '0';\r
+        bit_ctr_x         <= x"7";\r
+        wait_timer_init_x <= I2C_SPEED srl 2;\r
+        NEXT_STATE        <= S_UNSET_SCL1;\r
+\r
+      when S_UNSET_SCL1 =>\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_UNSET_SCL1;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE <= S_SET_SCL1;\r
+        end if;\r
+\r
+      when S_SET_SCL1 =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SCL1;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_GET_BIT;\r
+        end if;\r
+\r
+      when S_GET_BIT =>\r
+        i2c_byte_x(0)   <= SDA_IN;\r
+        NEXT_STATE      <= S_SET_SCL2;\r
+                \r
+      when S_SET_SCL2 =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SCL2;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_UNSET_SCL2;\r
+        end if;\r
+        \r
+      when S_UNSET_SCL2 =>\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_UNSET_SCL2;\r
+        else\r
+          NEXT_STATE <= S_NEXT_BIT;\r
+        end if;\r
+        \r
+      when S_NEXT_BIT =>\r
+        scl_o <= '0';\r
+        if (bit_ctr > 0) then\r
+          bit_ctr_x          <= bit_ctr - 1;\r
+          i2c_byte_x         <= i2c_byte sll 1;\r
+          wait_timer_init_x  <= I2C_SPEED srl 2;\r
+          NEXT_STATE         <= S_UNSET_SCL1;\r
+        else\r
+          wait_timer_init_x  <= I2C_SPEED srl 2;\r
+          NEXT_STATE         <= S_SET_ACK;\r
+        end if;\r
+\r
+        -- I2C Send ACK Sequence (doesn't work, so just send a clock)\r
+      when S_SET_ACK =>\r
+        --sda_o <= '0';\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_ACK;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE        <= S_ACK_SET_SCL;\r
+        end if;\r
+\r
+      when S_ACK_SET_SCL =>\r
+        -- sda_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_ACK_SET_SCL;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_ACK_UNSET_SCL;\r
+        end if; \r
+        \r
+      when S_ACK_UNSET_SCL =>\r
+        --sda_o <= '0';\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_ACK_UNSET_SCL;\r
+        else\r
+          sequence_done_o_x <= '1';\r
+          NEXT_STATE        <= S_IDLE;\r
+        end if;\r
+\r
+    end case;\r
+  end process PROC_READ_BYTE;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  SEQUENCE_DONE_OUT <= sequence_done_o;\r
+  BYTE_OUT          <= i2c_byte;\r
+  \r
+  -- I2c Outputs\r
+  SDA_OUT <= sda_o;\r
+  SCL_OUT <= scl_o;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/nx_i2c_sendbyte.vhd b/mupix/source/nx_i2c_sendbyte.vhd
new file mode 100644 (file)
index 0000000..88ab011
--- /dev/null
@@ -0,0 +1,243 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity nx_i2c_sendbyte is\r
+  generic (\r
+    I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
+    );\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    START_IN             : in  std_logic;\r
+    BYTE_IN              : in  std_logic_vector(7 downto 0);\r
+    SEQUENCE_DONE_OUT    : out std_logic;\r
+\r
+    -- I2C connections\r
+    SDA_OUT              : out std_logic;\r
+    SCL_OUT              : out std_logic;\r
+    SDA_IN               : in  std_logic;\r
+    ACK_OUT              : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_sendbyte is\r
+\r
+  -- Send Byte  \r
+  signal sda_o             : std_logic;\r
+  signal scl_o             : std_logic;\r
+  signal i2c_start         : std_logic;\r
+\r
+  signal sequence_done_o   : std_logic;\r
+  signal i2c_byte          : unsigned(7 downto 0);\r
+  signal bit_ctr           : unsigned(3 downto 0);\r
+  signal i2c_ack_o         : std_logic;\r
+  signal wait_timer_init   : unsigned(11 downto 0);\r
+\r
+  signal sequence_done_o_x : std_logic;\r
+  signal i2c_byte_x        : unsigned(7 downto 0);\r
+  signal bit_ctr_x         : unsigned(3 downto 0);\r
+  signal i2c_ack_o_x       : std_logic;\r
+  signal wait_timer_init_x : unsigned(11 downto 0);\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_INIT,\r
+                  S_INIT_WAIT,\r
+\r
+                  S_SEND_BYTE,\r
+                  S_SET_SDA,\r
+                  S_SET_SCL,\r
+                  S_UNSET_SCL,\r
+                  S_NEXT_BIT,\r
+\r
+                  S_GET_ACK,\r
+                  S_ACK_SET_SCL,\r
+                  S_STORE_ACK,\r
+                  S_ACK_UNSET_SCL\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+  \r
+  -- Wait Timer\r
+  signal wait_timer_done    : std_logic;\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 12\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+\r
+  PROC_SEND_BYTE_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sequence_done_o  <= '0';\r
+        bit_ctr          <= (others => '0');\r
+        i2c_ack_o        <= '0';\r
+        wait_timer_init  <= (others => '0');\r
+        STATE            <= S_IDLE;\r
+      else\r
+        sequence_done_o  <= sequence_done_o_x;\r
+        i2c_byte         <= i2c_byte_x;\r
+        bit_ctr          <= bit_ctr_x;\r
+        i2c_ack_o        <= i2c_ack_o_x;\r
+        wait_timer_init  <= wait_timer_init_x;\r
+        STATE            <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_SEND_BYTE_TRANSFER;  \r
+  \r
+  PROC_SEND_BYTE: process(STATE,\r
+                          START_IN,\r
+                          wait_timer_done,\r
+                          bit_ctr\r
+                          )\r
+  begin \r
+    sda_o              <= '1';\r
+    scl_o              <= '1';\r
+    sequence_done_o_x  <= '0';\r
+    i2c_byte_x         <= i2c_byte;\r
+    bit_ctr_x          <= bit_ctr;       \r
+    i2c_ack_o_x        <= i2c_ack_o;\r
+    wait_timer_init_x  <= (others => '0');\r
+    \r
+    case STATE is\r
+      when S_IDLE =>\r
+        if (START_IN = '1') then\r
+          sda_o       <= '0';\r
+          scl_o       <= '0';\r
+          i2c_byte_x  <= BYTE_IN;\r
+          NEXT_STATE  <= S_INIT;\r
+        else\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+\r
+        -- INIT\r
+      when S_INIT =>\r
+        sda_o              <= '0';\r
+        scl_o              <= '0';\r
+        wait_timer_init_x  <= I2C_SPEED srl 1;\r
+        NEXT_STATE <= S_INIT_WAIT;\r
+\r
+      when S_INIT_WAIT =>\r
+        sda_o              <= '0';\r
+        scl_o              <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_INIT_WAIT;\r
+        else\r
+          NEXT_STATE <= S_SEND_BYTE;\r
+        end if;\r
+        \r
+        -- I2C Send byte\r
+      when S_SEND_BYTE =>\r
+        sda_o             <= '0';\r
+        scl_o             <= '0';\r
+        bit_ctr_x         <= x"7";\r
+        wait_timer_init_x <= I2C_SPEED srl 2;\r
+        NEXT_STATE        <= S_SET_SDA;\r
+\r
+      when S_SET_SDA =>\r
+        sda_o <= i2c_byte(7);\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SDA;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE <= S_SET_SCL;\r
+        end if;\r
+\r
+      when S_SET_SCL =>\r
+        sda_o <= i2c_byte(7);\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_SET_SCL;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_UNSET_SCL;\r
+        end if;\r
+\r
+      when S_UNSET_SCL =>\r
+        sda_o <= i2c_byte(7);\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_UNSET_SCL;\r
+        else\r
+          NEXT_STATE <= S_NEXT_BIT;\r
+        end if;\r
+        \r
+      when S_NEXT_BIT =>\r
+        sda_o <= i2c_byte(7);\r
+        scl_o <= '0';\r
+        if (bit_ctr > 0) then\r
+          bit_ctr_x          <= bit_ctr - 1;\r
+          i2c_byte_x         <= i2c_byte sll 1;\r
+          wait_timer_init_x  <= I2C_SPEED srl 2;\r
+          NEXT_STATE         <= S_SET_SDA;\r
+        else\r
+          wait_timer_init_x  <= I2C_SPEED srl 2;\r
+          NEXT_STATE         <= S_GET_ACK;\r
+        end if;\r
+\r
+        -- I2C Check ACK Sequence\r
+      when S_GET_ACK =>\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_GET_ACK;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_ACK_SET_SCL;\r
+        end if;\r
+\r
+      when S_ACK_SET_SCL =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_ACK_SET_SCL;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_STORE_ACK;\r
+        end if; \r
+        \r
+      when S_STORE_ACK =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_STORE_ACK;\r
+        else\r
+          i2c_ack_o_x       <= not SDA_IN;\r
+          wait_timer_init_x <= I2C_SPEED srl 2;\r
+          NEXT_STATE        <= S_ACK_UNSET_SCL;\r
+        end if;\r
+        \r
+      when S_ACK_UNSET_SCL =>\r
+        scl_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_ACK_UNSET_SCL;\r
+        else\r
+          sequence_done_o_x <= '1';\r
+          NEXT_STATE        <= S_IDLE;\r
+        end if;\r
+\r
+    end case;\r
+  end process PROC_SEND_BYTE;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  SEQUENCE_DONE_OUT <= sequence_done_o;\r
+  ACK_OUT           <= i2c_ack_o;\r
+  \r
+  -- I2c Outputs\r
+  SDA_OUT <= sda_o;\r
+  SCL_OUT <= scl_o;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/nx_i2c_startstop.vhd b/mupix/source/nx_i2c_startstop.vhd
new file mode 100644 (file)
index 0000000..b5b4a49
--- /dev/null
@@ -0,0 +1,188 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_i2c_startstop is\r
+  generic (\r
+    I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
+    );\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    START_IN             : in  std_logic;  -- Start Sequence\r
+    SELECT_IN            : in  std_logic;  -- '1' -> Start, '0'-> Stop\r
+    SEQUENCE_DONE_OUT    : out std_logic;\r
+    \r
+    -- I2C connections\r
+    SDA_OUT              : out std_logic;\r
+    SCL_OUT              : out std_logic;\r
+    NREADY_OUT           : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_startstop is\r
+\r
+  -- I2C Bus  \r
+  signal sda_o             : std_logic;\r
+  signal scl_o             : std_logic;\r
+  signal sequence_done_o   : std_logic;\r
+  signal wait_timer_init   : unsigned(11 downto 0);\r
+\r
+  signal sequence_done_o_x : std_logic;\r
+  signal wait_timer_init_x : unsigned(11 downto 0);\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_START,\r
+                  S_WAIT_START_1,\r
+                  S_WAIT_START_2,\r
+                  S_WAIT_START_3,\r
+                  \r
+                  S_STOP,\r
+                  S_WAIT_STOP_1,\r
+                  S_WAIT_STOP_2,\r
+                  S_WAIT_STOP_3\r
+                  );\r
+  signal STATE, NEXT_STATE : STATES;\r
+\r
+  -- I2C Timer\r
+  signal wait_timer_done    : std_logic;\r
+\r
+begin\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 12\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+  PROC_START_STOP_TRANSFER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        sequence_done_o  <= '0';\r
+        wait_timer_init  <= (others => '0');\r
+        STATE <= S_IDLE;\r
+      else\r
+        sequence_done_o  <= sequence_done_o_x;\r
+        wait_timer_init  <= wait_timer_init_x;\r
+        STATE            <= NEXT_STATE;\r
+      end if;\r
+    end if;\r
+  end process PROC_START_STOP_TRANSFER;\r
+  \r
+  PROC_START_STOP: process(STATE,\r
+                           START_IN,\r
+                           SELECT_IN,\r
+                           wait_timer_done\r
+                           )\r
+  begin\r
+    sda_o             <= '1';\r
+    scl_o             <= '1';\r
+    wait_timer_init_x <= (others => '0');\r
+    sequence_done_o_x <= '0';\r
+    \r
+    case STATE is\r
+      when S_IDLE =>\r
+        if (START_IN = '1') then\r
+          if (SELECT_IN = '1') then\r
+            NEXT_STATE <= S_START;\r
+          else\r
+            sda_o      <= '0';\r
+            scl_o      <= '0';\r
+            NEXT_STATE <= S_STOP;\r
+          end if;\r
+        else\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+        \r
+        -- I2C START Sequence \r
+      when S_START =>\r
+        wait_timer_init_x <= I2C_SPEED srl 1;\r
+        NEXT_STATE <= S_WAIT_START_1;\r
+\r
+      when S_WAIT_START_1 =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_START_1;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE <= S_WAIT_START_2;\r
+        end if;\r
+\r
+      when S_WAIT_START_2 =>\r
+        sda_o         <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_START_2;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE <= S_WAIT_START_3;\r
+        end if;\r
+\r
+      when S_WAIT_START_3 =>\r
+        sda_o         <= '0';\r
+        scl_o         <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_START_3;\r
+        else\r
+          sequence_done_o_x <= '1';\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+\r
+        -- I2C STOP Sequence \r
+      when S_STOP =>\r
+        sda_o           <= '0';\r
+        scl_o           <= '0';\r
+        wait_timer_init_x <= I2C_SPEED srl 1;\r
+        NEXT_STATE <= S_WAIT_STOP_1;\r
+\r
+      when S_WAIT_STOP_1 =>\r
+        sda_o           <= '0';\r
+        scl_o           <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_STOP_1;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE <= S_WAIT_STOP_2;\r
+        end if;\r
+\r
+      when S_WAIT_STOP_2 =>\r
+        sda_o <= '0';\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_STOP_2;\r
+        else\r
+          wait_timer_init_x <= I2C_SPEED srl 1;\r
+          NEXT_STATE <= S_WAIT_STOP_3;\r
+        end if;\r
+\r
+      when S_WAIT_STOP_3 =>\r
+        if (wait_timer_done = '0') then\r
+          NEXT_STATE <= S_WAIT_STOP_3;\r
+        else\r
+          sequence_done_o_x <= '1';\r
+          NEXT_STATE <= S_IDLE;\r
+        end if;\r
+\r
+    end case;\r
+  end process PROC_START_STOP;\r
+\r
+\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  SEQUENCE_DONE_OUT <= sequence_done_o;\r
+  SDA_OUT           <= sda_o;\r
+  SCL_OUT           <= scl_o;\r
+  NREADY_OUT        <= '0';\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/nx_setup.vhd b/mupix/source/nx_setup.vhd
new file mode 100644 (file)
index 0000000..ad586cd
--- /dev/null
@@ -0,0 +1,479 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+\r
+entity nx_setup is\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+\r
+    I2C_COMMAND_OUT      : out std_logic_vector(31 downto 0);\r
+    I2C_COMMAND_BUSY_IN  : in  std_logic;\r
+    I2C_DATA_IN          : in  std_logic_vector(31 downto 0);\r
+    I2C_LOCK             : out std_logic;\r
+\r
+    SPI_COMMAND_OUT      : out std_logic_vector(31 downto 0);\r
+    SPI_COMMAND_BUSY_IN  : in  std_logic;\r
+    SPI_DATA_IN          : in  std_logic_vector(31 downto 0);\r
+    SPI_LOCK             : out std_logic;\r
+    \r
+    -- Slave bus         \r
+    SLV_READ_IN          : in  std_logic;\r
+    SLV_WRITE_IN         : in  std_logic;\r
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN          : in std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT          : out std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+    \r
+    -- Debug Line\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_setup is\r
+\r
+  -- Send I2C Command\r
+  type I2C_STATES is (I2C_IDLE,\r
+                      I2C_WAIT_BUSY_HIGH,\r
+                      I2C_WAIT_BUSY_LOW\r
+                      );\r
+\r
+  signal I2C_STATE : I2C_STATES;\r
+  \r
+  signal spi_command_o : std_logic_vector(31 downto 0);\r
+  signal i2c_lock_o              : std_logic;\r
+  signal i2c_command_o           : std_logic_vector(31 downto 0);\r
+  signal i2c_command             : std_logic_vector(31 downto 0);\r
+  signal i2c_command_busy        : std_logic;\r
+  signal i2c_command_done        : std_logic;\r
+  signal i2c_data                : std_logic_vector(31 downto 0);\r
+\r
+  -- Write I2C Registers\r
+  type W_STATES is (W_IDLE,\r
+                    W_NEXT_REGISTER,\r
+                    W_NOP,\r
+                    W_REGISTER,\r
+                    W_WAIT_DONE\r
+                    );\r
+\r
+  signal W_STATE, W_STATE_RETURN : W_STATES;\r
+\r
+  signal write_defaults_start    : std_logic;\r
+  signal write_i2c_command       : std_logic_vector(31 downto 0);\r
+  signal write_i2c_lock          : std_logic;        \r
+  signal w_register_ctr          : unsigned(7 downto 0);\r
+  \r
+  signal nx_ram_output_addr_i    : std_logic_vector(5 downto 0);\r
+  signal nx_ram_input_addr_i     : std_logic_vector(5 downto 0);\r
+  signal nx_ram_input_i          : std_logic_vector(7 downto 0);\r
+  signal nx_ram_write_i          : std_logic;\r
+\r
+  -- Read I2C Registers\r
+  type R_STATES is (R_IDLE,\r
+                    R_REGISTER,\r
+                    R_NEXT_REGISTER,\r
+                    R_WAIT_DONE\r
+                    );\r
+  \r
+  signal R_STATE, R_STATE_RETURN : R_STATES;\r
+\r
+  signal read_defaults_start     : std_logic;\r
+  signal read_i2c_command        : std_logic_vector(31 downto 0);\r
+  signal read_i2c_lock           : std_logic;        \r
+  signal r_register_ctr          : unsigned(7 downto 0);\r
+    \r
+  -- RAM Handler\r
+  signal nx_ram_input_addr       : std_logic_vector(5 downto 0);\r
+  signal nx_ram_input            : std_logic_vector(7 downto 0);\r
+  signal nx_ram_write            : std_logic;\r
+  \r
+  signal nx_ram_output_addr      : std_logic_vector(5 downto 0);\r
+  signal nx_ram_output           : std_logic_vector(7 downto 0);\r
+  \r
+  -- TRBNet Slave Bus\r
+  signal slv_data_out_o          : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o      : std_logic;\r
+  signal slv_unknown_addr_o      : std_logic;\r
+  signal slv_ack_o               : std_logic;\r
+\r
+  signal nx_ram_output_addr_s    : std_logic_vector(5 downto 0);\r
+  signal nx_ram_input_addr_s     : std_logic_vector(5 downto 0);\r
+  signal nx_ram_input_s          : std_logic_vector(7 downto 0);\r
+  signal nx_ram_write_s          : std_logic;\r
+  \r
+  signal register_mem_read_s     : std_logic;\r
+  signal register_mem_read       : std_logic;\r
+\r
+  type register_access_type_t is array(0 to 45) of std_logic;\r
+  constant register_access_type : register_access_type_t :=\r
+    ('1','1','1','1','1','1','1','1',   -- 7\r
+     '1','1','1','1','1','1','1','1',   -- 15\r
+     '1','1','1','1','1','1','1','1',   -- 23\r
+     '1','1','1','1','1','1','0','0',   -- 31\r
+     '1','1','0','0','0','0','1','1',   --39\r
+     '0','0','1','1','1','1'            -- 45\r
+     );\r
+\r
+\r
+  signal read_write_ding : std_logic;\r
+  \r
+begin\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- DEBUG\r
+  -----------------------------------------------------------------------------\r
+\r
+  DEBUG_OUT(0)            <= CLK_IN;\r
+  DEBUG_OUT(1)            <= read_defaults_start;\r
+  DEBUG_OUT(2)            <= write_defaults_start;\r
+  DEBUG_OUT(3)            <= i2c_lock_o;\r
+  DEBUG_OUT(4)            <= i2c_command_busy;\r
+  DEBUG_OUT(5)            <= i2c_command_done;\r
+  DEBUG_OUT(6)            <= I2C_COMMAND_BUSY_IN;\r
+  DEBUG_OUT(7)            <= register_mem_read_s;\r
+  DEBUG_OUT(8)            <= register_mem_read;\r
+  DEBUG_OUT(15 downto 9)  <= (others => '0');   \r
+  \r
+  -----------------------------------------------------------------------------\r
+    \r
+  -- Simple RAM to hold all nXyter I2C register settings\r
+\r
+  \r
+  ram_dp_1: ram_dp\r
+    generic map (\r
+      depth => 6,\r
+      width => 8\r
+      )\r
+    port map (\r
+      CLK   => CLK_IN,\r
+      wr1   => nx_ram_write,\r
+      a1    => nx_ram_input_addr,\r
+      dout1 => open,\r
+      din1  => nx_ram_input,\r
+      a2    => nx_ram_output_addr,\r
+      dout2 => nx_ram_output \r
+      );\r
+\r
+  nx_ram_output_addr <= nx_ram_output_addr_s or nx_ram_output_addr_i;\r
+  nx_ram_input_addr  <= nx_ram_input_addr_s or nx_ram_input_addr_i;\r
+  nx_ram_input       <= nx_ram_input_s or nx_ram_input_i;\r
+  nx_ram_write       <= nx_ram_write_s or nx_ram_write_i;\r
+  \r
+  ----------------------------------------------------------------------\r
+\r
+  i2c_lock_o    <= write_i2c_lock or read_i2c_lock;\r
+  i2c_command   <= write_i2c_command or read_i2c_command;\r
+\r
+  PROC_SEND_I2C_COMMAND: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        i2c_command_o    <= (others => '0');\r
+        i2c_command_busy <= '0';\r
+        i2c_command_done <= '0';\r
+        i2c_data         <= (others => '0');\r
+        I2C_STATE        <= I2C_IDLE;\r
+      else\r
+        i2c_command_o    <= (others => '0');\r
+        i2c_command_busy <= '0';\r
+        i2c_command_done <= '0';\r
+        \r
+        case I2C_STATE is\r
+\r
+          when I2C_IDLE =>\r
+            if (i2c_command(31) = '1') then\r
+              i2c_command_o    <= i2c_command;\r
+              i2c_command_busy <= '1';\r
+              I2C_STATE        <= I2C_WAIT_BUSY_HIGH;\r
+            else\r
+              I2C_STATE        <= I2C_IDLE;\r
+            end if;\r
+\r
+          when I2C_WAIT_BUSY_HIGH =>\r
+            if (I2C_COMMAND_BUSY_IN = '0') then\r
+              i2c_command_o    <= i2c_command_o;\r
+              i2c_command_busy <= '1';\r
+              I2C_STATE        <= I2C_WAIT_BUSY_HIGH;\r
+            else\r
+              i2c_command_busy <= '1';\r
+              I2C_STATE        <= I2C_WAIT_BUSY_LOW;\r
+            end if;\r
+\r
+          when I2C_WAIT_BUSY_LOW =>\r
+            if (I2C_COMMAND_BUSY_IN = '1') then\r
+              i2c_command_busy <= '1';\r
+              I2C_STATE        <= I2C_WAIT_BUSY_LOW;\r
+            else\r
+              i2c_data         <= I2C_DATA_IN;\r
+              i2c_command_done <= '1';\r
+              i2c_command_busy <= '1';\r
+              I2C_STATE        <= I2C_IDLE;\r
+            end if;\r
+        end case;\r
+        \r
+      end if;\r
+    end if;\r
+  end process PROC_SEND_I2C_COMMAND;\r
+\r
+PROC_WRITE_REGISTERS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        write_i2c_lock        <= '0';\r
+        write_i2c_command     <= (others => '0');\r
+        w_register_ctr        <= (others => '0');\r
+        \r
+        nx_ram_output_addr_i  <= (others => '0');\r
+\r
+        W_STATE_RETURN        <= W_IDLE;\r
+        W_STATE               <= W_IDLE;\r
+      else\r
+        write_i2c_command     <= (others => '0');\r
+        write_i2c_lock        <= '1';\r
+\r
+        nx_ram_output_addr_i  <= (others => '0');\r
+        read_write_ding <= '0';\r
+        \r
+        case W_STATE is\r
+\r
+          when W_IDLE =>\r
+            if (write_defaults_start = '1') then\r
+              w_register_ctr                  <= (others => '0');\r
+              W_STATE                         <= W_NEXT_REGISTER;\r
+            else\r
+              write_i2c_lock                  <= '0';\r
+              W_STATE                         <= W_IDLE;\r
+            end if;\r
+\r
+          when W_NEXT_REGISTER =>\r
+            if (w_register_ctr <= x"2d") then\r
+              nx_ram_output_addr_i            <= w_register_ctr(5 downto 0);\r
+              W_STATE                         <= W_NOP;\r
+            else\r
+              W_STATE                         <= W_IDLE;\r
+            end if;\r
+\r
+          when W_NOP =>\r
+            read_write_ding <= '1';\r
+            W_STATE                           <= W_REGISTER;\r
+            \r
+          when W_REGISTER =>\r
+            if (register_access_type(\r
+              to_integer(unsigned(w_register_ctr))) = '1') \r
+            then\r
+              write_i2c_command(31 downto 16) <= x"bf08";\r
+              write_i2c_command(15 downto 8)  <= w_register_ctr;\r
+              write_i2c_command(7 downto 0)   <= nx_ram_output;\r
+              W_STATE_RETURN                  <= W_NEXT_REGISTER;\r
+              W_STATE                         <= W_WAIT_DONE;\r
+            else\r
+              W_STATE                         <= W_NEXT_REGISTER;\r
+            end if;\r
+\r
+            w_register_ctr                    <= w_register_ctr + 1;\r
+            \r
+          when W_WAIT_DONE =>\r
+            if (i2c_command_done = '0') then\r
+              W_STATE                         <= W_WAIT_DONE;\r
+            else\r
+              W_STATE                         <= W_STATE_RETURN;\r
+            end if;\r
+\r
+        end case;\r
+      end if;\r
+    end if;\r
+  end process PROC_WRITE_REGISTERS;\r
+\r
+  PROC_READ_REGISTERS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        read_i2c_command    <= (others => '0');\r
+        read_i2c_lock       <= '0';\r
+        r_register_ctr      <= (others => '0');\r
+\r
+        nx_ram_input_addr_i <= (others => '0');\r
+        nx_ram_input_i      <= (others => '0');\r
+        nx_ram_write_i      <= '0';\r
+\r
+        R_STATE_RETURN      <= R_IDLE;\r
+        R_STATE             <= R_IDLE;\r
+      else\r
+        read_i2c_command    <= (others => '0');\r
+        read_i2c_lock       <= '1';\r
+\r
+        nx_ram_input_addr_i <= (others => '0');\r
+        nx_ram_input_i      <= (others => '0');\r
+        nx_ram_write_i      <= '0';\r
+\r
+        case R_STATE is\r
+          when R_IDLE =>\r
+            if (read_defaults_start = '1') then\r
+              r_register_ctr                  <= (others => '0');\r
+              R_STATE                         <= R_REGISTER;\r
+            else\r
+              read_i2c_lock                   <= '0';\r
+              R_STATE                         <= R_IDLE;\r
+            end if;\r
+\r
+          when R_REGISTER =>\r
+           if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+             read_i2c_command(31 downto 16)  <= x"ff08";\r
+             read_i2c_command(15 downto 8)   <= r_register_ctr;\r
+             read_i2c_command(7 downto 0)    <= (others => '0');\r
+             R_STATE_RETURN                  <= R_NEXT_REGISTER;\r
+             R_STATE                         <= R_WAIT_DONE;\r
+           else\r
+             R_STATE                         <= R_NEXT_REGISTER;\r
+           end if;\r
+            \r
+          when R_NEXT_REGISTER =>\r
+            if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+              nx_ram_input_i                  <= i2c_data(7 downto 0);\r
+            else\r
+              nx_ram_input_i                  <= x"be";\r
+            end if;\r
+            nx_ram_write_i                    <= '1';\r
+            nx_ram_input_addr_i               <= r_register_ctr(5 downto 0);\r
+            \r
+            if (r_register_ctr <= x"2d") then\r
+              r_register_ctr                  <= r_register_ctr + 1;\r
+              R_STATE                         <= R_REGISTER;\r
+            else\r
+              R_STATE                         <= R_IDLE;\r
+            end if;\r
+            \r
+          when R_WAIT_DONE =>\r
+            if (i2c_command_done = '0') then\r
+              R_STATE                         <= R_WAIT_DONE;\r
+            else\r
+              R_STATE                         <= R_STATE_RETURN;\r
+            end if;\r
+\r
+        end case;\r
+     end if;\r
+    end if;\r
+  end process PROC_READ_REGISTERS;\r
+        \r
+  PROC_SLAVE_BUS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o        <= (others => '0');\r
+        slv_no_more_data_o    <= '0';\r
+        slv_unknown_addr_o    <= '0';\r
+        slv_ack_o             <= '0';\r
+        write_defaults_start  <= '0';\r
+        read_defaults_start   <= '0';\r
+        register_mem_read_s   <= '0';\r
+        register_mem_read     <= '0';\r
+        nx_ram_output_addr_s  <= (others => '0');        \r
+        nx_ram_input_addr_s   <= (others => '0');\r
+        nx_ram_input_s        <= (others => '0');\r
+        nx_ram_write_s        <= '0';\r
+      else                    \r
+        slv_data_out_o        <= (others => '0');\r
+        slv_unknown_addr_o    <= '0';\r
+        slv_no_more_data_o    <= '0';\r
+        write_defaults_start  <= '0';\r
+        read_defaults_start   <= '0';\r
+        register_mem_read_s   <= '0';\r
+        register_mem_read     <= register_mem_read_s;\r
+        nx_ram_output_addr_s  <= (others => '0');\r
+        nx_ram_input_addr_s   <= (others => '0');\r
+        nx_ram_input_s        <= (others => '0');\r
+        nx_ram_write_s        <= '0';\r
+\r
+        if (register_mem_read = '1') then\r
+          slv_data_out_o(7 downto 0)  <= nx_ram_output;\r
+          slv_data_out_o(31 downto 8) <= (others => '0');\r
+          slv_ack_o                   <= '1';\r
+\r
+        \r
+        elsif (SLV_WRITE_IN  = '1') then\r
+          if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
+            if (i2c_lock_o = '1') then\r
+              slv_no_more_data_o      <= '1';\r
+              slv_ack_o               <= '0';\r
+            else\r
+              if (register_access_type(\r
+                to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))) = '1')\r
+              then\r
+                nx_ram_input_addr_s   <= SLV_ADDR_IN(5 downto 0);\r
+                nx_ram_input_s        <= SLV_DATA_IN(7 downto 0);\r
+                nx_ram_write_s        <= '1';\r
+              end if;\r
+              slv_ack_o               <= '1';\r
+            end if;\r
+\r
+          else\r
+            case SLV_ADDR_IN is\r
+              when x"0040" =>\r
+                write_defaults_start  <= '1';\r
+                slv_ack_o             <= '1';\r
+                \r
+              when x"0041" =>\r
+                read_defaults_start   <= '1';\r
+                slv_ack_o             <= '1';\r
+                                    \r
+              when others =>          \r
+                slv_unknown_addr_o    <= '1';\r
+                slv_ack_o             <= '0';    \r
+                                    \r
+            end case;                     \r
+          end if;\r
+\r
+        elsif (SLV_READ_IN = '1') then\r
+          if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
+            nx_ram_output_addr_s      <= SLV_ADDR_IN(5 downto 0);\r
+            register_mem_read_s       <= '1';\r
+            slv_ack_o                 <= '0';\r
+          else\r
+            case SLV_ADDR_IN is       \r
+              when x"0040" =>         \r
+                slv_data_out_o        <= x"deadbeef";\r
+                slv_ack_o             <= '1';\r
+                                    \r
+              when x"0041" =>         \r
+                slv_data_out_o        <= i2c_data;\r
+                slv_ack_o             <= '1';\r
+                                    \r
+              when others =>          \r
+                slv_unknown_addr_o    <= '1';\r
+                slv_ack_o             <= '0';\r
+                                    \r
+            end case;                 \r
+          end if;\r
+\r
+        else                        \r
+          slv_ack_o                   <= '0';\r
+        end if;\r
+\r
+      end if;\r
+    end if;           \r
+  end process PROC_SLAVE_BUS;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+  \r
+  I2C_COMMAND_OUT  <= i2c_command_o;\r
+  I2C_LOCK         <= i2c_lock_o;\r
+  \r
+  SPI_COMMAND_OUT  <= spi_command_o;\r
+  spi_command_o    <= (others => '0');\r
+\r
+  -- Slave Bus\r
+  SLV_DATA_OUT         <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT          <= slv_ack_o; \r
+\r
+end Behavioral;\r
diff --git a/mupix/source/nx_timer.vhd b/mupix/source/nx_timer.vhd
new file mode 100644 (file)
index 0000000..520818b
--- /dev/null
@@ -0,0 +1,79 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+entity nx_timer is\r
+  generic (\r
+    CTR_WIDTH : integer := 12\r
+    );\r
+  port(\r
+    CLK_IN               : in    std_logic;\r
+    RESET_IN             : in    std_logic;\r
+\r
+    TIMER_START_IN       : in unsigned(CTR_WIDTH - 1 downto 0);\r
+    TIMER_DONE_OUT       : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_timer is\r
+\r
+  -- Timer\r
+  signal timer_ctr       : unsigned(CTR_WIDTH - 1 downto 0);\r
+  signal timer_done_o    : std_logic;\r
+\r
+  type STATES is (S_IDLE,\r
+                  S_COUNT,\r
+                  S_DONE\r
+                  );\r
+  signal STATE : STATES;\r
+\r
+begin\r
+  \r
+  PROC_TIMER: process(CLK_IN)\r
+  begin \r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        timer_ctr     <= (others => '0');\r
+        timer_done_o  <= '0';\r
+        STATE         <= S_IDLE;\r
+      else\r
+        timer_done_o  <= '0';\r
+        \r
+        if (TIMER_START_IN > 0) then\r
+          timer_ctr <= TIMER_START_IN;\r
+          STATE     <= S_COUNT;\r
+        else\r
+          case STATE is\r
+            when S_IDLE =>\r
+              if (TIMER_START_IN = 0) then\r
+                STATE      <= S_IDLE;\r
+              else\r
+                timer_ctr  <= TIMER_START_IN;\r
+                STATE      <= S_COUNT;\r
+              end if;\r
+        \r
+            when S_COUNT =>\r
+              if (timer_ctr > 0) then\r
+                timer_ctr  <= timer_ctr - 1;\r
+                STATE      <= S_COUNT;\r
+              else\r
+                STATE      <= S_DONE;\r
+              end if;\r
+        \r
+            when S_DONE =>\r
+              timer_done_o <= '1';\r
+              STATE        <= S_IDLE;\r
+\r
+          end case;\r
+        end if;\r
+      end if;\r
+    end if;\r
+  end process PROC_TIMER;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  TIMER_DONE_OUT <= timer_done_o;\r
+\r
+end Behavioral;\r
diff --git a/mupix/source/nx_timestamp_sim.vhd b/mupix/source/nx_timestamp_sim.vhd
new file mode 100644 (file)
index 0000000..fb94d01
--- /dev/null
@@ -0,0 +1,101 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nxyter_timestamp_sim is\r
+  port(\r
+    CLK_IN               : in  std_logic;  -- Clock 128MHz\r
+    RESET_IN             : in  std_logic;\r
+    \r
+    TIMESTAMP_OUT        : out std_logic_vector(7 downto 0);\r
+    CLK128_OUT           : out std_logic\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nxyter_timestamp_sim is\r
+  \r
+  signal timestamp_n     : std_logic_vector(7 downto 0);\r
+  signal timestamp_g     : std_logic_vector(7 downto 0);\r
+  signal counter         : unsigned(1 downto 0);\r
+  signal counter2        : unsigned(3 downto 0);\r
+  signal counter3        : unsigned(1 downto 0);\r
+\r
+begin\r
+\r
+  PROC_NX_TIMESTAMP: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        timestamp_n <= (others => '0');\r
+        counter     <= (others => '0');\r
+        counter2    <= (others => '0');\r
+        counter3    <= (others => '0');\r
+\r
+      else\r
+\r
+        if (counter3 /= 0) then\r
+          case counter is\r
+            when "11" => timestamp_n <= x"06";\r
+                         counter3 <= counter3 + 1;\r
+\r
+            when "10" => timestamp_n <= x"7f";\r
+\r
+            when "01" => timestamp_n <= x"7f";\r
+\r
+            when "00" => timestamp_n <= x"7f";\r
+          end case;\r
+\r
+        else\r
+          case counter is\r
+            when "11" =>\r
+              timestamp_n(7)           <= '0';\r
+              timestamp_n(6 downto 4)  <= (others => '0');\r
+              timestamp_n(3 downto 0)  <= counter2;\r
+              counter3 <= counter3 + 1;\r
+              \r
+            when "10" =>\r
+              timestamp_n(7)           <= '0';\r
+              timestamp_n(6 downto 4)  <= (others => '0');\r
+              timestamp_n(3 downto 0)  <= counter2;\r
+            \r
+            when "01" =>\r
+              timestamp_n(7)           <= '0';\r
+              timestamp_n(6 downto 4)  <= (others => '0');\r
+              timestamp_n(3 downto 0)  <= counter2;\r
+\r
+            when "00" =>\r
+              timestamp_n(7)           <= '0';\r
+              timestamp_n(6 downto 4)  <= (others => '0');\r
+              timestamp_n(3 downto 0)  <= counter2;\r
+\r
+          end case;\r
+          counter2 <= counter2 + 1;\r
+        end if;\r
+\r
+        counter  <= counter + 1;\r
+      end if;\r
+    end if;           \r
+  end process PROC_NX_TIMESTAMP;\r
+\r
+--   Gray_Encoder_1: Gray_Encoder\r
+--     generic map (\r
+--       WIDTH => 8\r
+--       )\r
+--     port map (\r
+--       CLK_IN    => CLK_IN,\r
+--       RESET_IN  => RESET_IN,\r
+--       BINARY_IN => timestamp_n,\r
+--       GRAY_OUT  => timestamp_g \r
+--       );\r
+-- \r
+--  timestamp_g <= timestamp_n;\r
+  \r
+  \r
+-- Output Signals\r
+  TIMESTAMP_OUT <= timestamp_n;\r
+  CLK128_OUT    <= CLK_IN;\r
+  \r
+end Behavioral;\r
diff --git a/mupix/source/nx_trigger_generator.vhd b/mupix/source/nx_trigger_generator.vhd
new file mode 100644 (file)
index 0000000..d556817
--- /dev/null
@@ -0,0 +1,246 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_trigger_generator is\r
+  port (\r
+    CLK_IN               : in    std_logic;\r
+    RESET_IN             : in    std_logic;\r
+\r
+    TRIGGER_OUT          : out   std_logic;\r
+    TS_RESET_OUT         : out   std_logic;\r
+    TESTPULSE_OUT        : out   std_logic;\r
+    \r
+    -- Slave bus         \r
+    SLV_READ_IN          : in    std_logic;\r
+    SLV_WRITE_IN         : in    std_logic;\r
+    SLV_DATA_OUT         : out   std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in    std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN          : in    std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT          : out   std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out   std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out   std_logic;\r
+    \r
+    -- Debug Line\r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_trigger_generator is\r
+\r
+  signal start_cycle         : std_logic;\r
+  signal trigger_cycle_ctr   : unsigned(7 downto 0);\r
+  signal wait_timer_init     : unsigned(15 downto 0);\r
+  signal wait_timer_done     : std_logic;\r
+  signal trigger_o           : std_logic;\r
+  signal ts_reset_o          : std_logic;\r
+  signal testpulse_o         : std_logic;\r
+  \r
+  type STATES is (S_IDLE,\r
+                  S_NEXT_CYCLE,\r
+                  S_SET_TESTPULSE,\r
+                  S_WAIT_TRIGGER_END\r
+                  );\r
+  signal STATE : STATES;\r
+  \r
+  -- TRBNet Slave Bus            \r
+  signal slv_data_out_o          : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o      : std_logic;\r
+  signal slv_unknown_addr_o      : std_logic;\r
+  signal slv_ack_o               : std_logic;\r
+\r
+  signal reg_trigger_period      : unsigned(15 downto 0);\r
+  signal reg_testpulse_length    : unsigned(15 downto 0);\r
+  signal reg_trigger_num_cycles  : unsigned(7 downto 0);      \r
+  signal reg_reset_on            : std_logic;\r
+  \r
+begin\r
+\r
+  -- Debug Line\r
+  DEBUG_OUT(0)           <= CLK_IN;\r
+  DEBUG_OUT(1)           <= trigger_o;\r
+  DEBUG_OUT(2)           <= start_cycle;\r
+  DEBUG_OUT(3)           <= wait_timer_done;\r
+  DEBUG_OUT(4)           <= ts_reset_o;\r
+  DEBUG_OUT(5)           <= testpulse_o;\r
+  DEBUG_OUT(7 downto 6)  <= (others => '0');\r
+  DEBUG_OUT(15 downto 8) <= trigger_cycle_ctr;\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 16\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Gernerate Trigger\r
+  -----------------------------------------------------------------------------\r
\r
+  PROC_TRIGGER_OUT: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        trigger_o         <= '0';\r
+        testpulse_o       <= '0';\r
+        ts_reset_o        <= '0';\r
+        wait_timer_init   <= (others => '0');\r
+        trigger_cycle_ctr <= (others => '0');\r
+        STATE             <= S_IDLE;\r
+      else\r
+        trigger_o         <= '0';\r
+        testpulse_o       <= '0';\r
+        ts_reset_o        <= '0';\r
+        wait_timer_init   <= (others => '0');\r
+        trigger_cycle_ctr <= trigger_cycle_ctr;\r
+        \r
+        case STATE is\r
+          when  S_IDLE =>\r
+            if (start_cycle = '1') then\r
+              trigger_cycle_ctr <= reg_trigger_num_cycles;\r
+              if (reg_reset_on = '1') then\r
+                ts_reset_o      <= '1';\r
+                wait_timer_init <= reg_trigger_period;\r
+                STATE           <= S_WAIT_TRIGGER_END;\r
+              else\r
+                STATE           <= S_NEXT_CYCLE;\r
+              end if;\r
+            else\r
+              STATE             <= S_IDLE;\r
+            end if;\r
+\r
+          when S_NEXT_CYCLE =>\r
+            if (trigger_cycle_ctr > 0) then\r
+              trigger_o         <= '1';\r
+              trigger_cycle_ctr <= trigger_cycle_ctr - 1;\r
+              if (reg_testpulse_length > 0) then\r
+                wait_timer_init <= reg_testpulse_length;\r
+                STATE           <= S_SET_TESTPULSE;\r
+              else\r
+                wait_timer_init <= reg_trigger_period;\r
+                STATE           <= S_WAIT_TRIGGER_END;\r
+              end if;\r
+            else\r
+              STATE             <= S_IDLE;\r
+            end if;\r
+\r
+          when S_SET_TESTPULSE =>\r
+            testpulse_o         <= '1';\r
+            if (wait_timer_done = '0') then\r
+              STATE             <= S_SET_TESTPULSE;\r
+            else\r
+              wait_timer_init   <= reg_trigger_period - reg_testpulse_length;\r
+              STATE             <= S_WAIT_TRIGGER_END;\r
+            end if;\r
+            \r
+          when S_WAIT_TRIGGER_END =>\r
+            if (wait_timer_done = '0') then\r
+              STATE             <= S_WAIT_TRIGGER_END;\r
+            else\r
+              STATE             <= S_NEXT_CYCLE;\r
+            end if;\r
+\r
+        end case;\r
+      end if;\r
+    end if;\r
+  end process PROC_TRIGGER_OUT;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+  \r
+  PROC_SLAVE_BUS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        reg_trigger_period     <= x"00ff";\r
+        reg_trigger_num_cycles <= x"01";\r
+        reg_testpulse_length   <= (others => '0');\r
+        reg_reset_on           <= '0';\r
+        slv_data_out_o         <= (others => '0');\r
+        slv_no_more_data_o     <= '0';\r
+        slv_unknown_addr_o     <= '0';\r
+        start_cycle            <= '0';\r
+        slv_ack_o              <= '0';\r
+      else\r
+        slv_unknown_addr_o <= '0';\r
+        slv_no_more_data_o <= '0';\r
+        slv_data_out_o     <= (others => '0');\r
+        start_cycle        <= '0';\r
+\r
+\r
+        if (SLV_WRITE_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0000" =>\r
+              start_cycle              <= '1';\r
+              slv_ack_o                <= '1';\r
+            when x"0001" =>\r
+              reg_trigger_period       <= unsigned(SLV_DATA_IN(15 downto 0));\r
+              slv_ack_o                <= '1';\r
+            when x"0002" =>\r
+              reg_trigger_num_cycles   <= unsigned(SLV_DATA_IN(7 downto 0));\r
+              slv_ack_o                <= '1';\r
+            when x"0003" =>\r
+              reg_testpulse_length     <= unsigned(SLV_DATA_IN(15 downto 0));\r
+              slv_ack_o                <= '1';\r
+            when x"0004" =>\r
+              reg_reset_on             <=  SLV_DATA_IN(0);\r
+              slv_ack_o                <= '1';\r
+            when others =>\r
+              slv_unknown_addr_o       <= '1';\r
+              slv_ack_o                <= '0';\r
+          end case;\r
+\r
+        elsif (SLV_READ_IN = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0001" =>\r
+              slv_data_out_o(15 downto 0) <=\r
+                std_logic_vector(reg_trigger_period);\r
+              slv_ack_o                   <= '1';\r
+            when x"0002" =>\r
+              slv_data_out_o(7 downto 0)  <=\r
+                std_logic_vector(reg_trigger_num_cycles);\r
+              slv_ack_o                   <= '1';\r
+            when x"0003" =>\r
+              slv_data_out_o(15 downto 0) <=\r
+                std_logic_vector(reg_testpulse_length);\r
+              slv_ack_o                   <= '1';\r
+            when x"0004" =>\r
+              slv_data_out_o(0)           <= reg_reset_on;\r
+              slv_ack_o                   <= '1';\r
+            when others =>\r
+              slv_unknown_addr_o          <= '1';\r
+              slv_ack_o                   <= '0';\r
+          end case;\r
+\r
+        else\r
+          slv_ack_o            <= '0';\r
+        end if;\r
+      end if;\r
+    end if;           \r
+  end process PROC_SLAVE_BUS;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+  \r
+  -- Trigger Output\r
+  TRIGGER_OUT          <= trigger_o;\r
+  TS_RESET_OUT         <= ts_reset_o;\r
+  TESTPULSE_OUT        <= testpulse_o;\r
+\r
+  -- Slave Bus\r
+  SLV_DATA_OUT         <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT          <= slv_ack_o;    \r
+\r
+end Behavioral;\r
diff --git a/mupix/source/nx_trigger_handler.vhd b/mupix/source/nx_trigger_handler.vhd
new file mode 100644 (file)
index 0000000..9cd632e
--- /dev/null
@@ -0,0 +1,346 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_trigger_handler is\r
+  port (\r
+    CLK_IN                     : in  std_logic;\r
+    RESET_IN                   : in  std_logic;\r
+\r
+    NXYTER_OFFLINE_IN          : in  std_logic;\r
+    \r
+    --LVL1 trigger\r
+    LVL1_TRG_DATA_VALID_IN     : in std_logic;  -- timing trigger valid, later\r
+    LVL1_VALID_TIMING_TRG_IN   : in std_logic;  -- timing trigger synced\r
+    LVL1_VALID_NOTIMING_TRG_IN : in std_logic;  -- timing trigger raw\r
+    LVL1_INVALID_TRG_IN        : in std_logic;  -- ???\r
+\r
+    LVL1_TRG_TYPE_IN           : in std_logic_vector(3 downto 0);\r
+    LVL1_TRG_NUMBER_IN         : in std_logic_vector(15 downto 0);\r
+    LVL1_TRG_CODE_IN           : in std_logic_vector(7 downto 0);\r
+    LVL1_TRG_INFORMATION_IN    : in std_logic_vector(23 downto 0);\r
+    LVL1_INT_TRG_NUMBER_IN     : in std_logic_vector(15 downto 0);\r
+\r
+    FEE_TRG_RELEASE_OUT        : out std_logic;\r
+    FEE_TRG_STATUSBITS_OUT     : out std_logic_vector(31 downto 0);\r
+\r
+    -- Internal FPGA Trigger\r
+    INTERNAL_TRIGGER_IN        : in  std_logic;\r
+    \r
+    -- Trigger FeedBack\r
+    TRIGGER_VALIDATE_BUSY_IN   : in  std_logic;\r
+    LVL2_TRIGGER_BUSY_IN       : in  std_logic;\r
+    \r
+    -- OUT\r
+    VALIDATE_TRIGGER_OUT       : out std_logic;\r
+    TIMESTAMP_HOLD_OUT         : out std_logic;\r
+    LVL2_TRIGGER_OUT           : out std_logic;\r
+    EVENT_BUFFER_CLEAR_OUT     : out std_logic;\r
+    FAST_CLEAR_OUT             : out std_logic;\r
+    TRIGGER_BUSY_OUT           : out std_logic;\r
+    \r
+    -- Slave bus               \r
+    SLV_READ_IN                : in  std_logic;\r
+    SLV_WRITE_IN               : in  std_logic;\r
+    SLV_DATA_OUT               : out std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN                : in  std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN                : in  std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT                : out std_logic;\r
+    SLV_NO_MORE_DATA_OUT       : out std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT       : out std_logic;\r
+                               \r
+    -- Debug Line              \r
+    DEBUG_OUT                  : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nx_trigger_handler is\r
+\r
+  -- Trigger Handler\r
+  signal validate_trigger_o       : std_logic;\r
+  signal timestamp_hold           : std_logic;\r
+  signal lvl2_trigger_o           : std_logic;\r
+  signal evt_buffer_clear_o       : std_logic;\r
+  signal fast_clear_o             : std_logic;\r
+  signal trigger_busy_o           : std_logic;\r
+  signal fee_trg_release_o        : std_logic;\r
+  signal fee_trg_statusbits_o     : std_logic_vector(31 downto 0);\r
+\r
+  type STATES is (S_IDLE,\r
+                  S_CTS_TRIGGER,\r
+                  S_WAIT_TRG_DATA_VALID,\r
+                  S_WAIT_LVL2_TRIGGER_DONE,\r
+                  S_FEE_TRIGGER_RELEASE,\r
+                  S_WAIT_FEE_TRIGGER_RELEASE_ACK,\r
+                  S_INTERNAL_TRIGGER,\r
+                  S_WAIT_TRIGGER_VALIDATE_ACK,\r
+                  S_WAIT_TRIGGER_VALIDATE_DONE\r
+                  );\r
+  signal STATE : STATES;\r
+\r
+  -- Timestamp Hold Handler\r
+  type TS_STATES is (TS_IDLE,\r
+                  TS_WAIT_TIMER_DONE\r
+                  );\r
+  signal TS_STATE : TS_STATES;\r
+\r
+  signal timestamp_hold_o         : std_logic;\r
+  signal wait_timer_init          : unsigned(7 downto 0);\r
+  signal wait_timer_done          : std_logic;\r
+                                  \r
+  -- TRBNet Slave Bus                \r
+  signal slv_data_out_o           : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o       : std_logic;\r
+  signal slv_unknown_addr_o       : std_logic;\r
+  signal slv_ack_o                : std_logic;\r
+\r
+  signal reg_timestamp_hold_delay : unsigned(7 downto 0);\r
+  \r
+begin\r
+\r
+  -- Debug Line\r
+  DEBUG_OUT(0)            <= CLK_IN;\r
+  DEBUG_OUT(1)            <= LVL1_VALID_TIMING_TRG_IN;\r
+  DEBUG_OUT(2)            <= LVL1_TRG_DATA_VALID_IN;\r
+  DEBUG_OUT(3)            <= INTERNAL_TRIGGER_IN;\r
+  DEBUG_OUT(4)            <= TRIGGER_VALIDATE_BUSY_IN;\r
+  DEBUG_OUT(5)            <= LVL2_TRIGGER_BUSY_IN;\r
+\r
+  DEBUG_OUT(6)            <= validate_trigger_o;\r
+  DEBUG_OUT(7)            <= timestamp_hold_o;\r
+  DEBUG_OUT(8)            <= lvl2_trigger_o;\r
+  DEBUG_OUT(9)            <= evt_buffer_clear_o;\r
+  DEBUG_OUT(10)           <= fee_trg_release_o;\r
+  DEBUG_OUT(11)           <= trigger_busy_o;\r
+  \r
+  DEBUG_OUT(15 downto 12) <= (others => '0');\r
+\r
+  -- Timer\r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 8\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Trigger Handler\r
+  -----------------------------------------------------------------------------\r
+\r
+  PROC_TRIGGER_HANDLER: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1') then\r
+        validate_trigger_o   <= '0';\r
+        timestamp_hold       <= '0';\r
+        lvl2_trigger_o       <= '0';\r
+        fee_trg_release_o    <= '0';\r
+        fee_trg_statusbits_o <= (others => '0');\r
+        evt_buffer_clear_o   <= '0';\r
+        trigger_busy_o       <= '0';\r
+        STATE                <= S_IDLE;\r
+      else\r
+        validate_trigger_o         <= '0';\r
+        timestamp_hold       <= '0';\r
+        lvl2_trigger_o       <= '0';\r
+        fee_trg_release_o    <= '0';\r
+        fee_trg_statusbits_o <= (others => '0');\r
+        evt_buffer_clear_o   <= '0';\r
+        trigger_busy_o       <= '1';\r
+        \r
+        case STATE is\r
+          when  S_IDLE =>\r
+\r
+            if (LVL1_VALID_NOTIMING_TRG_IN = '1') then\r
+              STATE              <= S_WAIT_TRG_DATA_VALID;\r
+\r
+            elsif (LVL1_INVALID_TRG_IN = '1') then\r
+              fee_trg_release_o      <= '1';\r
+              STATE                  <= S_IDLE;\r
+              \r
+            elsif (LVL1_VALID_TIMING_TRG_IN = '1') then\r
+              if (NXYTER_OFFLINE_IN = '1') then\r
+                STATE              <= S_WAIT_TRG_DATA_VALID;\r
+              else\r
+                STATE              <= S_CTS_TRIGGER;\r
+              end if;\r
+            elsif (INTERNAL_TRIGGER_IN = '1') then\r
+              STATE                <= S_INTERNAL_TRIGGER;\r
+            else\r
+              trigger_busy_o       <= '0';\r
+              STATE                <= S_IDLE;\r
+            end if;     \r
+\r
+            -- CTS Trigger Handler\r
+          when S_CTS_TRIGGER =>\r
+            evt_buffer_clear_o     <= '1';\r
+            validate_trigger_o     <= '1';\r
+            timestamp_hold         <= '1';\r
+            lvl2_trigger_o         <= '1';\r
+            STATE                  <= S_WAIT_TRG_DATA_VALID;\r
+\r
+          when S_WAIT_TRG_DATA_VALID =>\r
+            if (LVL1_TRG_DATA_VALID_IN = '0') then\r
+              STATE                <= S_WAIT_TRG_DATA_VALID;\r
+            else\r
+              STATE                <= S_WAIT_LVL2_TRIGGER_DONE;\r
+            end if;\r
+\r
+          when S_WAIT_LVL2_TRIGGER_DONE =>\r
+            if (LVL2_TRIGGER_BUSY_IN = '1') then\r
+              STATE                <= S_WAIT_LVL2_TRIGGER_DONE;\r
+            else\r
+              STATE                <= S_FEE_TRIGGER_RELEASE;\r
+            end if;\r
+\r
+          when S_FEE_TRIGGER_RELEASE =>\r
+            fee_trg_release_o      <= '1';\r
+            STATE                  <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
+              \r
+          when S_WAIT_FEE_TRIGGER_RELEASE_ACK =>\r
+            if (LVL1_TRG_DATA_VALID_IN = '1') then\r
+              STATE                <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
+            else\r
+              STATE                <= S_IDLE;\r
+            end if;\r
+            \r
+            -- Internal Trigger Handler\r
+          when S_INTERNAL_TRIGGER =>\r
+            validate_trigger_o     <= '1';\r
+            timestamp_hold         <= '1';\r
+            evt_buffer_clear_o     <= '1';\r
+            STATE                  <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
+\r
+          when S_WAIT_TRIGGER_VALIDATE_ACK =>\r
+            if (TRIGGER_VALIDATE_BUSY_IN = '0') then\r
+              STATE                <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
+            else\r
+              STATE                <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
+            end if;\r
+            \r
+          when S_WAIT_TRIGGER_VALIDATE_DONE =>\r
+            if (TRIGGER_VALIDATE_BUSY_IN = '1') then\r
+              STATE                <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
+            else\r
+              STATE                <= S_IDLE;\r
+            end if;\r
+            \r
+        end case;\r
+      end if;\r
+    end if;\r
+  end process PROC_TRIGGER_HANDLER;\r
+\r
+  PROC_SEND_TIMSTAMP_HOLD: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then\r
+        wait_timer_init   <= (others => '0');\r
+        timestamp_hold_o  <= '0';\r
+        TS_STATE          <= TS_IDLE;\r
+      else\r
+        wait_timer_init   <= (others => '0');\r
+        timestamp_hold_o  <= '0';\r
+\r
+        case TS_STATE is\r
+\r
+          when TS_IDLE =>\r
+            if (timestamp_hold = '0') then\r
+              TS_STATE          <= TS_IDLE;\r
+            else\r
+              wait_timer_init   <= reg_timestamp_hold_delay;\r
+              TS_STATE          <= TS_WAIT_TIMER_DONE;\r
+            end if;\r
+\r
+          when TS_WAIT_TIMER_DONE =>\r
+            if (wait_timer_done = '0') then\r
+              TS_STATE          <= TS_WAIT_TIMER_DONE;\r
+            else\r
+              timestamp_hold_o  <= '1';\r
+              TS_STATE          <= TS_IDLE;\r
+            end if;\r
+\r
+        end case;\r
+            \r
+      end if;\r
+    end if;\r
+  end process PROC_SEND_TIMSTAMP_HOLD;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- TRBNet Slave Bus\r
+  -----------------------------------------------------------------------------\r
+  \r
+  PROC_SLAVE_BUS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o           <= (others => '0');\r
+        slv_no_more_data_o       <= '0';\r
+        slv_unknown_addr_o       <= '0';\r
+        slv_ack_o                <= '0';\r
+        reg_timestamp_hold_delay <= x"01";\r
+      else\r
+        slv_unknown_addr_o <= '0';\r
+        slv_no_more_data_o <= '0';\r
+        slv_data_out_o     <= (others => '0');\r
+        slv_ack_o          <= '0';\r
+        \r
+        if (SLV_WRITE_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0000" =>\r
+              if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then\r
+                reg_timestamp_hold_delay <= unsigned(SLV_DATA_IN(7 downto 0));\r
+              end if;\r
+              slv_ack_o                   <= '1';\r
+              \r
+            when others =>\r
+              slv_unknown_addr_o          <= '1';\r
+\r
+          end case;\r
+\r
+        elsif (SLV_READ_IN = '1') then\r
+          case SLV_ADDR_IN is\r
+\r
+            when x"0000" =>\r
+              slv_data_out_o(7 downto 0)   <=\r
+                std_logic_vector(reg_timestamp_hold_delay);\r
+              slv_data_out_o(31 downto 8)  <= (others => '0');\r
+              slv_ack_o                    <= '1';\r
+\r
+            when others =>\r
+              slv_unknown_addr_o           <= '1';\r
+\r
+          end case;\r
+\r
+        end if;\r
+      end if;\r
+    end if;           \r
+  end process PROC_SLAVE_BUS;\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- Output Signals\r
+  -----------------------------------------------------------------------------\r
+\r
+  -- Trigger Output\r
+  VALIDATE_TRIGGER_OUT      <= validate_trigger_o;\r
+  TIMESTAMP_HOLD_OUT        <= timestamp_hold_o;\r
+  LVL2_TRIGGER_OUT          <= lvl2_trigger_o;\r
+  EVENT_BUFFER_CLEAR_OUT    <= evt_buffer_clear_o;\r
+  FAST_CLEAR_OUT            <= fast_clear_o;\r
+  TRIGGER_BUSY_OUT          <= trigger_busy_o;\r
+  FEE_TRG_RELEASE_OUT       <= fee_trg_release_o;\r
+  FEE_TRG_STATUSBITS_OUT    <= fee_trg_statusbits_o;\r
+\r
+  -- Slave Bus              \r
+  SLV_DATA_OUT              <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT      <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT      <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT               <= slv_ack_o;    \r
+\r
+end Behavioral;\r
diff --git a/mupix/source/nx_trigger_validate.vhd b/mupix/source/nx_trigger_validate.vhd
new file mode 100644 (file)
index 0000000..5915259
--- /dev/null
@@ -0,0 +1,588 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+
+entity nx_trigger_validate is
+  port (
+    CLK_IN               : in  std_logic;  
+    RESET_IN             : in  std_logic;
+
+    -- Inputs
+    DATA_CLK_IN          : in  std_logic;
+    TIMESTAMP_IN         : in  std_logic_vector(13 downto 0);
+    CHANNEL_IN           : in  std_logic_vector(6 downto 0);
+    TIMESTAMP_STATUS_IN  : in  std_logic_vector(2 downto 0);
+    ADC_DATA_IN          : in  std_logic_vector(11 downto 0);
+    NX_TOKEN_RETURN_IN   : in  std_logic;
+    NX_NOMORE_DATA_IN    : in  std_logic;
+
+    TRIGGER_IN           : in  std_logic;
+    FAST_CLEAR_IN        : in  std_logic;
+    TRIGGER_BUSY_OUT     : out std_logic;
+    TIMESTAMP_REF_IN     : in  unsigned(11 downto 0);
+        
+    -- Outputs
+    DATA_OUT             : out std_logic_vector(31 downto 0);
+    DATA_CLK_OUT         : out std_logic;
+    NOMORE_DATA_OUT      : out std_logic;
+
+    -- Histogram
+    HISTOGRAM_FILL_OUT   : out std_logic;
+    HISTOGRAM_BIN_OUT    : out std_logic_vector(6 downto 0);
+    
+    -- Slave bus         
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+
+end entity;
+
+architecture Behavioral of nx_trigger_validate is
+
+  -- Sync Ref
+  signal timestamp_ref_x      : unsigned(11 downto 0);
+  signal timestamp_ref        : unsigned(11 downto 0);
+
+  -- Process Channel_Status
+  signal channel_index        : std_logic_vector(6 downto 0);
+  signal channel_wait         : std_logic_vector(127 downto 0);
+  signal channel_done         : std_logic_vector(127 downto 0);
+  signal channel_all_done     : std_logic;
+
+  -- Channel Status Commands
+  type CS_CMDS is (CS_RESET,
+                   CS_TOKEN_UPDATE,
+                   CS_SET_WAIT,
+                   CS_SET_DONE,
+                   CS_NONE
+                  );
+  signal channel_status_cmd   : CS_CMDS; 
+  
+  -- Process Timestamp
+  signal data_o               : std_logic_vector(31 downto 0);
+  signal data_clk_o           : std_logic;
+  signal out_of_window_l      : std_logic;
+  signal out_of_window_h      : std_logic;
+  signal ch_status_cmd_pr     : CS_CMDS;
+   
+  -- Process Trigger Handler
+  signal store_to_fifo        : std_logic;
+  signal trigger_busy_o       : std_logic;
+  signal nomore_data_o        : std_logic;
+  signal wait_timer_init      : unsigned(11 downto 0);
+  signal token_return_ctr     : std_logic;
+  signal ch_status_cmd_tr     : CS_CMDS;
+  
+  type STATES is (S_IDLE,
+                  S_TRIGGER,
+                  S_WAIT_DATA,
+                  S_PROCESS_START,
+                  S_WAIT_PROCESS_END,
+                  S_WRITE_TRAILER,
+                  S_SET_NOMORE_DATA
+                  );
+  signal STATE : STATES;
+
+  signal t_data_o             : std_logic_vector(31 downto 0);
+  signal t_data_clk_o         : std_logic;
+  signal busy_time_ctr        : unsigned(11 downto 0);
+  
+  -- Timer
+  signal wait_timer_done      : std_logic;
+
+  -- Histogram
+  signal histogram_fill_o     : std_logic;
+  signal histogram_bin_o      : std_logic_vector(6 downto 0);
+
+  -- Slave Bus                    
+  signal slv_data_out_o       : std_logic_vector(31 downto 0);
+  signal slv_no_more_data_o   : std_logic;
+  signal slv_unknown_addr_o   : std_logic;
+  signal slv_ack_o            : std_logic;
+
+  signal readout_mode         : std_logic_vector(3 downto 0);
+  signal trigger_window_width : unsigned(11 downto 0);
+  signal trigger_window_delay : unsigned(11 downto 0);
+  signal readout_time_max     : unsigned(11 downto 0);
+
+  signal window_lower_thr_r   : std_logic_vector(11 downto 0);
+  signal window_upper_thr_r   : std_logic_vector(11 downto 0);
+
+begin
+
+  -- Debug Line
+  DEBUG_OUT(0)            <= CLK_IN;
+--  DEBUG_OUT(2)            <= trigger_busy_o;
+--  DEBUG_OUT(3)            <= channel_all_done;
+--  DEBUG_OUT(4)            <= data_clk_o;
+--  DEBUG_OUT(5)            <= t_data_clk_o;
+--  DEBUG_OUT(6)            <= out_of_window_l;
+  --DEBUG_OUT(7)            <= out_of_window_h;
+  --DEBUG_OUT(8)            <= NX_TOKEN_RETURN_IN;
+  --DEBUG_OUT(9)            <= NX_NOMORE_DATA_IN;
+  --DEBUG_OUT(10)           <= store_to_fifo;
+  DEBUG_OUT(15 downto 1)  <= SLV_ADDR_IN(15 downto 1);
+  
+  -- Timer
+  nx_timer_1: nx_timer
+    generic map(
+      CTR_WIDTH => 12
+      )
+    port map (
+      CLK_IN         => CLK_IN,
+      RESET_IN       => RESET_IN,
+      TIMER_START_IN => wait_timer_init,
+      TIMER_DONE_OUT => wait_timer_done
+      );
+
+  -- Sync Timestamp Ref
+  PROC_SYNC_TIMESTAMP_REF: process (CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if (RESET_IN = '1') then
+        timestamp_ref_x <= (others => '0');
+        timestamp_ref   <= (others => '0');
+      else
+        timestamp_ref_x <= TIMESTAMP_REF_IN;
+        timestamp_ref   <= timestamp_ref_x;
+      end if;
+    end if;
+  end process PROC_SYNC_TIMESTAMP_REF;
+  
+  -----------------------------------------------------------------------------
+  -- Filter only valid events
+  -----------------------------------------------------------------------------
+
+  PROC_PROCESS_TIMESTAMP: process (CLK_IN)
+    variable ts_ref             : unsigned(11 downto 0);
+    variable window_lower_thr   : unsigned(11 downto 0);
+    variable window_upper_thr   : unsigned(11 downto 0);
+    variable deltaT             : unsigned(11 downto 0);
+
+  begin 
+    if( rising_edge(CLK_IN) ) then
+      if (RESET_IN = '1') then
+        data_o               <= (others => '0');
+        data_clk_o           <= '0';
+        out_of_window_l      <= '0';
+        out_of_window_h      <= '0';
+        window_lower_thr_r   <= (others => '0');
+        window_upper_thr_r   <= (others => '0');
+      else
+        data_o               <= (others => '0');
+        data_clk_o           <= '0';
+        out_of_window_l      <= '0';
+        out_of_window_h      <= '0';
+        ch_status_cmd_pr     <= CS_NONE;
+
+        histogram_fill_o     <= '0';
+        histogram_bin_o      <= (others => '0');
+        
+        if (DATA_CLK_IN = '1') then
+          if (store_to_fifo = '1') then
+            ts_ref             := timestamp_ref - x"010";
+            window_lower_thr   := trigger_window_delay;
+            window_upper_thr   := window_lower_thr + trigger_window_width;
+            deltaT             := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref;
+
+            window_lower_thr_r <= window_lower_thr;
+            window_upper_thr_r <= window_upper_thr;
+
+            case readout_mode is
+              
+              when x"0" =>            -- RefValue + valid and window filter 
+                if (TIMESTAMP_STATUS_IN(1) = '0') then
+                  if (deltaT < window_lower_thr) then
+                    out_of_window_l        <= '1';
+                    data_clk_o             <= '0';
+                    -- IN LUT-Data bit setzten.
+                    channel_index          <= CHANNEL_IN;
+                    ch_status_cmd_pr       <= CS_SET_WAIT;
+                  elsif (deltaT > window_upper_thr) then
+                    out_of_window_h        <= '1';
+                    data_clk_o             <= '0';
+                    -- In LUT-Done Bit setzten
+                    channel_index          <= CHANNEL_IN;
+                    ch_status_cmd_pr       <= CS_SET_DONE;
+                  else
+                    -- IN LUT-Data bit setzten.
+                    channel_index          <= CHANNEL_IN;
+                    ch_status_cmd_pr       <= CS_SET_WAIT;
+                    
+                    data_o(11 downto  0)   <= deltaT;
+                    data_o(23 downto 12)   <= ADC_DATA_IN;
+                    data_o(30 downto 24)   <= CHANNEL_IN;
+                    data_o(31)             <= '0';
+                    data_clk_o <= '1';
+                  end if;
+                end if;
+                
+              when x"1" =>            -- RefValue + valid filter
+                if (TIMESTAMP_STATUS_IN(1) = '0') then
+                  data_o(11 downto  0)     <= deltaT;
+                  data_o(23 downto 12)     <= ADC_DATA_IN;
+                  data_o(30 downto 24)     <= CHANNEL_IN;
+                  data_o(31)               <= '0';
+                  data_clk_o               <= '1';
+                end if;
+
+              when x"3" =>            -- RefValue + valid filter
+                if (TIMESTAMP_STATUS_IN(1) = '0') then
+                  data_o(11 downto  0)     <= TIMESTAMP_IN(13 downto 2);
+                  data_o(23 downto 12)     <= ADC_DATA_IN;
+                  data_o(30 downto 24)     <= CHANNEL_IN;
+                  data_o(31)               <= '0';
+                  data_clk_o <= '1';
+                end if;
+                
+              when x"4" =>            -- RawValue
+                data_o(11 downto  0)       <= TIMESTAMP_IN(13 downto 2);
+                data_o(23 downto 12)       <= ADC_DATA_IN;
+                data_o(30 downto 24)       <= CHANNEL_IN;
+                data_o(31)                 <= '0';
+                data_clk_o                 <= '1';
+
+              when x"5" =>            -- RawValue + valid filter
+                if (TIMESTAMP_STATUS_IN(1) = '0') then
+                  data_o(11 downto  0)     <= TIMESTAMP_IN(13 downto 2);
+                  data_o(23 downto 12)     <= ADC_DATA_IN;
+                  data_o(30 downto 24)     <= CHANNEL_IN;
+                  data_o(31)               <= '0';
+                  data_clk_o               <= '1';
+                end if;
+
+              when others => null;
+
+            end case;
+
+          end if;
+
+          -- Fill Histogram
+          histogram_fill_o    <= '1';
+          histogram_bin_o     <= CHANNEL_IN;
+        end if;
+      end if;
+    end if;
+  end process PROC_PROCESS_TIMESTAMP;
+
+  -----------------------------------------------------------------------------
+  -- Trigger Handler
+  -----------------------------------------------------------------------------
+
+  PROC_TRIGGER_HANDLER: process(CLK_IN)
+    variable min_validation_time : unsigned(23 downto 0);
+
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if (RESET_IN = '1') then
+        store_to_fifo         <= '0';
+        trigger_busy_o        <= '0';
+        nomore_data_o         <= '0';
+        wait_timer_init       <= (others => '0');
+        t_data_o              <= (others => '0');
+        t_data_clk_o          <= '0';
+        busy_time_ctr         <= (others => '0');
+        token_return_ctr      <= '0';
+        ch_status_cmd_tr      <= CS_RESET;
+        STATE                 <= S_IDLE;
+      else
+        store_to_fifo         <= '0';
+        wait_timer_init       <= (others => '0');
+        trigger_busy_o        <= '1';
+        nomore_data_o         <= '0';
+        t_data_o              <= (others => '0');
+        t_data_clk_o          <= '0';
+        ch_status_cmd_tr      <= CS_NONE;
+
+        min_validation_time := x"020" +
+                               (trigger_window_delay * 2 +
+                                trigger_window_delay / 2) +
+                               (trigger_window_width * 2 +
+                                trigger_window_width / 2);
+        
+        case STATE is
+          
+          when S_IDLE =>
+            if (TRIGGER_IN = '1') then
+              busy_time_ctr        <= (others => '0');
+              STATE                <= S_TRIGGER;
+            else
+              trigger_busy_o       <= '0';
+              STATE                <= S_IDLE;
+            end if;
+            
+          when S_TRIGGER =>
+            ch_status_cmd_tr       <= CS_RESET;
+            wait_timer_init        <= x"020";    -- wait 320ns for first event
+            STATE                  <= S_WAIT_DATA;
+            
+          when S_WAIT_DATA =>
+            if (wait_timer_done = '0') then
+              STATE                <= S_WAIT_DATA;
+            else
+              STATE                <= S_PROCESS_START;
+            end if;
+            
+          when S_PROCESS_START =>
+            token_return_ctr       <= '0';
+            wait_timer_init        <= readout_time_max; 
+            store_to_fifo          <= '1';
+            STATE                  <= S_WAIT_PROCESS_END;
+            
+          when S_WAIT_PROCESS_END =>
+            if (wait_timer_done   = '1' or
+                channel_all_done  = '1' or
+                (NX_NOMORE_DATA_IN = '1' and
+                 busy_time_ctr > min_validation_time(11 downto 0))
+                )
+            then
+              STATE                <= S_WRITE_TRAILER;
+            else
+              store_to_fifo        <= '1';
+              STATE                <= S_WAIT_PROCESS_END;
+              
+              -- Check Token_Return
+              if (busy_time_ctr > min_validation_time(11 downto 0)) then
+                if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
+                  if (token_return_ctr = '1') then
+                    ch_status_cmd_tr <= CS_TOKEN_UPDATE;
+                  end if;
+                  token_return_ctr   <= token_return_ctr or '1';
+                end if;
+              end if;
+
+            end if;
+                    
+          when S_WRITE_TRAILER =>
+            t_data_o               <= x"deadaffe";
+            t_data_clk_o           <= '1';
+            ch_status_cmd_tr       <= CS_RESET;
+            STATE                  <= S_SET_NOMORE_DATA;
+
+          when S_SET_NOMORE_DATA =>
+            nomore_data_o          <= '1';
+            STATE                  <= S_IDLE;
+        end case;
+
+        if (STATE /= S_IDLE) then
+          busy_time_ctr            <= busy_time_ctr + 1;
+        end if;      
+
+      end if;
+    end if;
+  end process PROC_TRIGGER_HANDLER;
+
+  -----------------------------------------------------------------------------
+  -- Channel Status Handler
+  -----------------------------------------------------------------------------
+
+  PROC_CHANNEL_STATUS_CMD: process(ch_status_cmd_tr,
+                                   ch_status_cmd_pr)
+  begin
+    if (ch_status_cmd_tr /= CS_NONE) then
+      channel_status_cmd   <= ch_status_cmd_tr;
+    elsif (ch_status_cmd_pr /= CS_NONE) then
+      channel_status_cmd   <= ch_status_cmd_pr;
+    else
+      channel_status_cmd   <= CS_NONE;
+    end if;
+  end process PROC_CHANNEL_STATUS_CMD;
+
+  
+  PROC_CHANNEL_STATUS: process(CLK_IN)
+    constant all_one : std_logic_vector(127 downto 0) := (others => '1');
+    
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1') then
+        channel_wait       <= (others => '0');
+        channel_done       <= (others => '0');
+        channel_all_done   <= '0';
+
+      else
+        -- Check done status
+        if (channel_done = all_one) then
+          channel_all_done    <= '1';
+        end if;
+
+        -- Process Command
+        case channel_status_cmd is
+
+          when CS_RESET =>
+            channel_wait      <= (others => '0');
+            channel_done      <= (others => '0');
+            channel_all_done  <= '0';
+
+          when CS_TOKEN_UPDATE =>
+            channel_done      <= channel_done or (not channel_wait);
+            channel_wait      <= (others => '0');
+            
+          when CS_SET_WAIT =>
+            channel_wait(to_integer(unsigned(channel_index))) <= '1';
+      
+          when CS_SET_DONE =>
+            channel_done(to_integer(unsigned(channel_index))) <= '1';
+      
+          when others => null;
+
+        end case;
+      end if;
+    end if;
+  end process PROC_CHANNEL_STATUS;
+  
+  -----------------------------------------------------------------------------
+  -- TRBNet Slave Bus
+  -----------------------------------------------------------------------------
+
+  -- Give status info to the TRB Slow Control Channel
+  PROC_FIFO_REGISTERS: process(CLK_IN)
+
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        slv_data_out_o         <= (others => '0');
+        slv_ack_o              <= '0';
+        slv_unknown_addr_o     <= '0';
+        slv_no_more_data_o     <= '0';
+        readout_mode           <= "0000";
+        trigger_window_delay   <= (others => '0');
+        trigger_window_width   <= x"020";
+        readout_time_max       <= x"640";
+      else
+        slv_data_out_o         <= (others => '0');
+        slv_unknown_addr_o     <= '0';
+        slv_no_more_data_o     <= '0';
+        
+        if (SLV_READ_IN  = '1') then
+          case SLV_ADDR_IN is
+            when x"0000" =>
+              slv_data_out_o(3 downto 0)   <= readout_mode;
+              slv_data_out_o(31 downto 4)  <= (others => '0');
+              slv_ack_o                    <= '1';
+
+            when x"0001" =>
+              slv_data_out_o(11 downto 0)  <=
+                std_logic_vector(trigger_window_delay);
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1';
+
+            when x"0002" =>
+              slv_data_out_o(11 downto 0)  <=
+                std_logic_vector(trigger_window_width);
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1';
+
+            when x"0003" =>
+              slv_data_out_o(11 downto 0)  <=
+                std_logic_vector(readout_time_max);
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1'; 
+
+            when x"0004" =>
+              slv_data_out_o(11 downto 0)  <=
+                std_logic_vector(busy_time_ctr);
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1'; 
+
+            when x"0005" =>
+              slv_data_out_o(11 downto 0)  <= timestamp_ref;
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1';  
+
+            when x"0006" =>
+              slv_data_out_o(11 downto 0)  <= window_lower_thr_r;
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1';  
+
+            when x"0007" =>
+              slv_data_out_o(11 downto 0)  <= window_upper_thr_r;
+              slv_data_out_o(31 downto 12) <= (others => '0');
+              slv_ack_o                    <= '1';  
+              
+            when x"0008" =>
+              slv_data_out_o               <=
+                std_logic_vector(channel_done(31 downto 0));
+              slv_ack_o                    <= '1'; 
+
+            when x"0009" =>
+              slv_data_out_o               <=
+                std_logic_vector(channel_done(63 downto 32));
+              slv_ack_o                    <= '1'; 
+
+            when x"000a" =>
+              slv_data_out_o               <=
+                std_logic_vector(channel_done(95 downto 64));
+              slv_ack_o                    <= '1'; 
+
+            when x"000b" =>
+              slv_data_out_o               <=
+                std_logic_vector(channel_done(127 downto 96));
+              slv_ack_o                    <= '1'; 
+              
+            when others  =>
+              slv_unknown_addr_o           <= '1';
+              slv_ack_o                    <= '0';
+
+          end case;
+          
+        elsif (SLV_WRITE_IN  = '1') then
+          case SLV_ADDR_IN is
+            when x"0000" =>
+              readout_mode                 <= SLV_DATA_IN(3 downto 0);
+              slv_ack_o                    <= '1';
+
+            when x"0001" =>
+              trigger_window_delay         <= SLV_DATA_IN(11 downto 0);
+              slv_ack_o                    <= '1';
+
+            when x"0002" =>
+              trigger_window_width         <=
+                unsigned(SLV_DATA_IN(11 downto 0));
+              slv_ack_o                    <= '1';
+
+            when x"0003" =>
+              readout_time_max             <=
+                unsigned(SLV_DATA_IN(11 downto 0));
+              slv_ack_o                    <= '1';
+              
+            when others  =>
+              slv_unknown_addr_o           <= '1';
+              slv_ack_o                    <= '0';
+          end case;                
+        else
+          slv_ack_o                        <= '0';
+        end if;
+      end if;
+    end if;
+  end process PROC_FIFO_REGISTERS;
+  
+  -----------------------------------------------------------------------------
+  -- Output Signals
+  -----------------------------------------------------------------------------
+
+  TRIGGER_BUSY_OUT      <= trigger_busy_o;
+  DATA_OUT              <= data_o or t_data_o;
+  DATA_CLK_OUT          <= data_clk_o or t_data_clk_o;
+  NOMORE_DATA_OUT       <= nomore_data_o;
+
+  HISTOGRAM_FILL_OUT    <= histogram_fill_o;
+  HISTOGRAM_BIN_OUT     <= histogram_bin_o;
+  
+  -- Slave 
+  SLV_DATA_OUT          <= slv_data_out_o;    
+  SLV_NO_MORE_DATA_OUT  <= slv_no_more_data_o; 
+  SLV_UNKNOWN_ADDR_OUT  <= slv_unknown_addr_o;
+  SLV_ACK_OUT           <= slv_ack_o;
+
+end Behavioral;
diff --git a/mupix/source/nxyter_components.vhd b/mupix/source/nxyter_components.vhd
new file mode 100644 (file)
index 0000000..1e00309
--- /dev/null
@@ -0,0 +1,655 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package nxyter_components is
+
+-------------------------------------------------------------------------------
+-- TRBNet interfaces
+-------------------------------------------------------------------------------
+
+  component nXyter_FEE_board
+    generic (
+    BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+    );
+    port (
+      CLK_IN                     : in    std_logic;
+      RESET_IN                   : in    std_logic;
+
+      CLK_NX_IN                  : in    std_logic;
+      CLK_ADC_IN                 : in    std_logic;
+
+      I2C_SDA_INOUT              : inout std_logic;
+      I2C_SCL_INOUT              : inout std_logic;
+      I2C_SM_RESET_OUT           : out   std_logic;
+      I2C_REG_RESET_OUT          : out   std_logic;
+
+      SPI_SCLK_OUT               : out   std_logic;
+      SPI_SDIO_INOUT             : inout std_logic;
+      SPI_CSB_OUT                : out   std_logic;
+
+      NX_CLK128_IN               : in    std_logic;
+      NX_TIMESTAMP_IN            : in    std_logic_vector (7 downto 0);
+      NX_RESET_OUT               : out   std_logic;
+      NX_TESTPULSE_OUT           : out   std_logic;
+
+      ADC_FCLK_IN                : in    std_logic_vector(1 downto 0);
+      ADC_DCLK_IN                : in    std_logic_vector(1 downto 0);
+      ADC_SAMPLE_CLK_OUT         : out   std_logic;
+      ADC_A_IN                   : in    std_logic_vector(1 downto 0);
+      ADC_B_IN                   : in    std_logic_vector(1 downto 0);
+      ADC_NX_IN                  : in    std_logic_vector(1 downto 0);
+      ADC_D_IN                   : in    std_logic_vector(1 downto 0);
+
+      LVL1_TRG_DATA_VALID_IN     : in    std_logic;
+      LVL1_VALID_TIMING_TRG_IN   : in    std_logic;
+      LVL1_VALID_NOTIMING_TRG_IN : in    std_logic;
+      LVL1_INVALID_TRG_IN        : in    std_logic;
+      LVL1_TRG_TYPE_IN           : in    std_logic_vector(3 downto 0);
+      LVL1_TRG_NUMBER_IN         : in    std_logic_vector(15 downto 0);
+      LVL1_TRG_CODE_IN           : in    std_logic_vector(7 downto 0);
+      LVL1_TRG_INFORMATION_IN    : in    std_logic_vector(23 downto 0);
+      LVL1_INT_TRG_NUMBER_IN     : in    std_logic_vector(15 downto 0);
+
+      FEE_TRG_RELEASE_OUT        : out   std_logic;
+      FEE_TRG_STATUSBITS_OUT     : out   std_logic_vector(31 downto 0);
+      FEE_DATA_OUT               : out   std_logic_vector(31 downto 0);
+      FEE_DATA_WRITE_OUT         : out   std_logic;
+      FEE_DATA_FINISHED_OUT      : out   std_logic;
+      FEE_DATA_ALMOST_FULL_IN    : in    std_logic;
+
+      REGIO_ADDR_IN              : in    std_logic_vector(15 downto 0);
+      REGIO_DATA_IN              : in    std_logic_vector(31 downto 0);
+      REGIO_DATA_OUT             : out   std_logic_vector(31 downto 0);
+      REGIO_READ_ENABLE_IN       : in    std_logic;
+      REGIO_WRITE_ENABLE_IN      : in    std_logic;
+      REGIO_TIMEOUT_IN           : in    std_logic;
+      REGIO_DATAREADY_OUT        : out   std_logic;
+      REGIO_WRITE_ACK_OUT        : out   std_logic;
+      REGIO_NO_MORE_DATA_OUT     : out   std_logic;
+      REGIO_UNKNOWN_ADDR_OUT     : out   std_logic;
+
+      DEBUG_LINE_OUT             : out   std_logic_vector(15 downto 0)
+      );
+  end component;
+
+-------------------------------------------------------------------------------
+-- nXyter I2C Interface
+-------------------------------------------------------------------------------
+
+
+component nx_i2c_master
+  generic (
+    I2C_SPEED : unsigned(11 downto 0)
+    );
+  port (
+    CLK_IN               : in    std_logic;
+    RESET_IN             : in    std_logic;
+    SDA_INOUT            : inout std_logic;
+    SCL_INOUT            : inout std_logic;
+    INTERNAL_COMMAND_IN  : in    std_logic_vector(31 downto 0);
+    COMMAND_BUSY_OUT     : out   std_logic;
+    I2C_DATA_OUT         : out   std_logic_vector(31 downto 0);
+    I2C_LOCK_IN          : in    std_logic;
+    SLV_READ_IN          : in    std_logic;
+    SLV_WRITE_IN         : in    std_logic;
+    SLV_DATA_OUT         : out   std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in    std_logic_vector(31 downto 0);
+    SLV_ACK_OUT          : out   std_logic;
+    SLV_NO_MORE_DATA_OUT : out   std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out   std_logic;
+    DEBUG_OUT            : out   std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_i2c_startstop
+  generic (
+    I2C_SPEED : unsigned(11 downto 0)
+    );
+  port (
+    CLK_IN            : in  std_logic;
+    RESET_IN          : in  std_logic;
+    START_IN          : in  std_logic;  -- Start Sequence
+    SELECT_IN         : in  std_logic;  -- '1' -> Start, '0'-> Stop
+    SEQUENCE_DONE_OUT : out std_logic;
+    SDA_OUT           : out std_logic;
+    SCL_OUT           : out std_logic;
+    NREADY_OUT        : out std_logic
+    );
+end component;
+
+component nx_i2c_sendbyte
+  generic (
+    I2C_SPEED : unsigned(11 downto 0)
+    );
+  port (
+    CLK_IN            : in  std_logic;
+    RESET_IN          : in  std_logic;
+    START_IN          : in  std_logic;
+    BYTE_IN           : in  std_logic_vector(7 downto 0);
+    SEQUENCE_DONE_OUT : out std_logic;
+    SDA_OUT           : out std_logic;
+    SCL_OUT           : out std_logic;
+    SDA_IN            : in  std_logic;
+    ACK_OUT           : out std_logic
+    );
+end component;
+
+component nx_i2c_readbyte
+  generic (
+    I2C_SPEED : unsigned(11 downto 0)
+    );
+  port (
+    CLK_IN            : in  std_logic;
+    RESET_IN          : in  std_logic;
+    START_IN          : in  std_logic;
+    BYTE_OUT          : out std_logic_vector(7 downto 0);
+    SEQUENCE_DONE_OUT : out std_logic;
+    SDA_OUT           : out std_logic;
+    SCL_OUT           : out std_logic;
+    SDA_IN            : in  std_logic
+    );
+end component;
+
+-------------------------------------------------------------------------------
+-- ADC SPI Interface
+-------------------------------------------------------------------------------
+
+component adc_spi_master
+  generic (
+    SPI_SPEED : unsigned(7 downto 0)
+    );
+  port (
+    CLK_IN               : in    std_logic;
+    RESET_IN             : in    std_logic;
+    SCLK_OUT             : out   std_logic;
+    SDIO_INOUT           : inout std_logic;
+    CSB_OUT              : out   std_logic;
+    INTERNAL_COMMAND_IN  : in    std_logic_vector(31 downto 0);
+    COMMAND_BUSY_OUT     : out   std_logic;
+    SPI_DATA_OUT         : out   std_logic_vector(31 downto 0);
+    SPI_LOCK_IN          : in    std_logic;
+    SLV_READ_IN          : in    std_logic;
+    SLV_WRITE_IN         : in    std_logic;
+    SLV_DATA_OUT         : out   std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in    std_logic_vector(31 downto 0);
+    SLV_ACK_OUT          : out   std_logic;
+    SLV_NO_MORE_DATA_OUT : out   std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out   std_logic;
+    DEBUG_OUT            : out   std_logic_vector(15 downto 0)
+    );
+end component;
+
+component adc_spi_sendbyte
+  generic (
+    SPI_SPEED : unsigned(7 downto 0)
+    );
+  port (
+    CLK_IN            : in  std_logic;
+    RESET_IN          : in  std_logic;
+    START_IN          : in  std_logic;
+    BYTE_IN           : in  std_logic_vector(7 downto 0);
+    SEQUENCE_DONE_OUT : out std_logic;
+    SCLK_OUT          : out std_logic;
+    SDIO_OUT          : out std_logic
+    );
+end component;
+
+component adc_spi_readbyte
+  generic (
+    SPI_SPEED : unsigned(7 downto 0)
+    );
+  port (
+    CLK_IN            : in  std_logic;
+    RESET_IN          : in  std_logic;
+    START_IN          : in  std_logic;
+    BYTE_OUT          : out std_logic_vector(7 downto 0);
+    SEQUENCE_DONE_OUT : out std_logic;
+    SDIO_IN           : in  std_logic;
+    SCLK_OUT          : out std_logic
+    );
+end component;
+
+-------------------------------------------------------------------------------
+-- TRBNet Registers
+-------------------------------------------------------------------------------
+
+component nx_setup
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    I2C_COMMAND_OUT      : out std_logic_vector(31 downto 0);
+    I2C_COMMAND_BUSY_IN  : in  std_logic;
+    I2C_DATA_IN          : in  std_logic_vector(31 downto 0);
+    I2C_LOCK_OUT         : out std_logic;
+    SPI_COMMAND_OUT      : out std_logic_vector(31 downto 0);
+    SPI_COMMAND_BUSY_IN  : in  std_logic;
+    SPI_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SPI_LOCK_OUT         : out std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nxyter_registers
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    I2C_SM_RESET_OUT     : out std_logic;
+    I2C_REG_RESET_OUT    : out std_logic;
+    NX_TS_RESET_OUT      : out std_logic;
+    OFFLINE_OUT          : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component clock10MHz
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    LOCK  : out std_logic
+    );
+end component;
+
+component fifo_ts_32to32_dc
+  port (
+    Data          : in  std_logic_vector(31 downto 0);
+    WrClock       : in  std_logic;
+    RdClock       : in  std_logic;
+    WrEn          : in  std_logic;
+    RdEn          : in  std_logic;
+    Reset         : in  std_logic;
+    RPReset       : in  std_logic;
+    AmEmptyThresh : in  std_logic_vector(4 downto 0);
+    Q             : out std_logic_vector(31 downto 0);
+    Empty         : out std_logic;
+    Full          : out std_logic;
+    AlmostEmpty   : out  std_logic
+    );
+end component;
+
+component fifo_32_data
+  port (
+    Data        : in  std_logic_vector(31 downto 0);
+    Clock       : in  std_logic;
+    WrEn        : in  std_logic;
+    RdEn        : in  std_logic;
+    Reset       : in  std_logic;
+    Q           : out std_logic_vector(31 downto 0);
+    WCNT        : out std_logic_vector(10 downto 0);
+    Empty       : out std_logic;
+    Full        : out std_logic
+    );
+end component;
+
+component nx_data_receiver
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    NX_TIMESTAMP_CLK_IN  : in  std_logic;
+    NX_TIMESTAMP_IN      : in  std_logic_vector (7 downto 0);
+    ADC_CLK_DAT_IN       : in  std_logic;
+    ADC_FCLK_IN          : in  std_logic_vector(1 downto 0);
+    ADC_DCLK_IN          : in  std_logic_vector(1 downto 0);
+    ADC_SAMPLE_CLK_OUT   : out std_logic;
+    ADC_A_IN             : in  std_logic_vector(1 downto 0);
+    ADC_B_IN             : in  std_logic_vector(1 downto 0);
+    ADC_NX_IN            : in  std_logic_vector(1 downto 0);
+    ADC_D_IN             : in  std_logic_vector(1 downto 0);
+    NX_TIMESTAMP_OUT     : out std_logic_vector(31 downto 0);
+    ADC_DATA_OUT         : out std_logic_vector(11 downto 0);
+    NEW_DATA_OUT         : out std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_data_validate
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    NX_TIMESTAMP_IN      : in  std_logic_vector(31 downto 0);
+    ADC_DATA_IN          : in  std_logic_vector(11 downto 0);
+    NEW_DATA_IN          : in  std_logic;
+    TIMESTAMP_OUT        : out std_logic_vector(13 downto 0);
+    CHANNEL_OUT          : out std_logic_vector(6 downto 0);
+    TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0);
+    ADC_DATA_OUT         : out std_logic_vector(11 downto 0);
+    DATA_VALID_OUT       : out std_logic;
+    NX_TOKEN_RETURN_OUT  : out std_logic;
+    NX_NOMORE_DATA_OUT   : out std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_trigger_validate
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    DATA_CLK_IN          : in  std_logic;
+    TIMESTAMP_IN         : in  std_logic_vector(13 downto 0);
+    CHANNEL_IN           : in  std_logic_vector(6 downto 0);
+    TIMESTAMP_STATUS_IN  : in  std_logic_vector(2 downto 0);
+    ADC_DATA_IN          : in  std_logic_vector(11 downto 0);
+    NX_TOKEN_RETURN_IN   : in  std_logic;
+    NX_NOMORE_DATA_IN    : in  std_logic;
+    TRIGGER_IN           : in  std_logic;
+    FAST_CLEAR_IN        : in  std_logic;
+    TRIGGER_BUSY_OUT     : out std_logic;
+    TIMESTAMP_REF_IN     : in  unsigned(11 downto 0);
+    DATA_OUT             : out std_logic_vector(31 downto 0);
+    DATA_CLK_OUT         : out std_logic;
+    NOMORE_DATA_OUT      : out std_logic;
+    HISTOGRAM_FILL_OUT   : out std_logic;
+    HISTOGRAM_BIN_OUT    : out std_logic_vector(6 downto 0);
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_event_buffer
+  generic (
+    BOARD_ID : std_logic_vector(15 downto 0));
+  port (
+    CLK_IN                  : in  std_logic;
+    RESET_IN                : in  std_logic;
+    RESET_DATA_BUFFER_IN    : in  std_logic;
+    NXYTER_OFFLINE_IN       : in  std_logic;
+    DATA_IN                 : in  std_logic_vector(31 downto 0);
+    DATA_CLK_IN             : in  std_logic;
+    EVT_NOMORE_DATA_IN      : in  std_logic;
+    LVL2_TRIGGER_IN         : in  std_logic;
+    FAST_CLEAR_IN           : in  std_logic;
+    TRIGGER_BUSY_OUT        : out std_logic;
+    FEE_DATA_OUT            : out std_logic_vector(31 downto 0);
+    FEE_DATA_WRITE_OUT      : out std_logic;
+    FEE_DATA_FINISHED_OUT   : out std_logic;
+    FEE_DATA_ALMOST_FULL_IN : in  std_logic;
+    SLV_READ_IN             : in  std_logic;
+    SLV_WRITE_IN            : in  std_logic;
+    SLV_DATA_OUT            : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN             : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN             : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT             : out std_logic;
+    SLV_NO_MORE_DATA_OUT    : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT    : out std_logic;
+    DEBUG_OUT               : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+-------------------------------------------------------------------------------
+
+component nx_histograms
+  generic (
+    NUM_BINS : integer);
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    RESET_HISTS_IN       : in  std_logic;
+    CHANNEL_STAT_FILL_IN : in  std_logic;
+    CHANNEL_ID_IN        : in  std_logic_vector(NUM_BINS - 1 downto 0);
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0));
+end component;
+
+-------------------------------------------------------------------------------
+
+component level_to_pulse
+  port (
+    CLK_IN         : in  std_logic;
+    RESET_IN       : in  std_logic;
+    LEVEL_IN       : in  std_logic;
+    PULSE_OUT      : out std_logic
+    );
+end component;
+
+component pulse_to_level
+  generic (
+    NUM_CYCLES : unsigned(4 downto 0) := "11111"
+    );
+  port (
+    CLK_IN    : in  std_logic;
+    RESET_IN  : in  std_logic;
+    PULSE_IN  : in  std_logic;
+    LEVEL_OUT : out std_logic
+    );
+end component;
+
+component Gray_Decoder
+  generic (
+    WIDTH : integer
+    );
+  port (
+    CLK_IN     : in  std_logic;
+    RESET_IN   : in  std_logic;
+    GRAY_IN    : in  std_logic_vector(WIDTH - 1 downto 0);
+    BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
+    );
+end component;
+
+component Gray_Encoder
+  generic (
+    WIDTH : integer
+    );
+  port (
+    CLK_IN    : in  std_logic;
+    RESET_IN  : in  std_logic;
+    BINARY_IN : in  std_logic_vector(WIDTH - 1 downto 0);
+    GRAY_OUT  : out std_logic_vector(WIDTH - 1 downto 0)
+    );
+end component;
+
+component pll_125_hub
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    CLKOK : out std_logic;
+    LOCK  : out std_logic
+    );
+end component;
+
+component pll_nx_clk256
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    LOCK  : out std_logic);
+end component;
+
+component pll_nx_clk250
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    LOCK  : out std_logic);
+end component;
+
+component pll_adc_clk32
+  port (
+    CLK    : in  std_logic;
+    CLKOP  : out std_logic;
+    LOCK   : out std_logic
+    );
+end component;
+
+component pll_adc_clk192
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    LOCK  : out std_logic
+    );
+end component;
+
+component pll_adc_clk3125
+  port (
+    CLK   : in  std_logic;
+    CLKOP : out std_logic;
+    LOCK  : out std_logic
+    );
+end component;
+
+component nx_fpga_timestamp
+  port (
+    CLK_IN                : in  std_logic;
+    RESET_IN              : in  std_logic;
+    TIMESTAMP_SYNC_IN     : in  std_logic;
+    TRIGGER_IN            : in  std_logic;
+    TIMESTAMP_OUT         : out unsigned(11 downto 0);
+    NX_TIMESTAMP_SYNC_OUT : in  std_logic;
+    SLV_READ_IN           : in  std_logic;
+    SLV_WRITE_IN          : in  std_logic;
+    SLV_DATA_OUT          : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN           : in  std_logic_vector(31 downto 0);
+    SLV_ACK_OUT           : out std_logic;
+    SLV_NO_MORE_DATA_OUT  : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT  : out std_logic;
+    DEBUG_OUT             : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_trigger_handler
+  port (
+    CLK_IN                     : in  std_logic;
+    RESET_IN                   : in  std_logic;
+    NXYTER_OFFLINE_IN          : in  std_logic;
+    LVL1_TRG_DATA_VALID_IN     : in  std_logic;
+    LVL1_VALID_TIMING_TRG_IN   : in  std_logic;
+    LVL1_VALID_NOTIMING_TRG_IN : in  std_logic;
+    LVL1_INVALID_TRG_IN        : in  std_logic;
+    LVL1_TRG_TYPE_IN           : in  std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_IN         : in  std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_IN           : in  std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_IN    : in  std_logic_vector(23 downto 0);
+    LVL1_INT_TRG_NUMBER_IN     : in  std_logic_vector(15 downto 0);
+    FEE_TRG_RELEASE_OUT        : out std_logic;
+    FEE_TRG_STATUSBITS_OUT     : out std_logic_vector(31 downto 0);
+    INTERNAL_TRIGGER_IN        : in  std_logic;
+    TRIGGER_VALIDATE_BUSY_IN   : in  std_logic;
+    LVL2_TRIGGER_BUSY_IN       : in  std_logic;
+    VALIDATE_TRIGGER_OUT       : out std_logic;
+    TIMESTAMP_HOLD_OUT         : out std_logic;
+    LVL2_TRIGGER_OUT           : out std_logic;
+    EVENT_BUFFER_CLEAR_OUT     : out std_logic;
+    FAST_CLEAR_OUT             : out std_logic;
+    TRIGGER_BUSY_OUT           : out std_logic;
+    SLV_READ_IN                : in  std_logic;
+    SLV_WRITE_IN               : in  std_logic;
+    SLV_DATA_OUT               : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN                : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN                : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT                : out std_logic;
+    SLV_NO_MORE_DATA_OUT       : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT       : out std_logic;
+    DEBUG_OUT                  : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+component nx_trigger_generator
+  port (
+    CLK_IN               : in  std_logic;
+    RESET_IN             : in  std_logic;
+    TRIGGER_OUT          : out std_logic;
+    TS_RESET_OUT         : out std_logic;
+    TESTPULSE_OUT        : out std_logic;
+    SLV_READ_IN          : in  std_logic;
+    SLV_WRITE_IN         : in  std_logic;
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);
+    SLV_ACK_OUT          : out std_logic;
+    SLV_NO_MORE_DATA_OUT : out std_logic;
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+-------------------------------------------------------------------------------
+-- ADC Handler
+-------------------------------------------------------------------------------
+component adc_ad9228
+  port (
+    CLK_IN           : in  std_logic;
+    RESET_IN         : in  std_logic;
+    ADC_FCLK_IN      : in  std_logic;
+    ADC_DCLK_IN      : in  std_logic;
+    ADC_SC_CLK32_OUT : out std_logic;
+    ADC_A_IN         : in  std_logic;
+    ADC_B_IN         : in  std_logic;
+    ADC_NX_IN        : in  std_logic;
+    ADC_D_IN         : in  std_logic;
+    DEBUG_OUT        : out std_logic_vector(15 downto 0)
+    );
+end component;
+
+-------------------------------------------------------------------------------
+-- Misc Tools
+-------------------------------------------------------------------------------
+
+component nx_timer
+  generic (
+    CTR_WIDTH : integer
+    );
+  port (
+    CLK_IN         : in  std_logic;
+    RESET_IN       : in  std_logic;
+    TIMER_START_IN : in  unsigned(CTR_WIDTH - 1 downto 0);
+    TIMER_DONE_OUT : out std_logic
+    );
+end component;
+
+-------------------------------------------------------------------------------
+-- Simulations
+-------------------------------------------------------------------------------
+
+component nxyter_timestamp_sim
+  port (
+    CLK_IN        : in  std_logic;
+    RESET_IN      : in  std_logic;
+    TIMESTAMP_OUT : out std_logic_vector(7 downto 0);
+    CLK128_OUT    : out std_logic
+    );
+end component;
+
+end package;
diff --git a/mupix/source/nxyter_fee_board.vhd b/mupix/source/nxyter_fee_board.vhd
new file mode 100644 (file)
index 0000000..30736ff
--- /dev/null
@@ -0,0 +1,701 @@
+---------------------------------------------------------------------------
+--
+-- One  nXyter FEB 
+--
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.nxyter_components.all;
+
+entity nXyter_FEE_board is
+  generic (
+    BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+    );
+  port (
+    CLK_IN                     : in std_logic;  
+    RESET_IN                   : in std_logic;
+    CLK_NX_IN                  : in std_logic;
+    CLK_ADC_IN                 : in std_logic;
+                                
+    -- I2C Ports                
+    I2C_SDA_INOUT              : inout std_logic;   -- nXyter I2C fdata line
+    I2C_SCL_INOUT              : inout std_logic;   -- nXyter I2C Clock line
+    I2C_SM_RESET_OUT           : out std_logic;     -- reset nXyter I2C SMachine 
+    I2C_REG_RESET_OUT          : out std_logic;     -- reset I2C registers 
+                                
+    -- ADC SPI                  
+    SPI_SCLK_OUT               : out std_logic;
+    SPI_SDIO_INOUT             : inout std_logic;
+    SPI_CSB_OUT                : out std_logic;    
+                                
+    -- nXyter Timestamp Ports
+    NX_CLK128_IN               : in std_logic;
+    NX_TIMESTAMP_IN            : in std_logic_vector (7 downto 0);
+    NX_RESET_OUT               : out std_logic;
+    NX_TESTPULSE_OUT           : out std_logic;
+                                
+    -- ADC nXyter Pulse Hight Ports
+    ADC_FCLK_IN                : in  std_logic_vector(1 downto 0);
+    ADC_DCLK_IN                : in  std_logic_vector(1 downto 0);
+    ADC_SAMPLE_CLK_OUT         : out std_logic;
+    ADC_A_IN                   : in  std_logic_vector(1 downto 0);
+    ADC_B_IN                   : in  std_logic_vector(1 downto 0);
+    ADC_NX_IN                  : in  std_logic_vector(1 downto 0);
+    ADC_D_IN                   : in  std_logic_vector(1 downto 0);        
+                                
+    -- Event Buffer
+    --LVL1 trigger to FEE
+    LVL1_TRG_DATA_VALID_IN     : in std_logic;
+    LVL1_VALID_TIMING_TRG_IN   : in std_logic;
+    LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- Status + Info TypE
+    LVL1_INVALID_TRG_IN        : in std_logic;
+
+    LVL1_TRG_TYPE_IN           : in std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_IN         : in std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_IN           : in std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_IN    : in std_logic_vector(23 downto 0);
+    LVL1_INT_TRG_NUMBER_IN     : in std_logic_vector(15 downto 0);
+
+    --Response from FEE        
+    FEE_TRG_RELEASE_OUT        : out std_logic;
+    FEE_TRG_STATUSBITS_OUT     : out std_logic_vector(31 downto 0);
+    FEE_DATA_OUT               : out std_logic_vector(31 downto 0);
+    FEE_DATA_WRITE_OUT         : out std_logic;
+    FEE_DATA_FINISHED_OUT      : out std_logic;
+    FEE_DATA_ALMOST_FULL_IN    : in  std_logic;
+
+    -- TRBNet RegIO Port for the slave bus
+    REGIO_ADDR_IN              : in    std_logic_vector(15 downto 0);
+    REGIO_DATA_IN              : in    std_logic_vector(31 downto 0);
+    REGIO_DATA_OUT             : out   std_logic_vector(31 downto 0);
+    REGIO_READ_ENABLE_IN       : in    std_logic;                    
+    REGIO_WRITE_ENABLE_IN      : in    std_logic;
+    REGIO_TIMEOUT_IN           : in    std_logic;
+    REGIO_DATAREADY_OUT        : out   std_logic;
+    REGIO_WRITE_ACK_OUT        : out   std_logic;
+    REGIO_NO_MORE_DATA_OUT     : out   std_logic;
+    REGIO_UNKNOWN_ADDR_OUT     : out   std_logic;
+    
+    -- Debug Signals
+    DEBUG_LINE_OUT             : out   std_logic_vector(15 downto 0)
+    );
+  
+end entity;
+
+
+architecture Behavioral of nXyter_FEE_board is
+
+-------------------------------------------------------------------------------
+-- Signals
+-------------------------------------------------------------------------------
+  -- Clock 256
+  signal clk_250_o             : std_logic;
+                               
+  -- Bus Handler
+  constant NUM_PORTS : integer := 11;
+
+  signal slv_read              : std_logic_vector(NUM_PORTS-1 downto 0);
+  signal slv_write             : std_logic_vector(NUM_PORTS-1 downto 0);
+  signal slv_no_more_data      : std_logic_vector(NUM_PORTS-1 downto 0);
+  signal slv_ack               : std_logic_vector(NUM_PORTS-1 downto 0);
+  signal slv_addr              : std_logic_vector(NUM_PORTS*16-1 downto 0);
+  signal slv_data_rd           : std_logic_vector(NUM_PORTS*32-1 downto 0);
+  signal slv_data_wr           : std_logic_vector(NUM_PORTS*32-1 downto 0);
+  signal slv_unknown_addr      : std_logic_vector(NUM_PORTS-1 downto 0);
+                               
+  -- TRB Register              
+  signal i2c_sm_reset_o        : std_logic;   
+  signal nx_ts_reset_1         : std_logic;
+  signal nx_ts_reset_2         : std_logic;
+  signal nx_ts_reset_o         : std_logic;
+  signal i2c_reg_reset_o       : std_logic;
+                               
+  -- NX Register Access        
+  signal i2c_lock              : std_logic;
+  signal i2c_command           : std_logic_vector(31 downto 0);
+  signal i2c_command_busy      : std_logic;
+  signal i2c_data              : std_logic_vector(31 downto 0);
+  signal spi_lock              : std_logic;
+  signal spi_command           : std_logic_vector(31 downto 0);
+  signal spi_command_busy      : std_logic;
+  signal spi_data              : std_logic_vector(31 downto 0);
+                               
+  -- SPI Interface ADC         
+  signal spi_sdi               : std_logic;
+  signal spi_sdo               : std_logic;        
+                               
+  -- Data Receiver             
+  signal adc_data_valid        : std_logic;
+  signal adc_new_data          : std_logic;
+                               
+  signal new_timestamp         : std_logic_vector(31 downto 0);
+  signal new_adc_data          : std_logic_vector(11 downto 0);
+  signal new_data              : std_logic;
+                               
+  -- Data Validate             
+  signal timestamp             : std_logic_vector(13 downto 0);
+  signal timestamp_channel_id  : std_logic_vector(6 downto 0);
+  signal timestamp_status      : std_logic_vector(2 downto 0);
+  signal adc_data              : std_logic_vector(11 downto 0);
+  signal data_valid            : std_logic;
+                               
+  signal nx_token_return       : std_logic;
+  signal nx_nomore_data        : std_logic;
+                               
+  -- Trigger Validate          
+  signal trigger_data          : std_logic_vector(31 downto 0);
+  signal trigger_data_clk      : std_logic;
+  signal event_buffer_clear    : std_logic;
+  signal trigger_validate_busy : std_logic;
+  signal validate_nomore_data  : std_logic;
+  
+  signal trigger_validate_fill : std_logic;
+  signal trigger_validate_bin  : std_logic_vector(6 downto 0);
+  
+  -- Event Buffer               
+  signal trigger_evt_busy      : std_logic;
+  signal fee_trg_statusbits_o  : std_logic_vector(31 downto 0);
+  signal fee_data_o            : std_logic_vector(31 downto 0);
+  signal fee_data_write_o      : std_logic;
+  signal fee_data_finished_o   : std_logic;
+  signal fee_almost_full_i     : std_logic;
+  
+  -- Trigger Handler
+  signal trigger               : std_logic;
+  signal timestamp_hold        : std_logic;
+  signal lvl2_trigger          : std_logic;
+  signal trigger_busy          : std_logic;
+  signal fast_clear            : std_logic;
+  signal nxyter_offline        : std_logic;
+  signal fee_trg_release_o     : std_logic;
+
+  -- FPGA Timestamp            
+  signal timestamp_trigger     : unsigned(11 downto 0);
+  signal nx_timestamp_sync     : std_logic;
+  
+  -- Trigger Generator
+  signal trigger_intern        : std_logic;
+  signal nx_testpulse_o        : std_logic;
+
+begin
+
+-------------------------------------------------------------------------------
+-- DEBUG
+-------------------------------------------------------------------------------
+--  DEBUG_LINE_OUT(0)            <= nx_testpulse_o; --CLK_IN;
+--  DEBUG_LINE_OUT(1)            <= NX_CLK128_IN;
+--  DEBUG_LINE_OUT(2)            <= ADC_SAMPLE_CLK_OUT;
+--  DEBUG_LINE_OUT(7 downto 3)  <= (others => '0');
+--  DEBUG_LINE_OUT(15 downto 8)  <= NX_TIMESTAMP_IN;
+--   DEBUG_LINE_OUT(4)            <= nx_new_timestamp;
+--   DEBUG_LINE_OUT(5)            <= timestamp_valid;
+--   DEBUG_LINE_OUT(6)            <= timestamp_hold;
+--   DEBUG_LINE_OUT(7)            <= nx_token_return;
+--   DEBUG_LINE_OUT(8)            <= nx_nomore_data;
+--   DEBUG_LINE_OUT(9)            <= trigger;
+--   DEBUG_LINE_OUT(10)           <= trigger_busy;
+--   DEBUG_LINE_OUT(11)           <= ts_data_clk;
+--   DEBUG_LINE_OUT(12)           <= data_fifo_reset;
+-- 
+--   DEBUG_LINE_OUT(14 downto 13) <= timestamp_status;
+--   DEBUG_LINE_OUT(15)           <= slv_ack(3);
+  
+--   DEBUG_LINE_OUT(0)            <= CLK_IN;
+--   DEBUG_LINE_OUT(1)            <= CLK_125_IN;
+--   DEBUG_LINE_OUT(2)            <= clk_250_o;
+--   DEBUG_LINE_OUT(3)            <= NX_CLK128_IN;
+--   DEBUG_LINE_OUT(4)            <= nx_timestamp(0);
+--   DEBUG_LINE_OUT(15 downto 5)  <= (others => '0');
+  --DEBUG_LINE_OUT(5)            <= timestamp_valid;
+  --DEBUG_LINE_OUT(6)            <= nx_token_return;
+  --DEBUG_LINE_OUT(7)            <= nx_nomore_data;
+
+--  DEBUG_LINE_OUT(0)            <= NX_CLK128_IN;
+--  DEBUG_LINE_OUT(8 downto 1)   <= NX_TIMESTAMP_IN;
+--  DEBUG_LINE_OUT(13 downto 9)  <= (others => '0');
+--  DEBUG_LINE_OUT(15)           <= CLK_IN;
+--  DEBUG_LINE_OUT(5)            <= '0';
+--  DEBUG_LINE_OUT(6)            <= '0';
+--  DEBUG_LINE_OUT(7)            <= '0';
+--  
+--  
+--  DEBUG_LINE_OUT(8)            <= ADC_FCLK_IN;        
+--  DEBUG_LINE_OUT(10)           <= ADC_SC_CLK32_OUT;
+--  DEBUG_LINE_OUT(11)           <= ADC_A_IN;
+--  DEBUG_LINE_OUT(12)           <= ADC_B_IN;
+--  DEBUG_LINE_OUT(13)           <= ADC_NX_IN;  
+--  DEBUG_LINE_OUT(14)           <= ADC_D_IN;  
+--  DEBUG_LINE_OUT(15)           <= '0';
+  
+--  DEBUG_LINE_OUT(15 downto 8) <= slv_read(9 downto 2);
+-------------------------------------------------------------------------------
+-- Port Maps
+-------------------------------------------------------------------------------
+
+  THE_BUS_HANDLER: trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER         => NUM_PORTS,
+
+      PORT_ADDRESSES      => ( 0 => x"0100",    -- Control Register Handler
+                               1 => x"0040",    -- I2C Master
+                               2 => x"0500",    -- Data Receiver
+                               3 => x"0600",    -- Data Buffer
+                               4 => x"0060",    -- SPI Master
+                               5 => x"0140",    -- Trigger Generator
+                               6 => x"0120",    -- Data Validate
+                               7 => x"0160",    -- Trigger Handler
+                               8 => x"0180",    -- Trigger Validate
+                               9 => x"0200",    -- NX Register Setup
+                               10 => x"0800",   -- NX Histograms
+                               others => x"0000"),
+
+      PORT_ADDR_MASK      => ( 0 => 3,          -- Control Register Handler
+                               1 => 0,          -- I2C master
+                               2 => 3,          -- Data Receiver
+                               3 => 3,          -- Data Buffer
+                               4 => 0,          -- SPI Master
+                               5 => 3,          -- Trigger Generator
+                               6 => 4,          -- Data Validate
+                               7 => 1,          -- Trigger Handler
+                               8 => 4,          -- Trigger Validate
+                               9 => 8,          -- NX Register Setup
+                               10 => 8,         -- NX Histograms
+                               others => 0),
+
+      PORT_MASK_ENABLE           => 1
+      )
+    port map(
+      CLK                        => CLK_IN,
+      RESET                      => RESET_IN,
+                                 
+      DAT_ADDR_IN                => REGIO_ADDR_IN,
+      DAT_DATA_IN                => REGIO_DATA_IN,
+      DAT_DATA_OUT               => REGIO_DATA_OUT,
+      DAT_READ_ENABLE_IN         => REGIO_READ_ENABLE_IN,
+      DAT_WRITE_ENABLE_IN        => REGIO_WRITE_ENABLE_IN,
+      DAT_TIMEOUT_IN             => REGIO_TIMEOUT_IN,
+      DAT_DATAREADY_OUT          => REGIO_DATAREADY_OUT,
+      DAT_WRITE_ACK_OUT          => REGIO_WRITE_ACK_OUT,
+      DAT_NO_MORE_DATA_OUT       => REGIO_NO_MORE_DATA_OUT,
+      DAT_UNKNOWN_ADDR_OUT       => REGIO_UNKNOWN_ADDR_OUT,
+                                 
+      -- Control Registers       
+      BUS_READ_ENABLE_OUT        => slv_read,
+      BUS_WRITE_ENABLE_OUT       => slv_write,
+      BUS_DATA_OUT               => slv_data_wr,
+      BUS_DATA_IN                => slv_data_rd,
+      BUS_ADDR_OUT               => slv_addr,
+      BUS_TIMEOUT_OUT            => open,
+      BUS_DATAREADY_IN           => slv_ack,
+      BUS_WRITE_ACK_IN           => slv_ack,
+      BUS_NO_MORE_DATA_IN        => slv_no_more_data,
+      BUS_UNKNOWN_ADDR_IN        => slv_unknown_addr,
+
+      -- DEBUG
+      STAT_DEBUG          => open
+      );
+
+
+-------------------------------------------------------------------------------
+-- Registers
+-------------------------------------------------------------------------------
+  nxyter_registers_1: nxyter_registers
+    port map (
+      CLK_IN                 => CLK_IN,
+      RESET_IN               => RESET_IN,
+                             
+      SLV_READ_IN            => slv_read(0),
+      SLV_WRITE_IN           => slv_write(0),
+      SLV_DATA_OUT           => slv_data_rd(0*32+31 downto 0*32),
+      SLV_DATA_IN            => slv_data_wr(0*32+31 downto 0*32),
+      SLV_ADDR_IN            => slv_addr(0*16+15 downto 0*16),
+      SLV_ACK_OUT            => slv_ack(0),
+      SLV_NO_MORE_DATA_OUT   => slv_no_more_data(0),
+      SLV_UNKNOWN_ADDR_OUT   => slv_unknown_addr(0),
+      I2C_SM_RESET_OUT       => i2c_sm_reset_o,
+      I2C_REG_RESET_OUT      => i2c_reg_reset_o,
+      NX_TS_RESET_OUT        => nx_ts_reset_1,
+      OFFLINE_OUT            => nxyter_offline,
+      --DEBUG_OUT              => DEBUG_LINE_OUT
+      DEBUG_OUT              => open
+      );
+
+  nx_register_setup_1: nx_setup
+    port map (
+      CLK_IN               => CLK_IN,
+      RESET_IN             => RESET_IN,
+      I2C_COMMAND_OUT      => i2c_command,
+      I2C_COMMAND_BUSY_IN  => i2c_command_busy,
+      I2C_DATA_IN          => i2c_data,
+      I2C_LOCK_OUT         => i2c_lock,
+      SPI_COMMAND_OUT      => spi_command,
+      SPI_COMMAND_BUSY_IN  => spi_command_busy,
+      SPI_DATA_IN          => spi_data,
+      SPI_LOCK_OUT         => spi_lock,
+      SLV_READ_IN          => slv_read(9),
+      SLV_WRITE_IN         => slv_write(9),
+      SLV_DATA_OUT         => slv_data_rd(9*32+31 downto 9*32),
+      SLV_DATA_IN          => slv_data_wr(9*32+31 downto 9*32),
+      SLV_ADDR_IN          => slv_addr(9*16+15 downto 9*16),
+      SLV_ACK_OUT          => slv_ack(9),
+      SLV_NO_MORE_DATA_OUT => slv_no_more_data(9),
+      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9),
+      --DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+  
+-------------------------------------------------------------------------------
+-- I2C master block for accessing the nXyter
+-------------------------------------------------------------------------------
+
+  nx_i2c_master_1: nx_i2c_master
+    generic map (
+      I2C_SPEED => x"3e8"
+      )
+    port map (
+      CLK_IN                => CLK_IN,
+      RESET_IN              => RESET_IN,
+      SDA_INOUT             => I2C_SDA_INOUT,
+      SCL_INOUT             => I2C_SCL_INOUT,
+      INTERNAL_COMMAND_IN   => i2c_command,
+      COMMAND_BUSY_OUT      => i2c_command_busy,
+      I2C_DATA_OUT          => i2c_data,
+      I2C_LOCK_IN           => i2c_lock,
+      SLV_READ_IN           => slv_read(1),
+      SLV_WRITE_IN          => slv_write(1),
+      SLV_DATA_OUT          => slv_data_rd(1*32+31 downto 1*32),
+      SLV_DATA_IN           => slv_data_wr(1*32+31 downto 1*32),
+      SLV_ACK_OUT           => slv_ack(1), 
+      SLV_NO_MORE_DATA_OUT  => slv_no_more_data(1),
+      SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(1),
+      --DEBUG_OUT          => DEBUG_LINE_OUT
+      DEBUG_OUT             => open
+      );
+
+-------------------------------------------------------------------------------
+-- SPI master block to access the ADC
+-------------------------------------------------------------------------------
+  
+  adc_spi_master_1: adc_spi_master
+    generic map (
+      SPI_SPEED => x"32"
+      )
+    port map (
+      CLK_IN               => CLK_IN,
+      RESET_IN             => RESET_IN,
+      SCLK_OUT             => SPI_SCLK_OUT,
+      SDIO_INOUT           => SPI_SDIO_INOUT,
+      CSB_OUT              => SPI_CSB_OUT,
+      INTERNAL_COMMAND_IN  => spi_command,
+      COMMAND_BUSY_OUT     => spi_command_busy,
+      SPI_DATA_OUT         => spi_data,
+      SPI_LOCK_IN          => spi_lock,
+      SLV_READ_IN          => slv_read(4),
+      SLV_WRITE_IN         => slv_write(4),
+      SLV_DATA_OUT         => slv_data_rd(4*32+31 downto 4*32),
+      SLV_DATA_IN          => slv_data_wr(4*32+31 downto 4*32),
+      SLV_ACK_OUT          => slv_ack(4), 
+      SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), 
+      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
+      -- DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+
+-------------------------------------------------------------------------------
+-- FPGA Timestamp
+-------------------------------------------------------------------------------
+  
+  nx_fpga_timestamp_1: nx_fpga_timestamp
+    port map (
+      CLK_IN                => CLK_NX_IN,
+      RESET_IN              => RESET_IN,
+      TIMESTAMP_SYNC_IN     => nx_ts_reset_o,
+      TRIGGER_IN            => timestamp_hold,
+      TIMESTAMP_OUT         => timestamp_trigger,
+      NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync,
+      SLV_READ_IN           => open,
+      SLV_WRITE_IN          => open,
+      SLV_DATA_OUT          => open,
+      SLV_DATA_IN           => open,
+      SLV_ACK_OUT           => open,
+      SLV_NO_MORE_DATA_OUT  => open,
+      SLV_UNKNOWN_ADDR_OUT  => open,
+      -- DEBUG_OUT             => DEBUG_LINE_OUT
+      DEBUG_OUT             => open
+      );
+
+-------------------------------------------------------------------------------
+-- Trigger Handler
+-------------------------------------------------------------------------------
+
+  nx_trigger_handler_1: nx_trigger_handler
+    port map (
+      CLK_IN                     => CLK_IN,
+      RESET_IN                   => RESET_IN,
+      NXYTER_OFFLINE_IN          => nxyter_offline,
+
+      LVL1_TRG_DATA_VALID_IN     => LVL1_TRG_DATA_VALID_IN,
+      LVL1_VALID_TIMING_TRG_IN   => LVL1_VALID_TIMING_TRG_IN,
+      LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN,
+      LVL1_INVALID_TRG_IN        => LVL1_INVALID_TRG_IN,
+
+      LVL1_TRG_TYPE_IN           => LVL1_TRG_TYPE_IN,
+      LVL1_TRG_NUMBER_IN         => LVL1_TRG_NUMBER_IN,
+      LVL1_TRG_CODE_IN           => LVL1_TRG_CODE_IN,
+      LVL1_TRG_INFORMATION_IN    => LVL1_TRG_INFORMATION_IN,
+      LVL1_INT_TRG_NUMBER_IN     => LVL1_INT_TRG_NUMBER_IN,
+
+      FEE_TRG_RELEASE_OUT        => FEE_TRG_RELEASE_OUT,
+      FEE_TRG_STATUSBITS_OUT     => FEE_TRG_STATUSBITS_OUT,
+
+      INTERNAL_TRIGGER_IN        => trigger_intern,
+
+      TRIGGER_VALIDATE_BUSY_IN   => trigger_validate_busy,
+      LVL2_TRIGGER_BUSY_IN       => trigger_evt_busy,
+      
+      VALIDATE_TRIGGER_OUT       => trigger,
+      TIMESTAMP_HOLD_OUT         => timestamp_hold,
+      LVL2_TRIGGER_OUT           => lvl2_trigger,
+      EVENT_BUFFER_CLEAR_OUT     => event_buffer_clear,
+      FAST_CLEAR_OUT             => fast_clear,
+      TRIGGER_BUSY_OUT           => trigger_busy,
+
+      SLV_READ_IN                => slv_read(7),
+      SLV_WRITE_IN               => slv_write(7),
+      SLV_DATA_OUT               => slv_data_rd(7*32+31 downto 7*32),
+      SLV_DATA_IN                => slv_data_wr(7*32+31 downto 7*32),
+      SLV_ADDR_IN                => slv_addr(7*16+15 downto 7*16),
+      SLV_ACK_OUT                => slv_ack(7),
+      SLV_NO_MORE_DATA_OUT       => slv_no_more_data(7),
+      SLV_UNKNOWN_ADDR_OUT       => slv_unknown_addr(7),
+
+      --DEBUG_OUT                  => DEBUG_LINE_OUT
+      DEBUG_OUT                  => open
+      );
+
+-------------------------------------------------------------------------------
+-- NX Trigger Generator
+-------------------------------------------------------------------------------
+
+  nx_trigger_generator_1: nx_trigger_generator
+    port map (
+      CLK_IN               => CLK_IN,
+      RESET_IN             => RESET_IN,
+      TRIGGER_OUT          => trigger_intern,
+      TS_RESET_OUT         => nx_ts_reset_2,
+      TESTPULSE_OUT        => nx_testpulse_o,
+      SLV_READ_IN          => slv_read(5),
+      SLV_WRITE_IN         => slv_write(5),
+      SLV_DATA_OUT         => slv_data_rd(5*32+31 downto 5*32),
+      SLV_DATA_IN          => slv_data_wr(5*32+31 downto 5*32),
+      SLV_ADDR_IN          => slv_addr(5*16+15 downto 5*16),
+      SLV_ACK_OUT          => slv_ack(5),
+      SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
+      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
+      --DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+
+-------------------------------------------------------------------------------
+-- nXyter Data Receiver
+-------------------------------------------------------------------------------
+
+  nx_data_receiver_1: nx_data_receiver
+    port map (
+      CLK_IN               => CLK_IN,
+      RESET_IN             => RESET_IN,
+
+      NX_TIMESTAMP_CLK_IN  => NX_CLK128_IN,
+      NX_TIMESTAMP_IN      => NX_TIMESTAMP_IN,
+
+      ADC_CLK_DAT_IN       => CLK_ADC_IN,
+      ADC_FCLK_IN          => ADC_FCLK_IN,
+      ADC_DCLK_IN          => ADC_DCLK_IN, 
+      ADC_SAMPLE_CLK_OUT   => ADC_SAMPLE_CLK_OUT,
+      ADC_A_IN             => ADC_A_IN,
+      ADC_B_IN             => ADC_B_IN,
+      ADC_NX_IN            => ADC_NX_IN, 
+      ADC_D_IN             => ADC_D_IN,
+
+      NX_TIMESTAMP_OUT     => new_timestamp,
+      ADC_DATA_OUT         => new_adc_data,
+      NEW_DATA_OUT         => new_data,
+
+      SLV_READ_IN          => slv_read(2),                      
+      SLV_WRITE_IN         => slv_write(2),                     
+      SLV_DATA_OUT         => slv_data_rd(2*32+31 downto 2*32), 
+      SLV_DATA_IN          => slv_data_wr(2*32+31 downto 2*32), 
+      SLV_ADDR_IN          => slv_addr(2*16+15 downto 2*16),    
+      SLV_ACK_OUT          => slv_ack(2),                       
+      SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),              
+      SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),              
+      --DEBUG_OUT            => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+  
+-------------------------------------------------------------------------------
+-- Timestamp Decoder and Valid Data Filter
+-------------------------------------------------------------------------------
+
+  nx_data_validate_1: nx_data_validate
+    port map (
+      CLK_IN                => CLK_IN,
+      RESET_IN              => RESET_IN,
+      
+      NX_TIMESTAMP_IN       => new_timestamp,
+      ADC_DATA_IN           => new_adc_data,
+      NEW_DATA_IN           => new_data,
+
+      TIMESTAMP_OUT         => timestamp,
+      CHANNEL_OUT           => timestamp_channel_id,
+      TIMESTAMP_STATUS_OUT  => timestamp_status,
+      ADC_DATA_OUT          => adc_data,
+      DATA_VALID_OUT        => data_valid,
+      
+      NX_TOKEN_RETURN_OUT   => nx_token_return,
+      NX_NOMORE_DATA_OUT    => nx_nomore_data,
+      
+      SLV_READ_IN           => slv_read(6),
+      SLV_WRITE_IN          => slv_write(6),
+      SLV_DATA_OUT          => slv_data_rd(6*32+31 downto 6*32),
+      SLV_DATA_IN           => slv_data_wr(6*32+31 downto 6*32),
+      SLV_ADDR_IN           => slv_addr(6*16+15 downto 6*16),
+      SLV_ACK_OUT           => slv_ack(6),
+      SLV_NO_MORE_DATA_OUT  => slv_no_more_data(6),
+      SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(6),
+      --DEBUG_OUT             => DEBUG_LINE_OUT
+      DEBUG_OUT             => open
+      );
+
+-------------------------------------------------------------------------------
+-- NX Trigger Validate
+-------------------------------------------------------------------------------
+
+  nx_trigger_validate_1: nx_trigger_validate
+    port map (
+      CLK_IN                 => CLK_IN,
+      RESET_IN               => RESET_IN,
+      
+      DATA_CLK_IN            => data_valid,
+      TIMESTAMP_IN           => timestamp,
+      CHANNEL_IN             => timestamp_channel_id,
+      TIMESTAMP_STATUS_IN    => timestamp_status,
+      ADC_DATA_IN            => adc_data,
+      NX_TOKEN_RETURN_IN     => nx_token_return,
+      NX_NOMORE_DATA_IN      => nx_nomore_data,
+
+      TRIGGER_IN             => trigger,
+      FAST_CLEAR_IN          => fast_clear,
+      TRIGGER_BUSY_OUT       => trigger_validate_busy,
+      TIMESTAMP_REF_IN       => timestamp_trigger,
+      
+      DATA_OUT               => trigger_data,
+      DATA_CLK_OUT           => trigger_data_clk,
+      NOMORE_DATA_OUT        => validate_nomore_data,
+
+      HISTOGRAM_FILL_OUT     => trigger_validate_fill,
+      HISTOGRAM_BIN_OUT      => trigger_validate_bin,
+      
+      SLV_READ_IN            => slv_read(8),
+      SLV_WRITE_IN           => slv_write(8),
+      SLV_DATA_OUT           => slv_data_rd(8*32+31 downto 8*32),
+      SLV_DATA_IN            => slv_data_wr(8*32+31 downto 8*32),
+      SLV_ADDR_IN            => slv_addr(8*16+15 downto 8*16),
+      SLV_ACK_OUT            => slv_ack(8),
+      SLV_NO_MORE_DATA_OUT   => slv_no_more_data(8),
+      SLV_UNKNOWN_ADDR_OUT   => slv_unknown_addr(8),
+      DEBUG_OUT              => DEBUG_LINE_OUT
+      --DEBUG_OUT              => open
+      );
+
+-------------------------------------------------------------------------------
+-- Data Buffer FIFO
+-------------------------------------------------------------------------------
+
+  nx_event_buffer_1: nx_event_buffer
+    generic map (
+      BOARD_ID => BOARD_ID
+      )
+    port map (
+      CLK_IN                     => CLK_IN,
+      RESET_IN                   => RESET_IN,
+      RESET_DATA_BUFFER_IN       => event_buffer_clear,
+      NXYTER_OFFLINE_IN          => nxyter_offline,
+
+      DATA_IN                    => trigger_data,
+      DATA_CLK_IN                => trigger_data_clk,
+      EVT_NOMORE_DATA_IN         => validate_nomore_data,
+
+      LVL2_TRIGGER_IN            => lvl2_trigger,
+      FAST_CLEAR_IN              => fast_clear,
+      TRIGGER_BUSY_OUT           => trigger_evt_busy,
+
+      FEE_DATA_OUT               => FEE_DATA_OUT,
+      FEE_DATA_WRITE_OUT         => FEE_DATA_WRITE_OUT,
+      FEE_DATA_FINISHED_OUT      => FEE_DATA_FINISHED_OUT,
+      FEE_DATA_ALMOST_FULL_IN    => FEE_DATA_ALMOST_FULL_IN,
+
+      SLV_READ_IN                => slv_read(3),
+      SLV_WRITE_IN               => slv_write(3),
+      SLV_DATA_OUT               => slv_data_rd(3*32+31 downto 3*32),
+      SLV_DATA_IN                => slv_data_wr(3*32+31 downto 3*32),
+      SLV_ADDR_IN                => slv_addr(3*16+15 downto 3*16),
+      SLV_ACK_OUT                => slv_ack(3),
+      SLV_NO_MORE_DATA_OUT       => slv_no_more_data(3),
+      SLV_UNKNOWN_ADDR_OUT       => slv_unknown_addr(3),
+
+      --DEBUG_OUT                  => DEBUG_LINE_OUT
+      DEBUG_OUT            => open
+      );
+
+  nx_histograms_1: nx_histograms
+    generic map (
+      NUM_BINS => 7
+      )
+    port map (
+      CLK_IN                      => CLK_IN,
+      RESET_IN                    => RESET_IN,
+                                  
+      RESET_HISTS_IN              => open,
+      CHANNEL_STAT_FILL_IN        => trigger_validate_fill,
+      CHANNEL_ID_IN               => trigger_validate_bin,
+                                  
+      SLV_READ_IN                 => slv_read(10),
+      SLV_WRITE_IN                => slv_write(10),
+      SLV_DATA_OUT                => slv_data_rd(10*32+31 downto 10*32),
+      SLV_DATA_IN                 => slv_data_wr(10*32+31 downto 10*32),
+      SLV_ADDR_IN                 => slv_addr(10*16+15 downto 10*16),
+      SLV_ACK_OUT                 => slv_ack(10),
+      SLV_NO_MORE_DATA_OUT        => slv_no_more_data(10),
+      SLV_UNKNOWN_ADDR_OUT        => slv_unknown_addr(10),
+
+      --DEBUG_OUT                   => DEBUG_LINE_OUT
+      DEBUG_OUT                   => open
+      );
+  
+-------------------------------------------------------------------------------
+-- nXyter Signals
+-------------------------------------------------------------------------------
+  nx_ts_reset_o     <= nx_ts_reset_1 or nx_ts_reset_2; 
+  NX_RESET_OUT      <= not nx_ts_reset_o;
+  NX_TESTPULSE_OUT  <= nx_testpulse_o;
+
+-------------------------------------------------------------------------------
+-- I2C Signals
+-------------------------------------------------------------------------------
+
+  I2C_SM_RESET_OUT  <= not i2c_sm_reset_o;
+  I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
+  
+-------------------------------------------------------------------------------
+-- END
+-------------------------------------------------------------------------------
+
+end Behavioral;
diff --git a/mupix/source/nxyter_registers.vhd b/mupix/source/nxyter_registers.vhd
new file mode 100644 (file)
index 0000000..9f98ad7
--- /dev/null
@@ -0,0 +1,224 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nxyter_registers is\r
+  port(\r
+    CLK_IN               : in  std_logic;\r
+    RESET_IN             : in  std_logic;\r
+    \r
+    -- Slave bus         \r
+    SLV_READ_IN          : in  std_logic;\r
+    SLV_WRITE_IN         : in  std_logic;\r
+    SLV_DATA_OUT         : out std_logic_vector(31 downto 0);\r
+    SLV_DATA_IN          : in  std_logic_vector(31 downto 0);\r
+    SLV_ADDR_IN          : in  std_logic_vector(15 downto 0);\r
+    SLV_ACK_OUT          : out std_logic;\r
+    SLV_NO_MORE_DATA_OUT : out std_logic;\r
+    SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+\r
+    -- Signals\r
+    I2C_SM_RESET_OUT     : out std_logic;\r
+    I2C_REG_RESET_OUT    : out std_logic;\r
+    NX_TS_RESET_OUT      : out std_logic;\r
+    OFFLINE_OUT          : out std_logic;\r
+    \r
+    DEBUG_OUT            : out std_logic_vector(15 downto 0)\r
+    );\r
+end entity;\r
+\r
+architecture Behavioral of nxyter_registers is\r
+\r
+  signal slv_data_out_o     : std_logic_vector(31 downto 0);\r
+  signal slv_no_more_data_o : std_logic;\r
+  signal slv_unknown_addr_o : std_logic;\r
+  signal slv_ack_o          : std_logic;\r
+\r
+\r
+  -- I2C Reset\r
+  signal i2c_sm_reset_start  : std_logic;\r
+  signal i2c_reg_reset_start : std_logic;\r
+  signal nx_ts_reset_start   : std_logic;\r
+  \r
+  signal i2c_sm_reset_o      : std_logic;\r
+  signal i2c_reg_reset_o     : std_logic;\r
+  signal nx_ts_reset_o       : std_logic;\r
+  signal offline_o           : std_logic;\r
+\r
+  type STATES is (S_IDLE,\r
+                  S_I2C_SM_RESET,\r
+                  S_I2C_SM_RESET_WAIT,\r
+                  S_I2C_REG_RESET,\r
+                  S_I2C_REG_RESET_WAIT,\r
+                  S_NX_TS_RESET\r
+                  );\r
+  \r
+  signal STATE : STATES;\r
+  \r
+  -- Wait Timer\r
+  signal wait_timer_init    : unsigned(7 downto 0);\r
+  signal wait_timer_done    : std_logic;\r
+  \r
+begin\r
+\r
+  DEBUG_OUT(0) <=  I2C_SM_RESET_OUT ;\r
+  DEBUG_OUT(1) <=  I2C_REG_RESET_OUT;\r
+  DEBUG_OUT(2) <=  NX_TS_RESET_OUT;\r
+\r
+  DEBUG_OUT(15 downto 3) <= (others => '0');\r
+  \r
+  nx_timer_1: nx_timer\r
+    generic map (\r
+      CTR_WIDTH => 8\r
+      )\r
+    port map (\r
+      CLK_IN         => CLK_IN,\r
+      RESET_IN       => RESET_IN,\r
+      TIMER_START_IN => wait_timer_init,\r
+      TIMER_DONE_OUT => wait_timer_done\r
+      );\r
+  \r
+  -----------------------------------------------------------------------------\r
+  -- I2C SM Reset\r
+  -----------------------------------------------------------------------------\r
+\r
+  PROC_I2C_SM_RESET: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        wait_timer_init    <= (others => '0');\r
+        i2c_sm_reset_o     <= '0';\r
+        i2c_reg_reset_o    <= '0';\r
+        nx_ts_reset_o      <= '0';\r
+        STATE              <= S_IDLE;\r
+      else\r
+        i2c_sm_reset_o     <= '0';\r
+        i2c_reg_reset_o    <= '0';\r
+        nx_ts_reset_o      <= '0';\r
+        wait_timer_init    <= (others => '0');\r
+        \r
+        case STATE is\r
+          when S_IDLE =>\r
+            if (i2c_sm_reset_start = '1') then\r
+              STATE          <= S_I2C_SM_RESET;\r
+            elsif (i2c_reg_reset_start = '1') then\r
+              STATE          <= S_I2C_REG_RESET;\r
+            elsif (nx_ts_reset_start = '1') then\r
+              STATE          <= S_NX_TS_RESET;\r
+            else\r
+              STATE          <= S_IDLE;\r
+            end if;\r
+            \r
+          when S_I2C_SM_RESET =>\r
+            i2c_sm_reset_o   <= '1';\r
+            wait_timer_init  <= x"8f";\r
+            STATE            <= S_I2C_SM_RESET_WAIT;\r
+\r
+          when S_I2C_SM_RESET_WAIT =>\r
+            i2c_sm_reset_o   <= '1';\r
+            if (wait_timer_done = '0') then\r
+              STATE          <= S_I2C_SM_RESET_WAIT;\r
+            else\r
+              STATE          <= S_IDLE;\r
+            end if;\r
+\r
+          when S_I2C_REG_RESET =>\r
+            i2c_reg_reset_o  <= '1';\r
+            wait_timer_init  <= x"8f";\r
+            STATE            <= S_I2C_REG_RESET_WAIT;\r
+\r
+          when S_I2C_REG_RESET_WAIT =>\r
+            i2c_reg_reset_o  <= '1';\r
+            if (wait_timer_done = '0') then\r
+              STATE          <= S_I2C_REG_RESET_WAIT;\r
+            else\r
+              STATE          <= S_IDLE;\r
+            end if;\r
+\r
+          when S_NX_TS_RESET =>\r
+            nx_ts_reset_o    <= '1';\r
+            STATE            <= S_IDLE;\r
+\r
+        end case;\r
+      end if;\r
+    end if;\r
+    \r
+  end process PROC_I2C_SM_RESET;\r
+\r
+  -----------------------------------------------------------------------------\r
+  -- Slave Bus\r
+  -----------------------------------------------------------------------------\r
+  \r
+  PROC_NX_REGISTERS: process(CLK_IN)\r
+  begin\r
+    if( rising_edge(CLK_IN) ) then\r
+      if( RESET_IN = '1' ) then\r
+        slv_data_out_o      <= (others => '0');\r
+        slv_no_more_data_o  <= '0';\r
+        slv_unknown_addr_o  <= '0';\r
+        slv_ack_o           <= '0';\r
+        \r
+        i2c_sm_reset_start  <= '0';\r
+        i2c_reg_reset_start <= '0';\r
+        nx_ts_reset_start   <= '0';\r
+        offline_o           <= '1';\r
+      else\r
+        slv_ack_o           <= '1';\r
+        slv_unknown_addr_o  <= '0';\r
+        slv_no_more_data_o  <= '0';\r
+        slv_data_out_o      <= (others => '0');    \r
+        i2c_sm_reset_start  <= '0';\r
+        i2c_reg_reset_start <= '0';\r
+        nx_ts_reset_start   <= '0';\r
+        \r
+        if (SLV_WRITE_IN  = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0000" =>\r
+              i2c_sm_reset_start          <= '1';\r
+\r
+            when x"0001" =>               \r
+              i2c_reg_reset_start         <= '1';\r
+\r
+            when x"0002" =>               \r
+              nx_ts_reset_start           <= '1';\r
+\r
+            when x"0003" =>               \r
+              offline_o                   <= SLV_DATA_IN(0);\r
+                                          \r
+            when others =>                \r
+              slv_unknown_addr_o          <= '1';\r
+              slv_ack_o                   <= '0';\r
+          end case;\r
+          \r
+        elsif (SLV_READ_IN = '1') then\r
+          case SLV_ADDR_IN is\r
+            when x"0003" =>\r
+              slv_data_out_o(0)           <= offline_o;\r
+              slv_data_out_o(31 downto 1) <= (others => '0');\r
+\r
+            when others =>\r
+              slv_unknown_addr_o          <= '1';\r
+              slv_ack_o                   <= '0';\r
+          end case;\r
+\r
+        else\r
+          slv_ack_o <= '0';\r
+        end if;\r
+      end if;\r
+    end if;           \r
+  end process PROC_NX_REGISTERS;\r
+\r
+-- Output Signals\r
+  SLV_DATA_OUT         <= slv_data_out_o;    \r
+  SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+  SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+  SLV_ACK_OUT          <= slv_ack_o;          \r
+\r
+  I2C_SM_RESET_OUT     <= i2c_sm_reset_o;\r
+  I2C_REG_RESET_OUT    <= i2c_reg_reset_o;\r
+  NX_TS_RESET_OUT      <= nx_ts_reset_o;\r
+  OFFLINE_OUT          <= offline_o;\r
+end Behavioral;\r
diff --git a/mupix/source/pulse_to_level.vhd b/mupix/source/pulse_to_level.vhd
new file mode 100644 (file)
index 0000000..568d4fa
--- /dev/null
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use nxyter_components.all;
+
+entity pulse_to_level is
+  generic (
+    NUM_CYCLES : unsigned(4 downto 0) := "11111"
+    );
+  port (
+    CLK_IN        : in  std_logic;  
+    RESET_IN      : in  std_logic;
+    
+    PULSE_IN      : in  std_logic;  
+    LEVEL_OUT     : out std_logic
+    );
+
+end entity;
+
+architecture Behavioral of pulse_to_level is
+
+  signal start_timer  : unsigned(4 downto 0);
+  signal timer_done   : std_logic;
+  signal level_o      : std_logic;
+
+  type STATES is (IDLE,
+                  WAIT_TIMER
+                );
+  signal STATE : STATES;
+  
+begin
+
+  nx_timer_1: nx_timer
+    generic map (
+      CTR_WIDTH => 5
+      )
+    port map (
+      CLK_IN          => CLK_IN,
+      RESET_IN        => RESET_IN,
+      TIMER_START_IN  => start_timer,
+      TIMER_DONE_OUT  => timer_done
+      );
+  
+  PROC_CONVERT: process(CLK_IN)
+  begin
+    if( rising_edge(CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        start_timer  <= (others => '0');
+        level_o      <= '0';
+        STATE        <= IDLE;
+      else
+        level_o <= '0';
+        start_timer  <= (others => '0');
+
+        case STATE is
+
+          when IDLE =>
+            if (PULSE_IN = '1') then
+              level_o     <= '1';
+              start_timer <= NUM_CYCLES;
+              STATE <= WAIT_TIMER;
+            else
+              STATE <= IDLE;
+            end if;
+
+          when WAIT_TIMER =>
+            level_o     <= '1';
+            if (timer_done = '1') then
+              STATE <= IDLE;
+            else
+              STATE <= WAIT_TIMER;
+            end if;
+
+           when others => null;
+
+        end case;
+      end if;
+    end if;
+  end process PROC_CONVERT;
+
+  LEVEL_OUT <= level_o;
+    
+end Behavioral;
diff --git a/mupix/source/registers.txt b/mupix/source/registers.txt
new file mode 100644 (file)
index 0000000..8c5e9a0
--- /dev/null
@@ -0,0 +1,73 @@
+-- Control Register
+0x8100 :  w    w: reset I2C State Machine
+0x8101 :  w    w: reset I2C all Register
+0x8102 :  w    w: Reset and Sync Timestamps (nXyter and FPGA)
+0x8103 :  r/w  Put nxyter into offline mode 
+
+-- NX Data Validate
+0x8120 :  rw   Invalid Frame Counter (16 bit) / w: clear all counters
+0x8121 :  r    Overflow Counter (16 bit)
+0x8122 :  r    Pileup Counter (16 bit)
+0x8123 :  r    Parity Error Counter (16 bit)
+0x8124 :  r    Trigger Rate (in kHz)
+
+-- NX Trigger Validate
+0x8180 :  r/w  Readout Mode (0:Ref + valid + window, 1: Ref + Valid 
+                             3: Raw and TimeStamp + valid,
+                             4: Raw,  5: Raw + Valid )
+0x8181 :  r/w  Trigger Window Delay (12 bit, in 3.9ns) 
+0x8182 :  r/w  Trigger Window Width (12 bit, in 3.9ns)
+0x8183 :  r/w  Readout Time Max (12 bit, in 10ns)
+0x8184 :  r    Busy Time Counter (12 bit, in 10ns)
+
+0x8185 :  r    done counter
+0x8186 :  r    done counter
+0x8187 :  r    done counter
+0x8188 :  r    done counter
+
+-- Trigger Generator
+0x8140 :  w    If writing just start trigger cycle, keep current setting
+0x8141 :  r/w  Bit 15-0 : periodic time (in 10ns) 
+0x8142 :  r/w  Bit0 7-0 : number of triggers to be sent consecutive
+0x8143 :  r/w  Bit 15-0 : Length of trigger pulse (in 10ns), if 0: skip it
+0x8144 :  r/w  Bit0     : 1: send timestamp-reset before trigger 
+
+-- Trigger Handler
+0x8160 :  r/w  Bit 15-0 : Delay Timestamp Hold  signal (8bit, 10ns)
+
+-- NX Data Receiver
+0x8500 :  r    current Timestamp FIFO value
+0x8501 :  r/w  r: FIFO Status 
+                                0: fifo_full
+                                1: fifo_empty
+                                2: fifo_almost_empty
+                 4..29: ignore
+                               31: nx_frame_synced
+               w: pll reset
+0x8502 :  r/w  r: Resync Counter(12bit)
+               w: clear Resync Counter    
+0x8503 :  r/w  r: Parity Error Counter (12bit)
+               w: clear Parity Error Counter
+0x8504 :  r/w  FIFO Delay, i.e. Trigger Delay (6Bit, in 31.25ns, range 2..60)
+                default: 8
+0x8505 :  r/w  ADC CLK Delay 4ns steps (3Bit: range 0..7)
+               0:  4ns after frame_valid
+               1:  8ns -------"---------
+               ......  -------"---------
+               6: 28ns -------"--------- 
+               7: 32ns -------"--------- <= this shoud be correct 
+                                            i.e. 2ns before new frame clock
+0x8506 :  r    current ADC FIFO value
+
+-- Event Data Buffer
+0x8600 :  r    read FIFO buffer
+0x8601 :  r    FIFO write counter
+0x8602 :  r    FIFO flush counter
+0x8603 :  r/w  r: read FIFO status
+               w: enable/disable FIFO write
+
+-- I2C Master
+0x8040 :        Access to I2C Interface
+
+-- SPI Master
+0x8060 :       Access to SPI Interface
diff --git a/mupix/trb3_periph.p2t b/mupix/trb3_periph.p2t
new file mode 100644 (file)
index 0000000..995161f
--- /dev/null
@@ -0,0 +1,20 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 11
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj
new file mode 100644 (file)
index 0000000..675fe06
--- /dev/null
@@ -0,0 +1,192 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr 
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+
+
+# nXyter Files
+
+#add_file -vhdl -lib "work" "cores/pll_125_hub.vhd"
+add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd"
+add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd"
+add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
+add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
+
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+
+add_file -vhdl -lib "work" "source/nxyter_components.vhd"
+add_file -vhdl -lib "work" "source/level_to_pulse.vhd"
+add_file -vhdl -lib "work" "source/pulse_to_level.vhd"
+add_file -vhdl -lib "work" "source/gray_decoder.vhd"
+add_file -vhdl -lib "work" "source/gray_encoder.vhd"
+add_file -vhdl -lib "work" "source/nx_timer.vhd"
+
+add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd"
+add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
+add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
+add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
+add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
+
+add_file -vhdl -lib "work" "source/nxyter_registers.vhd"
+add_file -vhdl -lib "work" "source/nx_setup.vhd"
+add_file -vhdl -lib "work" "source/nx_histograms.vhd"
+
+add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_sendbyte.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd"
+
+add_file -vhdl -lib "work" "source/adc_spi_master.vhd"
+add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
+add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
+
+add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
+add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
+add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd"
+add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd"
+
+# Needed by ADC9222 Entity
+add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd"
+add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd"
+add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd"
+add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd"
diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd
new file mode 100644 (file)
index 0000000..583f1b2
--- /dev/null
@@ -0,0 +1,907 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+use work.nxyter_components.all;
+
+library ecp3;
+use ecp3.components.all;
+
+
+entity trb3_periph is
+  port(
+    --Clocks
+    CLK_GPLL_RIGHT       : in    std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
+    CLK_GPLL_LEFT        : in    std_logic;  --Clock Manager 1/(2468), 125 MHz
+    CLK_PCLK_LEFT        : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
+    CLK_PCLK_RIGHT       : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+    --Trigger
+    TRIGGER_LEFT         : in    std_logic;  --left side trigger input from fan-out
+    TRIGGER_RIGHT        : in    std_logic;  --right side trigger input from fan-out
+    --Serdes
+    CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
+    CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
+    SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
+    SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
+    SERDES_ADDON_TX      : out   std_logic_vector(11 downto 0);
+    SERDES_ADDON_RX      : in    std_logic_vector(11 downto 0);
+    --Inter-FPGA Communication
+    FPGA5_COMM           : inout std_logic_vector(11 downto 0);
+                                        --Bit 0/1 input, serial link RX active
+                                        --Bit 2/3 output, serial link TX active
+    
+    ---------------------------------------------------------------------------
+    -- BEGIN AddonBoard nXyter
+    ---------------------------------------------------------------------------
+    --Connections to NXYTER-FEB 1
+
+    NX1_RESET_OUT              : out   std_logic;     
+    NX1_I2C_SDA_INOUT          : inout std_logic;
+    NX1_I2C_SCL_INOUT          : inout std_logic;
+    NX1_I2C_SM_RESET_OUT       : out   std_logic;
+    NX1_I2C_REG_RESET_OUT      : out   std_logic;
+    NX1_SPI_SCLK_OUT           : out   std_logic;
+    NX1_SPI_SDIO_INOUT         : inout std_logic;
+    NX1_SPI_CSB_OUT            : out   std_logic;
+    NX1_CLK128_IN              : in    std_logic;
+    NX1_TIMESTAMP_IN           : in    std_logic_vector (7 downto 0);
+    NX1_CLK256A_OUT            : out   std_logic;
+    NX1_TESTPULSE_OUT          : out   std_logic;
+    NX1_ADC_FCLK_IN            : in    std_logic;
+    NX1_ADC_DCLK_IN            : in    std_logic;
+    NX1_ADC_SAMPLE_CLK_OUT     : out   std_logic;
+    NX1_ADC_A_IN               : in    std_logic;
+    NX1_ADC_B_IN               : in    std_logic;
+    NX1_ADC_NX_IN              : in    std_logic;
+    NX1_ADC_D_IN               : in    std_logic;
+    NX1B_ADC_FCLK_IN           : in    std_logic;
+    NX1B_ADC_DCLK_IN           : in    std_logic;
+    NX1B_ADC_A_IN              : in    std_logic;
+    NX1B_ADC_B_IN              : in    std_logic;
+    NX1B_ADC_NX_IN             : in    std_logic;
+    NX1B_ADC_D_IN              : in    std_logic;
+
+    --Connections to NXYTER-FEB 2
+
+    NX2_RESET_OUT              : out   std_logic;     
+    NX2_I2C_SDA_INOUT          : inout std_logic;
+    NX2_I2C_SCL_INOUT          : inout std_logic;
+    NX2_I2C_SM_RESET_OUT       : out   std_logic;
+    NX2_I2C_REG_RESET_OUT      : out   std_logic;
+    NX2_SPI_SCLK_OUT           : out   std_logic;
+    NX2_SPI_SDIO_INOUT         : inout std_logic;
+    NX2_SPI_CSB_OUT            : out   std_logic;
+    NX2_CLK128_IN              : in    std_logic;
+    NX2_TIMESTAMP_IN           : in    std_logic_vector (7 downto 0);
+    NX2_CLK256A_OUT            : out   std_logic;
+    NX2_TESTPULSE_OUT          : out   std_logic;
+    NX2_ADC_FCLK_IN            : in    std_logic;
+    NX2_ADC_DCLK_IN            : in    std_logic;
+    NX2_ADC_SAMPLE_CLK_OUT     : out   std_logic;
+    NX2_ADC_A_IN               : in    std_logic;
+    NX2_ADC_B_IN               : in    std_logic;
+    NX2_ADC_NX_IN              : in    std_logic;
+    NX2_ADC_D_IN               : in    std_logic;
+    NX2B_ADC_FCLK_IN           : in    std_logic;
+    NX2B_ADC_DCLK_IN           : in    std_logic;
+    NX2B_ADC_A_IN              : in    std_logic;
+    NX2B_ADC_B_IN              : in    std_logic;
+    NX2B_ADC_NX_IN             : in    std_logic;
+    NX2B_ADC_D_IN              : in    std_logic;
+     
+    ---------------------------------------------------------------------------
+    -- END AddonBoard nXyter
+    ---------------------------------------------------------------------------
+    
+
+    --Flash ROM & Reboot
+    FLASH_CLK            : out   std_logic;
+    FLASH_CS             : out   std_logic;
+    FLASH_DIN            : out   std_logic;
+    FLASH_DOUT           : in    std_logic;
+    PROGRAMN             : out   std_logic;  --reboot FPGA
+    --Misc
+    TEMPSENS             : inout std_logic;  --Temperature Sensor
+    CODE_LINE            : in    std_logic_vector(1 downto 0);
+    LED_GREEN            : out   std_logic;
+    LED_ORANGE           : out   std_logic;
+    LED_RED              : out   std_logic;
+    LED_YELLOW           : out   std_logic;
+    SUPPL                : in    std_logic;  --terminated diff pair, PCLK, Pads
+    --Test Connectors
+    TEST_LINE            : out   std_logic_vector(15 downto 0)
+    );
+
+  attribute syn_useioff                  : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN     : signal is false;
+  attribute syn_useioff of LED_ORANGE    : signal is false;
+  attribute syn_useioff of LED_RED       : signal is false;
+  attribute syn_useioff of LED_YELLOW    : signal is false;
+  attribute syn_useioff of TEMPSENS      : signal is false;
+  attribute syn_useioff of PROGRAMN      : signal is false;
+  attribute syn_useioff of CODE_LINE     : signal is false;
+  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
+  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+  --important signals
+  attribute syn_useioff of FLASH_CLK     : signal is true;
+  attribute syn_useioff of FLASH_CS      : signal is true;
+  attribute syn_useioff of FLASH_DIN     : signal is true;
+  attribute syn_useioff of FLASH_DOUT    : signal is true;
+  attribute syn_useioff of FPGA5_COMM    : signal is true;
+  attribute syn_useioff of TEST_LINE     : signal is true;
+  --attribute syn_useioff of INP           : signal is false;
+  attribute syn_useioff of NX1_TIMESTAMP_IN   : signal is true;
+  attribute syn_useioff of NX2_TIMESTAMP_IN   : signal is true;
+  --attribute syn_useioff of NX1_ADC_NX_IN   : signal is true;
+  --attribute syn_useioff of DAC_SDO       : signal is true;
+  --attribute syn_useioff of DAC_SDI       : signal is true;
+  --attribute syn_useioff of DAC_SCK       : signal is true;
+  --attribute syn_useioff of DAC_CS        : signal is true;
+
+
+end entity;
+
+
+architecture trb3_periph_arch of trb3_periph is
+  --Constants
+  constant REGIO_NUM_STAT_REGS : integer := 5;
+  constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  -- For 250MHz PLL nxyter clock, THE_256M_ODDR_1
+ --attribute ODDRAPPS : string;
+ --attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED";
+
+  
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i  : std_logic;
+  signal trg_data_valid_i       : std_logic;
+  signal trg_timing_valid_i     : std_logic;
+  signal trg_notiming_valid_i   : std_logic;
+  signal trg_invalid_i          : std_logic;
+  signal trg_type_i             : std_logic_vector(3 downto 0);
+  signal trg_number_i           : std_logic_vector(15 downto 0);
+  signal trg_code_i             : std_logic_vector(7 downto 0);
+  signal trg_information_i      : std_logic_vector(23 downto 0);
+  signal trg_int_number_i       : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i     : std_logic;
+  signal trg_timeout_detected_i : std_logic;
+  signal trg_spurious_trg_i     : std_logic;
+  signal trg_missing_tmg_trg_i  : std_logic;
+  signal trg_spike_detected_i   : std_logic;
+
+  --Data channel
+  signal fee_trg_release_i      : std_logic_vector(2-1 downto 0);
+  signal fee_trg_statusbits_i   : std_logic_vector(2*32-1 downto 0);
+  signal fee_data_i             : std_logic_vector(2*32-1 downto 0);
+  signal fee_data_write_i       : std_logic_vector(2-1 downto 0);
+  signal fee_data_finished_i    : std_logic_vector(2-1 downto 0);
+  signal fee_almost_full_i      : std_logic_vector(2-1 downto 0);
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+  signal spidac_read_en   : std_logic;
+  signal spidac_write_en  : std_logic;
+  signal spidac_data_in   : std_logic_vector(31 downto 0);
+  signal spidac_addr      : std_logic_vector(4 downto 0);
+  signal spidac_data_out  : std_logic_vector(31 downto 0);
+  signal spidac_ack       : std_logic;
+  signal spidac_busy      : std_logic;
+
+  signal dac_cs_i  : std_logic_vector(3 downto 0);
+  signal dac_sck_i : std_logic;
+  signal dac_sdi_i : std_logic;
+
+  signal spi_bram_addr : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+  signal spi_bram_we   : std_logic;
+
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
+
+
+  -- nXyter-FEE-Board Clocks
+  signal nx_clk256                   : std_logic;
+  signal pll_lock_clk256             : std_logic;
+  signal clk_adc_dat                 : std_logic;
+  signal clk_adc_dat_lock            : std_logic;
+  
+  -- nXyter 1 Regio Bus
+  signal nx1_regio_addr_in           : std_logic_vector (15 downto 0);
+  signal nx1_regio_data_in           : std_logic_vector (31 downto 0);
+  signal nx1_regio_data_out          : std_logic_vector (31 downto 0);
+  signal nx1_regio_read_enable_in    : std_logic;
+  signal nx1_regio_write_enable_in   : std_logic;
+  signal nx1_regio_timeout_in        : std_logic;
+  signal nx1_regio_dataready_out     : std_logic;
+  signal nx1_regio_write_ack_out     : std_logic;
+  signal nx1_regio_no_more_data_out  : std_logic;
+  signal nx1_regio_unknown_addr_out  : std_logic;
+  
+  signal nx1_timestamp_sim_o         : std_logic_vector(7 downto 0);
+  signal nx1_clk128_sim_o            : std_logic;
+
+  -- nXyter 2 Regio Bus
+  signal nx2_regio_addr_in           : std_logic_vector (15 downto 0);
+  signal nx2_regio_data_in           : std_logic_vector (31 downto 0);
+  signal nx2_regio_data_out          : std_logic_vector (31 downto 0);
+  signal nx2_regio_read_enable_in    : std_logic;
+  signal nx2_regio_write_enable_in   : std_logic;
+  signal nx2_regio_timeout_in        : std_logic;
+  signal nx2_regio_dataready_out     : std_logic;
+  signal nx2_regio_write_ack_out     : std_logic;
+  signal nx2_regio_no_more_data_out  : std_logic;
+  signal nx2_regio_unknown_addr_out  : std_logic;
+           
+  signal nx2_timestamp_sim_o         : std_logic_vector(7 downto 0);
+  signal nx2_clk128_sim_o            : std_logic;
+           
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_GPLL_RIGHT,
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
+      LOCK  => pll_lock
+      );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+    generic map(
+      SERDES_NUM  => 1,                 --number of serdes in quad
+      EXT_CLOCK   => c_NO,              --use internal clock
+      USE_200_MHZ => c_YES,             --run on 200 MHz clock
+      USE_125_MHZ => c_NO,
+      USE_CTC     => c_NO
+      )
+    port map(
+      CLK                => clk_200_i,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_INT_RX(2),
+      SD_RXD_N_IN        => SERDES_INT_RX(3),
+      SD_TXD_P_OUT       => SERDES_INT_TX(2),
+      SD_TXD_N_OUT       => SERDES_INT_TX(3),
+      SD_REFCLK_P_IN     => open,
+      SD_REFCLK_N_IN     => open,
+      SD_PRSNT_N_IN      => FPGA5_COMM(0),
+      SD_LOS_IN          => FPGA5_COMM(0),
+      SD_TXDIS_OUT       => FPGA5_COMM(2),
+      -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+    generic map(
+      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,  --16 stat reg
+      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,  --8 cotrol reg
+      ADDRESS_MASK              => x"FFFF",
+      BROADCAST_BITMASK         => x"FF",
+      --BROADCAST_SPECIAL_ADDR    => x"45",
+      BROADCAST_SPECIAL_ADDR    => x"48",
+      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+      REGIO_HARDWARE_VERSION    => x"9100_6000",
+      REGIO_INIT_ADDRESS        => x"1100",
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+      CLOCK_FREQUENCY           => 125,
+      TIMING_TRIGGER_RAW        => c_YES,
+      --Configure data handler
+      DATA_INTERFACE_NUMBER     => 2,
+      DATA_BUFFER_DEPTH         => 13,         --13
+      DATA_BUFFER_WIDTH         => 32,
+      DATA_BUFFER_FULL_THRESH   => 2**13-800,  --2**13-1024
+      TRG_RELEASE_AFTER_DATA    => c_YES,
+      HEADER_BUFFER_DEPTH       => 9,
+      HEADER_BUFFER_FULL_THRESH => 2**9-16
+      )
+    port map(
+      CLK                => clk_100_i,
+      RESET              => reset_i,
+      CLK_EN             => '1',
+      MED_DATAREADY_OUT  => med_dataready_out,  -- open,  --
+      MED_DATA_OUT       => med_data_out,  -- open,  --
+      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open,  --
+      MED_READ_IN        => med_read_in,
+      MED_DATAREADY_IN   => med_dataready_in,
+      MED_DATA_IN        => med_data_in,
+      MED_PACKET_NUM_IN  => med_packet_num_in,
+      MED_READ_OUT       => med_read_out,  -- open,  --
+      MED_STAT_OP_IN     => med_stat_op,
+      MED_CTRL_OP_OUT    => med_ctrl_op,
+
+      --Timing trigger in
+      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      --LVL1 trigger to FEE
+      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+      LVL1_TRG_TYPE_OUT        => trg_type_i,
+      LVL1_TRG_NUMBER_OUT      => trg_number_i,
+      LVL1_TRG_CODE_OUT        => trg_code_i,
+      LVL1_TRG_INFORMATION_OUT => trg_information_i,
+      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+
+      --Response from FEE, i.e. nXyter #0
+      FEE_TRG_RELEASE_IN(0)                       => fee_trg_release_i(0),
+      FEE_TRG_STATUSBITS_IN(0*32+31  downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
+      FEE_DATA_IN(0*32+31  downto 0*32)           => fee_data_i(0*32+31 downto 0*32),
+      FEE_DATA_WRITE_IN(0)                        => fee_data_write_i(0),
+      FEE_DATA_FINISHED_IN(0)                     => fee_data_finished_i(0),
+      FEE_DATA_ALMOST_FULL_OUT(0)                 => fee_almost_full_i(0),
+
+      --Response from FEE, i.e. nXyter #1
+      FEE_TRG_RELEASE_IN(1)                       => fee_trg_release_i(1),
+      FEE_TRG_STATUSBITS_IN(1*32+31  downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
+      FEE_DATA_IN(1*32+31  downto 1*32)           => fee_data_i(1*32+31 downto 1*32),
+      FEE_DATA_WRITE_IN(1)                        => fee_data_write_i(1),
+      FEE_DATA_FINISHED_IN(1)                     => fee_data_finished_i(1),
+      FEE_DATA_ALMOST_FULL_OUT(1)                 => fee_almost_full_i(1),
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+      REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+      REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+      REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+      REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+      BUS_ADDR_OUT         => regio_addr_out,
+      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+      BUS_DATA_OUT         => regio_data_out,
+      BUS_DATA_IN          => regio_data_in,
+      BUS_DATAREADY_IN     => regio_dataready_in,
+      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+      BUS_WRITE_ACK_IN     => regio_write_ack_in,
+      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+      BUS_TIMEOUT_OUT      => regio_timeout_out,
+      ONEWIRE_INOUT        => TEMPSENS,
+      ONEWIRE_MONITOR_OUT  => open,
+
+      TIME_GLOBAL_OUT         => global_time,
+      TIME_LOCAL_OUT          => local_time,
+      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+      TIME_TICKS_OUT          => timer_ticks,
+
+      STAT_DEBUG_IPU              => open,
+      STAT_DEBUG_1                => open,
+      STAT_DEBUG_2                => open,
+      STAT_DEBUG_DATA_HANDLER_OUT => open,
+      STAT_DEBUG_IPU_HANDLER_OUT  => open,
+      STAT_TRIGGER_OUT            => open,
+      CTRL_MPLEX                  => (others => '0'),
+      IOBUF_CTRL_GEN              => (others => '0'),
+      STAT_ONEWIRE                => open,
+      STAT_ADDR_DEBUG             => open,
+      DEBUG_LVL1_HANDLER_OUT      => open
+      );
+
+  timing_trg_received_i <= TRIGGER_LEFT;
+  
+--  fee_trg_release_i(1)                      <= '1';
+--  fee_data_i(1*32+31 downto 1*32)           <= (others => '1');
+--  fee_trg_statusbits_i(1*32+31 downto 1*32) <= (others => '0');
+--  fee_data_write_i(1)                       <= '0';
+--  fee_data_finished_i(1)                    <= '1';
+  
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER    => 4,
+      PORT_ADDRESSES => (0 => x"d000",
+                         1 => x"d100",
+                         2 => x"8000",
+                         3 => x"9000", 
+                         others => x"0000"),
+      PORT_ADDR_MASK => (0 => 1,
+                         1 => 6,
+                         2 => 12,
+                         3 => 12,
+                         others => 0)
+      )
+    port map(
+      CLK   => clk_100_i,
+      RESET => reset_i,
+
+      DAT_ADDR_IN          => regio_addr_out,
+      DAT_DATA_IN          => regio_data_out,
+      DAT_DATA_OUT         => regio_data_in,
+      DAT_READ_ENABLE_IN   => regio_read_enable_out,
+      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+      DAT_TIMEOUT_IN       => regio_timeout_out,
+      DAT_DATAREADY_OUT    => regio_dataready_in,
+      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+      --Bus Handler (SPI CTRL)
+      BUS_READ_ENABLE_OUT(0)               => spictrl_read_en,
+      BUS_WRITE_ENABLE_OUT(0)              => spictrl_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)    => spictrl_data_in,
+      BUS_ADDR_OUT(0*16)                   => spictrl_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+1)  => open,
+      BUS_TIMEOUT_OUT(0)                   => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)     => spictrl_data_out,
+      BUS_DATAREADY_IN(0)                  => spictrl_ack,
+      BUS_WRITE_ACK_IN(0)                  => spictrl_ack,
+      BUS_NO_MORE_DATA_IN(0)               => spictrl_busy,
+      BUS_UNKNOWN_ADDR_IN(0)               => '0',
+                                           
+      --Bus Handler (SPI Memory)           
+      BUS_READ_ENABLE_OUT(1)               => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(1)              => spimem_write_en,
+      BUS_DATA_OUT(1*32+31 downto 1*32)    => spimem_data_in,
+      BUS_ADDR_OUT(1*16+5 downto 1*16)     => spimem_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+6)  => open,
+      BUS_TIMEOUT_OUT(1)                   => open,
+      BUS_DATA_IN(1*32+31 downto 1*32)     => spimem_data_out,
+      BUS_DATAREADY_IN(1)                  => spimem_ack,
+      BUS_WRITE_ACK_IN(1)                  => spimem_ack,
+      BUS_NO_MORE_DATA_IN(1)               => '0',
+      BUS_UNKNOWN_ADDR_IN(1)               => '0',
+
+      --Bus Handler (nXyter1 trb_net16_regio_bus_handler)
+      BUS_READ_ENABLE_OUT(2)               => nx1_regio_read_enable_in,
+      BUS_WRITE_ENABLE_OUT(2)              => nx1_regio_write_enable_in,
+      BUS_DATA_OUT(2*32+31 downto 2*32)    => nx1_regio_data_in,
+      BUS_ADDR_OUT(2*16+11 downto 2*16)    => nx1_regio_addr_in(11 downto 0),
+      BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+      BUS_TIMEOUT_OUT(2)                   => open,  --nx1_regio_timeout_in,
+      BUS_DATA_IN(2*32+31 downto 2*32)     => nx1_regio_data_out,
+      BUS_DATAREADY_IN(2)                  => nx1_regio_dataready_out,
+      BUS_WRITE_ACK_IN(2)                  => nx1_regio_write_ack_out,
+      BUS_NO_MORE_DATA_IN(2)               => nx1_regio_no_more_data_out,
+      BUS_UNKNOWN_ADDR_IN(2)               => nx1_regio_unknown_addr_out,
+
+      --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
+      BUS_READ_ENABLE_OUT(3)               => nx2_regio_read_enable_in,
+      BUS_WRITE_ENABLE_OUT(3)              => nx2_regio_write_enable_in,
+      BUS_DATA_OUT(3*32+31 downto 3*32)    => nx2_regio_data_in,
+      BUS_ADDR_OUT(3*16+11 downto 3*16)    => nx2_regio_addr_in(11 downto 0),
+      BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open,
+      BUS_TIMEOUT_OUT(3)                   => open,  --nx2_regio_timeout_in,
+      BUS_DATA_IN(3*32+31 downto 3*32)     => nx2_regio_data_out,
+      BUS_DATAREADY_IN(3)                  => nx2_regio_dataready_out,
+      BUS_WRITE_ACK_IN(3)                  => nx2_regio_write_ack_out,
+      BUS_NO_MORE_DATA_IN(3)               => nx2_regio_no_more_data_out,
+      BUS_UNKNOWN_ADDR_IN(3)               => nx2_regio_unknown_addr_out,
+
+      
+      STAT_DEBUG => open
+      );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+  THE_SPI_MASTER : spi_master
+    port map(
+      CLK_IN         => clk_100_i,
+      RESET_IN       => reset_i,
+      -- Slave bus
+      BUS_READ_IN    => spictrl_read_en,
+      BUS_WRITE_IN   => spictrl_write_en,
+      BUS_BUSY_OUT   => spictrl_busy,
+      BUS_ACK_OUT    => spictrl_ack,
+      BUS_ADDR_IN(0) => spictrl_addr,
+      BUS_DATA_IN    => spictrl_data_in,
+      BUS_DATA_OUT   => spictrl_data_out,
+      -- SPI connections
+      SPI_CS_OUT     => FLASH_CS,
+      SPI_SDI_IN     => FLASH_DOUT,
+      SPI_SDO_OUT    => FLASH_DIN,
+      SPI_SCK_OUT    => FLASH_CLK,
+      -- BRAM for read/write data
+      BRAM_A_OUT     => spi_bram_addr,
+      BRAM_WR_D_IN   => spi_bram_wr_d,
+      BRAM_RD_D_OUT  => spi_bram_rd_d,
+      BRAM_WE_OUT    => spi_bram_we,
+      -- Status lines
+      STAT           => open
+      );
+
+  -- data memory for SPI accesses
+  THE_SPI_MEMORY : spi_databus_memory
+    port map(
+      CLK_IN        => clk_100_i,
+      RESET_IN      => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN   => spimem_addr,
+      BUS_READ_IN   => spimem_read_en,
+      BUS_WRITE_IN  => spimem_write_en,
+      BUS_ACK_OUT   => spimem_ack,
+      BUS_DATA_IN   => spimem_data_in,
+      BUS_DATA_OUT  => spimem_data_out,
+      -- state machine connections
+      BRAM_ADDR_IN  => spi_bram_addr,
+      BRAM_WR_D_OUT => spi_bram_wr_d,
+      BRAM_RD_D_IN  => spi_bram_rd_d,
+      BRAM_WE_IN    => spi_bram_we,
+      -- Status lines
+      STAT          => open
+      );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => PROGRAMN
+      );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  LED_GREEN  <= not med_stat_op(9);
+  LED_ORANGE <= not med_stat_op(10);
+  LED_RED    <= timing_trg_received_i;
+  LED_YELLOW <= not med_stat_op(11);
+
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #1
+-----------------------------------------------------------------------------
+
+  nXyter_FEE_board_0: nXyter_FEE_board
+    generic map (
+      BOARD_ID => x"affe"
+      )
+    port map (
+      CLK_IN                     => clk_100_i,
+      RESET_IN                   => reset_i,
+      CLK_NX_IN                  => nx_clk256,
+      CLK_ADC_IN                 => clk_adc_dat,
+                                 
+      I2C_SDA_INOUT              => NX1_I2C_SDA_INOUT,
+      I2C_SCL_INOUT              => NX1_I2C_SCL_INOUT,
+      I2C_SM_RESET_OUT           => NX1_I2C_SM_RESET_OUT,
+      I2C_REG_RESET_OUT          => NX1_I2C_REG_RESET_OUT,
+                                 
+      SPI_SCLK_OUT               => NX1_SPI_SCLK_OUT,
+      SPI_SDIO_INOUT             => NX1_SPI_SDIO_INOUT,
+      SPI_CSB_OUT                => NX1_SPI_CSB_OUT,
+                                 
+      NX_CLK128_IN               => NX1_CLK128_IN,
+      NX_TIMESTAMP_IN            => NX1_TIMESTAMP_IN,
+      -- NX_CLK128_IN               => nx1_clk128_sim_o,
+      -- NX_TIMESTAMP_IN            => nx1_timestamp_sim_o,
+                                 
+      NX_RESET_OUT               => NX1_RESET_OUT,
+      NX_TESTPULSE_OUT           => NX1_TESTPULSE_OUT,
+                                 
+      ADC_FCLK_IN(0)             => NX1_ADC_FCLK_IN,
+      ADC_FCLK_IN(1)             => NX1B_ADC_FCLK_IN,
+      ADC_DCLK_IN(0)             => NX1_ADC_DCLK_IN,
+      ADC_DCLK_IN(1)             => NX1B_ADC_DCLK_IN,
+      ADC_SAMPLE_CLK_OUT         => NX1_ADC_SAMPLE_CLK_OUT,
+      ADC_A_IN(0)                => NX1_ADC_A_IN,
+      ADC_A_IN(1)                => NX1B_ADC_A_IN,
+      ADC_B_IN(0)                => NX1_ADC_B_IN,
+      ADC_B_IN(1)                => NX1B_ADC_B_IN,
+      ADC_NX_IN(0)               => NX1_ADC_NX_IN,
+      ADC_NX_IN(1)               => NX1B_ADC_NX_IN,
+      ADC_D_IN(0)                => NX1_ADC_D_IN,
+      ADC_D_IN(1)                => NX1B_ADC_D_IN,
+
+      LVL1_TRG_DATA_VALID_IN     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_IN   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_IN        => trg_invalid_i,
+      LVL1_TRG_TYPE_IN           => trg_type_i,
+      LVL1_TRG_NUMBER_IN         => trg_number_i,
+      LVL1_TRG_CODE_IN           => trg_code_i,
+      LVL1_TRG_INFORMATION_IN    => trg_information_i,
+      LVL1_INT_TRG_NUMBER_IN     => trg_int_number_i,
+
+      FEE_TRG_RELEASE_OUT        => fee_trg_release_i(0),
+      FEE_TRG_STATUSBITS_OUT     => fee_trg_statusbits_i(31 downto 0),
+      FEE_DATA_OUT               => fee_data_i(31 downto 0),
+      FEE_DATA_WRITE_OUT         => fee_data_write_i(0),
+      FEE_DATA_FINISHED_OUT      => fee_data_finished_i(0),
+      FEE_DATA_ALMOST_FULL_IN    => fee_almost_full_i(0),
+      
+      REGIO_ADDR_IN              => nx1_regio_addr_in,
+      REGIO_DATA_IN              => nx1_regio_data_in,
+      REGIO_DATA_OUT             => nx1_regio_data_out,
+      REGIO_READ_ENABLE_IN       => nx1_regio_read_enable_in,
+      REGIO_WRITE_ENABLE_IN      => nx1_regio_write_enable_in,
+      REGIO_TIMEOUT_IN           => nx1_regio_timeout_in,
+      REGIO_DATAREADY_OUT        => nx1_regio_dataready_out,
+      REGIO_WRITE_ACK_OUT        => nx1_regio_write_ack_out,
+      REGIO_NO_MORE_DATA_OUT     => nx1_regio_no_more_data_out,
+      REGIO_UNKNOWN_ADDR_OUT     => nx1_regio_unknown_addr_out,
+                                 
+      DEBUG_LINE_OUT            => TEST_LINE
+      --DEBUG_LINE_OUT                => open
+      );
+  
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #2
+-----------------------------------------------------------------------------
+
+  nXyter_FEE_board_1: nXyter_FEE_board
+    generic map (
+      BOARD_ID => x"babe"
+      )
+    port map (
+      CLK_IN                     => clk_100_i,
+      RESET_IN                   => reset_i,
+      CLK_NX_IN                  => nx_clk256,
+      CLK_ADC_IN                 => clk_adc_dat,
+                                 
+      I2C_SDA_INOUT              => NX2_I2C_SDA_INOUT,
+      I2C_SCL_INOUT              => NX2_I2C_SCL_INOUT,
+      I2C_SM_RESET_OUT           => NX2_I2C_SM_RESET_OUT,
+      I2C_REG_RESET_OUT          => NX2_I2C_REG_RESET_OUT,
+                                    
+      SPI_SCLK_OUT               => NX2_SPI_SCLK_OUT,
+      SPI_SDIO_INOUT             => NX2_SPI_SDIO_INOUT,
+      SPI_CSB_OUT                => NX2_SPI_CSB_OUT,
+      
+      NX_CLK128_IN               => NX2_CLK128_IN,
+      NX_TIMESTAMP_IN            => NX2_TIMESTAMP_IN,
+                                    
+      NX_RESET_OUT               => NX2_RESET_OUT,
+      NX_TESTPULSE_OUT           => NX2_TESTPULSE_OUT,
+  
+      ADC_FCLK_IN(0)             => NX2_ADC_FCLK_IN,
+      ADC_FCLK_IN(1)             => NX2B_ADC_FCLK_IN,
+      ADC_DCLK_IN(0)             => NX2_ADC_DCLK_IN,
+      ADC_DCLK_IN(1)             => NX2B_ADC_DCLK_IN,
+      ADC_SAMPLE_CLK_OUT         => NX2_ADC_SAMPLE_CLK_OUT,
+      ADC_A_IN(0)                => NX2_ADC_A_IN,
+      ADC_A_IN(1)                => NX2B_ADC_A_IN,
+      ADC_B_IN(0)                => NX2_ADC_B_IN,
+      ADC_B_IN(1)                => NX2B_ADC_B_IN,
+      ADC_NX_IN(0)               => NX2_ADC_NX_IN,
+      ADC_NX_IN(1)               => NX2B_ADC_NX_IN,
+      ADC_D_IN(0)                => NX2_ADC_D_IN,
+      ADC_D_IN(1)                => NX2B_ADC_D_IN,
+      
+      LVL1_TRG_DATA_VALID_IN     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_IN   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_IN        => trg_invalid_i,
+      LVL1_TRG_TYPE_IN           => trg_type_i,
+      LVL1_TRG_NUMBER_IN         => trg_number_i,
+      LVL1_TRG_CODE_IN           => trg_code_i,
+      LVL1_TRG_INFORMATION_IN    => trg_information_i,
+      LVL1_INT_TRG_NUMBER_IN     => trg_int_number_i,
+  
+      FEE_TRG_RELEASE_OUT        => fee_trg_release_i(1),
+      FEE_TRG_STATUSBITS_OUT     => fee_trg_statusbits_i(63 downto 32),
+      FEE_DATA_OUT               => fee_data_i(63 downto 32),
+      FEE_DATA_WRITE_OUT         => fee_data_write_i(1),
+      FEE_DATA_FINISHED_OUT      => fee_data_finished_i(1),
+      FEE_DATA_ALMOST_FULL_IN    => fee_almost_full_i(1),
+      
+      REGIO_ADDR_IN              => nx2_regio_addr_in,
+      REGIO_DATA_IN              => nx2_regio_data_in,
+      REGIO_DATA_OUT             => nx2_regio_data_out,
+      REGIO_READ_ENABLE_IN       => nx2_regio_read_enable_in,
+      REGIO_WRITE_ENABLE_IN      => nx2_regio_write_enable_in,
+      REGIO_TIMEOUT_IN           => nx2_regio_timeout_in,
+      REGIO_DATAREADY_OUT        => nx2_regio_dataready_out,
+      REGIO_WRITE_ACK_OUT        => nx2_regio_write_ack_out,
+      REGIO_NO_MORE_DATA_OUT     => nx2_regio_no_more_data_out,
+      REGIO_UNKNOWN_ADDR_OUT     => nx2_regio_unknown_addr_out,
+                                 
+      --DEBUG_LINE_OUT            => TEST_LINE
+      DEBUG_LINE_OUT                => open
+      );
+
+  -----------------------------------------------------------------------------
+  -- nXyter common Clocks
+  -----------------------------------------------------------------------------
+  pll_nx_clk256_1: entity work.pll_nx_clk256
+    port map (
+      CLK   => clk_100_i,
+      CLKOP => nx_clk256,
+      LOCK  => pll_lock_clk256
+      );
+
+  NX1_CLK256A_OUT <= nx_clk256;
+  NX2_CLK256A_OUT <= nx_clk256;
+
+  -- ADC Receiver Clock
+  pll_adc_clk192_1: pll_adc_clk192
+    port map (
+      CLK   => CLK_PCLK_LEFT,
+      CLKOP => clk_adc_dat,
+      LOCK  => clk_adc_dat_lock
+      );
+
+  -----------------------------------------------------------------------------
+  
+  -- 250MHz Clock to nXyters
+  --pll_nx_clk250_1: entity work.pll_nx_clk250
+  --  port map (
+  --    CLK   => CLK_GPLL_LEFT,
+  --    CLKOP => nx1_clk256_o,
+  --    LOCK  => open
+  --    );
+
+  --pll_125_hub_1: pll_125_hub
+  --  port map (
+  --    CLK   => CLK_GPLL_LEFT,
+  --    CLKOP => open,
+  --    CLKOK => nx1_clk256_o,
+  --    LOCK  => open
+  --    );
+ -- NX1_CLK256A_OUT <= CLK_PCLK_RIGHT;
+  
+  --THE_256M_ODDR_1: ODDRXD1
+  --  port map(
+  --    SCLK  => nx1_clk256_o,
+  --    DA    => '1',
+  --    DB    => '0',
+  --    Q     => NX1_CLK256A_OUT
+  --    );
+
+
+-------------------------------------------------------------------------------
+-- Timestamp Simulator
+-------------------------------------------------------------------------------
+--   nxyter_timestamp_sim_1: nxyter_timestamp_sim
+--     port map (
+--       CLK_IN        => CLK_GPLL_LEFT,
+--       RESET_IN      => reset_i,
+--       TIMESTAMP_OUT => nx1_timestamp_sim_o,
+--       CLK128_OUT    => nx1_clk128_sim_o
+--       );
+
+  
+---------------------------------------------------------------------------
+-- Test Connector - Logic Analyser
+---------------------------------------------------------------------------
+
+ -- TEST_LINE(0)           <= clk_100_i;
+ -- TEST_LINE(1)           <= NX1_CLK128_IN;
+ -- TEST_LINE(15 downto 2) <= (others => '0');
+  
+
+end architecture;
diff --git a/mupix/trb3_periph_constraints.lpf b/mupix/trb3_periph_constraints.lpf
new file mode 100644 (file)
index 0000000..0022ba1
--- /dev/null
@@ -0,0 +1,93 @@
+# BLOCK RESETPATHS ;
+# BLOCK ASYNCPATHS ;
+# BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+  SYSCONFIG MCCLK_FREQ = 20;
+
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+
+  FREQUENCY PORT NX1_CLK256A_OUT 256 MHz;
+  FREQUENCY PORT NX2_CLK256A_OUT 256 MHz;
+    
+#Put the names of your nxyter inputs here:  
+  FREQUENCY PORT NX1_CLK128_IN 128 MHz;
+  FREQUENCY PORT NX2_CLK128_IN 128 MHz;
+  FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz;   
+  FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;  
+
+#Change the next two lines to the clk_fast signal of the ADC  
+  USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0";
+  USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0";
+
+  
+  USE PRIMARY NET "CLK_PCLK_LEFT";
+  USE PRIMARY NET "CLK_PCLK_LEFT_c";
+  
+  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
+  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c";
+
+  USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
+  USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c";
+
+  USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+  USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+  
+  #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+  #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+  
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";  
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+
+
+#################################################################
+# Relax some of the timing constraints
+#################################################################
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
+
+
+#################################################################
+# Constraints for nxyter inputs
+#################################################################
+
+# look at .par and .twr.setup file for clocks 
+# and .mrp or errors
+PROHIBIT PRIMARY NET "NX1_CLK128_IN_c";
+PROHIBIT SECONDARY NET "NX1_CLK128_IN_c";
+
+PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
+PROHIBIT SECONDARY NET "NX2_CLK128_IN_c";
+
+PROHIBIT PRIMARY NET "TEST_LINE_c_0";
+PROHIBIT SECONDARY NET "TEST_LINE_c_0";
+
+DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; 
+
+DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN" ; 
+
+MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c" 50 ns;
+MULTICYCLE FROM CLKNET "NX2_CLK256A_OUT_c" 50 ns;
+
+#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c";
+#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";
+