few details added, JM

diff --git a/trb3/GbEGettingStarted.tex b/trb3/GbEGettingStarted.tex
index 346f27c016ef6026d9581470709495cef38fd090..71de81fff8783abdff098e4cbccd81a3513440b1 100644 (file)
--- a/trb3/GbEGettingStarted.tex
+++ b/trb3/GbEGettingStarted.tex
@@ -1,3 +1,4 @@
+\label{sec:GbeGettingStarted}
 In order to control TRB3 or a larger system with TRB3 as slow control client via Ethernet link, one needs to properly install and compile the trbcmd server, load a correct FPGA design and configure DHCP deamon on the server PC.Follow the instructions described in the next points.
 
 \subsubsection{FPGA design}

diff --git a/trb3/HardwareProject.tex b/trb3/HardwareProject.tex
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 6e97afb896b99705a7bdd30103d8e17733f1f74a..6aa4f07c99a6d7bf1a93134af47b9dce21837310 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -118,4 +118,21 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th
 \end{itemize*}
 
 
+\subsection{JTAG}
+Since programming of FPGAs can be done via GbE, the JTAG connector is usually not used. In case of corrupted designs it provides the only access to reconfigure FPGAs. Loading a design directly to the FPGA is quite fast (25 s) but loading it to the Flash ROM is deadly slow (5 minutes) - better: first load the design to the FPGA via JTAG, then flash it using TrbNet.
+
+The pin-out of the JTAG connector (1x8 pin-header near the power supply). 
+\begin{description*}
+ \item[1] VCC (3.3V, red)
+ \item[2] TMS (violet)
+ \item[3] TCK (white)
+ \item[4] TDI (orange)
+ \item[5] TDO (brown)
+ \item[6] GND (black)
+ \item[7] GND (n/c)
+ \item[8] GND (n/c)
+\end{description*}
+Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards. If you experience strange behavior of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
+
+
 

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diff --git a/trb3/main.tex b/trb3/main.tex
index 9ca3f5f23525144aefec5ed24e18c5de10ec9c95..33c9a9a00e7e63e10c6cdcb4260db1a8f3f008a5 100755 (executable)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -202,6 +202,8 @@
 
 \cleardoublepage
 \input{trb3qs_part}
+  \section{New Hardware Project}
+  \input{HardwareProject}
 
 \cleardoublepage
 \part{Synchronous TrbNet}

diff --git a/trb3/trb3qs_configuration.tex b/trb3/trb3qs_configuration.tex
index ae433fe3132fd0db265db83487f707fa787a3a75..2c9cc69c2049827e1b460953378bde78dceddb9a 100644 (file)
--- a/trb3/trb3qs_configuration.tex
+++ b/trb3/trb3qs_configuration.tex
@@ -117,6 +117,7 @@ rtt min/avg/max/mdev = 0.053/0.062/0.077/0.013 ms
 \end{lstlisting}
 
 \subsection{Starting TRBnet}
+[Please also read section GbE Slow-Control (\ref{sec:GbeGettingStarted}) for additional information.]
 
 Each TRB3 can be controlled with \verb+trbcmd+ command over then TRBnet. Each
 TRBnet is assigned to TRB3 and when communicating to TRB3 you must inform