+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net_gbe_components.all;
-use work.med_sync_define_RS.all;
-
-entity gbe_med_interface_single_5G is
- port (
- RESET : in std_logic;
- GSR_N : in std_logic;
- CLK_SYS_IN : in std_logic;
- CLK_125_OUT : out std_logic;
- CLK_125_IN : in std_logic;
- CLK_125_RX_OUT : out std_logic;
- -- MAC status and config
- MAC_READY_CONF_OUT : out std_logic;
- MAC_RECONF_IN : in std_logic;
- MAC_AN_READY_OUT : out std_logic;
- -- MAC data interface
- MAC_FIFOAVAIL_IN : in std_logic;
- MAC_FIFOEOF_IN : in std_logic;
- MAC_FIFOEMPTY_IN : in std_logic;
- MAC_RX_FIFOFULL_IN : in std_logic;
- -- MAC TX interface
- MAC_TX_DATA_IN : in std_logic_vector(7 downto 0);
- MAC_TX_READ_OUT : out std_logic;
- MAC_TX_DISCRFRM_OUT : out std_logic;
- MAC_TX_STAT_EN_OUT : out std_logic;
- MAC_TX_STATS_OUT : out std_logic_vector(30 downto 0);
- MAC_TX_DONE_OUT : out std_logic;
- -- MAC RX interface
- MAC_RX_FIFO_ERR_OUT : out std_logic;
- MAC_RX_STATS_OUT : out std_logic_vector(31 downto 0);
- MAC_RX_DATA_OUT : out std_logic_vector(7 downto 0);
- MAC_RX_WRITE_OUT : out std_logic;
- MAC_RX_STAT_EN_OUT : out std_logic;
- MAC_RX_EOF_OUT : out std_logic;
- MAC_RX_ERROR_OUT : out std_logic;
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_PRSNT_N_IN : in std_logic;
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- STATUS_OUT : out std_logic_vector(7 downto 0);
- -- Debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
- );
-end entity gbe_med_interface_single_5G;
-
-architecture RTL of gbe_med_interface_single_5G is
-
- component sgmii_gbe_core -- checked for ECP5-5G core
- port(
- rst_n : in std_logic;
- signal_detect : in std_logic;
- gbe_mode : in std_logic;
- sgmii_mode : in std_logic;
- operational_rate : in std_logic_vector(1 downto 0);
- debug_link_timer_short : in std_logic;
-
- force_isolate : in std_logic;
- force_loopback : in std_logic;
- force_unidir : in std_logic;
-
- rx_compensation_err : out std_logic;
-
- ctc_drop_flag : out std_logic;
- ctc_add_flag : out std_logic;
- an_link_ok : out std_logic;
-
- tx_clk_125 : in std_logic;
- tx_clock_enable_source : out std_logic;
- tx_clock_enable_sink : in std_logic;
- tx_d : in std_logic_vector(7 downto 0);
- tx_en : in std_logic;
- tx_er : in std_logic;
- rx_clk_125 : in std_logic;
- rx_clock_enable_source : out std_logic;
- rx_clock_enable_sink : in std_logic;
- rx_d : out std_logic_vector(7 downto 0);
- rx_dv : out std_logic;
- rx_er : out std_logic;
- col : out std_logic;
- crs : out std_logic;
- tx_data : out std_logic_vector(7 downto 0);
- tx_kcntl : out std_logic;
- tx_disparity_cntl : out std_logic;
-
- xmit_autoneg : out std_logic;
-
- serdes_recovered_clk : in std_logic;
- rx_data : in std_logic_vector(7 downto 0);
- rx_even : in std_logic;
- rx_kcntl : in std_logic;
- rx_disp_err : in std_logic;
- rx_cv_err : in std_logic;
- rx_err_decode_mode : in std_logic;
- mr_an_complete : out std_logic;
- mr_page_rx : out std_logic;
- mr_lp_adv_ability : out std_logic_vector(15 downto 0);
- mr_main_reset : in std_logic;
- mr_an_enable : in std_logic;
- mr_restart_an : in std_logic;
- mr_adv_ability : in std_logic_vector(15 downto 0)
- );
- end component;
-
- component tsmac_gbe -- checked for ECP5-5G core
- port(
- --------------- clock and reset port declarations ------------------
- hclk : in std_logic;
- txmac_clk : in std_logic;
- rxmac_clk : in std_logic;
- reset_n : in std_logic;
- ------------------- Input signals to the GMII ----------------
- rxd : in std_logic_vector(7 downto 0);
- rx_dv : in std_logic;
- rx_er : in std_logic;
- -------------------- Input signals to the CPU I/F -------------------
- haddr : in std_logic_vector(7 downto 0);
- hdatain : in std_logic_vector(7 downto 0);
- hcs_n : in std_logic;
- hwrite_n : in std_logic;
- hread_n : in std_logic;
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata : in std_logic_vector(7 downto 0);
- tx_fifoavail : in std_logic;
- tx_fifoeof : in std_logic;
- tx_fifoempty : in std_logic;
- tx_sndpaustim : in std_logic_vector(15 downto 0);
- tx_sndpausreq : in std_logic;
- tx_fifoctrl : in std_logic;
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full : in std_logic;
- ignore_pkt : in std_logic;
- -------------------- Output signals from the GMII -----------------------
- txd : out std_logic_vector(7 downto 0);
- tx_en : out std_logic;
- tx_er : out std_logic;
- -------------------- Output signals from the CPU I/F -------------------
- hdataout : out std_logic_vector(7 downto 0);
- hdataout_en_n : out std_logic;
- hready_n : out std_logic;
- cpu_if_gbit_en : out std_logic;
- ---------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread : out std_logic;
- tx_discfrm : out std_logic;
- tx_staten : out std_logic;
- tx_done : out std_logic;
- tx_statvec : out std_logic_vector(30 downto 0);
- ---------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error : out std_logic;
- rx_stat_vector : out std_logic_vector(31 downto 0);
- rx_dbout : out std_logic_vector(7 downto 0);
- rx_write : out std_logic;
- rx_stat_en : out std_logic;
- rx_eof : out std_logic;
- rx_error : out std_logic
- );
- end component;
-
- signal sd_rx_clk : std_logic;
- signal sd_tx_kcntl : std_logic_vector(0 downto 0);
- signal sd_tx_data : std_logic_vector(7 downto 0);
- signal xmit : std_logic_vector(0 downto 0);
- signal sd_tx_correct_disp : std_logic_vector(0 downto 0);
- signal sd_rx_data : std_logic_vector(7 downto 0);
- signal sd_rx_kcntl : std_logic_vector(0 downto 0);
- signal sd_rx_disp_error : std_logic_vector(0 downto 0);
- signal sd_rx_cv_error : std_logic_vector(0 downto 0);
- signal lsm_status : std_logic;
- signal rx_clk_en : std_logic;
- signal tx_clk_en : std_logic;
- signal operational_rate : std_logic_vector(1 downto 0);
- signal an_complete : std_logic;
- signal mr_page_rx : std_logic;
- signal mr_lp_adv_ability : std_logic_vector(15 downto 0);
- signal mr_main_reset : std_logic;
- signal mr_restart_an : std_logic;
- signal mr_adv_ability : std_logic_vector(15 downto 0);
- signal mr_an_enable : std_logic;
- signal an_link_ok : std_logic;
- signal pcs_rxd : std_logic_vector(7 downto 0);
- signal pcs_rx_en : std_logic;
- signal pcs_rx_er : std_logic;
- signal pcs_txd : std_logic_vector(7 downto 0);
- signal pcs_tx_en : std_logic;
- signal pcs_tx_er : std_logic;
- signal tsm_hdataout_en_n : std_logic;
- signal tsm_hready_n : std_logic;
- signal tsm_hread_n : std_logic;
- signal tsm_hwrite_n : std_logic;
- signal tsm_hcs_n : std_logic;
- signal tsm_hdata : std_logic_vector(7 downto 0);
- signal tsm_haddr : std_logic_vector(7 downto 0);
-
- signal synced_rst : std_logic;
-
- signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic;
-
- signal link_rx_ready : std_logic;
- signal rx_los_low : std_logic;
- signal rx_cdr_lol : std_logic;
- signal rst_dual : std_logic;
- signal rx_pcs_rst : std_logic;
- signal rx_pcs_rst_q : std_logic;
- signal rx_serdes_rst : std_logic;
- signal rx_serdes_rst_q : std_logic;
- signal tx_pcs_rst : std_logic;
- signal link_tx_ready : std_logic;
- signal pll_lol : std_logic;
-
- signal debug : std_logic_vector(63 downto 0);
-
- -- for replacing register interface
- signal delay_q : std_logic_vector(7 downto 0);
- signal pulse : std_logic;
-
-begin
-
- -- We allow only one GbE in ECP5 for now
- assert not (LINKS_ACTIVE = b"0000") report "Error: no GbE interface selected" severity error;
-
- --------------------------------------------------------------------
- --------------------------------------------------------------------
- DEBUG_OUT <= debug;
- -- debug(19..0) are on INTCOM
- -- debug(33..20) are on GPIO
- -- 33 = CLK2 (white/green)
- -- 32 = CLK1 (white/blue)
- --------------------------------------------------------------------
- --------------------------------------------------------------------
-
--- reset_sync: process( CLK_125_IN )
--- begin
--- if( rising_edge(CLK_125_IN) ) then
- synced_rst <= GSR_N;
--- end if;
--- end process reset_sync;
- rst_dual <= not GSR_N;
-
- SD_TXDIS_OUT <= '0';
-
- CLK_125_OUT <= CLK_125_IN;
- CLK_125_RX_OUT <= sd_rx_clk;
-
- -- Some notes on clocks: the SerDes uses TX and RX bridge FIFO, with RX FIFO being clocked on
- -- both read and write side by rx_pclk, and TX FIFO being clocked on write side by txi_clk.
- -- For TX, we can use local 125MHz clock.
- -- For RX, the SGMII core implements the CTC FIFO, and by clocking SGMII also by local 125MHz
- -- (except serdes_recovered_clk, which goes to rx_pclk) we have *everthing* behind the SGMII
- -- on local 125MHz clock.
-
- gbe_serdes: entity serdes_gbe
- port map(
- -- external I/Os
- hdinp => SD_RXD_P_IN,
- hdinn => SD_RXD_N_IN,
- hdoutp => SD_TXD_P_OUT,
- hdoutn => SD_TXD_N_OUT,
- -- clocks
- pll_refclki => CLK_125_IN, -- TX reference clock for PLL
- rxrefclk => CLK_125_IN, -- RX reference clock for CDR
- txi_clk => CLK_125_IN, -- feeds the TX FIFO
- tx_pclk => open, -- not really needed
- rx_pclk => sd_rx_clk, -- recovered RX clock, also used on FIFO!
- -- TX channel
- txdata => sd_tx_data,
- tx_k => sd_tx_kcntl,
- tx_disp_correct => sd_tx_correct_disp,
- xmit => xmit, -- not used, should not harm
- -- RX channel
- rxdata => sd_rx_data,
- rx_k => sd_rx_kcntl,
- rx_disp_err => sd_rx_disp_error,
- rx_cv_err => sd_rx_cv_error,
- lsm_status_s => lsm_status,
- signal_detect_c => '1', -- enable internal LSM
- -- Status signals
- pll_lol => pll_lol,
- rx_cdr_lol_s => rx_cdr_lol,
- rx_los_low_s => rx_los_low,
- -- Power control
- rx_pwrup_c => '1',
- tx_pwrup_c => '1',
- serdes_pdb => '1', -- DUAL is powered up
- -- Resets
- sli_rst => '0', -- soft logic reset (?)
- rst_dual_c => rst_dual,
- rx_pcs_rst_c => rx_pcs_rst_q,
- rx_serdes_rst_c => rx_serdes_rst_q,
- tx_pcs_rst_c => tx_pcs_rst,
- serdes_rst_dual_c => '0',
- tx_serdes_rst_c => '0'
- );
-
- -- RSL for TX of SerDes, based on extRSL logic
- THE_MAIN_TX_RST: main_tx_reset_RS
- port map (
- CLEAR => rst_dual,
- CLK_REF => CLK_125_IN,
- TX_PLL_LOL_IN => pll_lol,
- TX_CLOCK_AVAIL_IN => '1', -- not needed here
- TX_PCS_RST_CH_C_OUT => tx_pcs_rst,
- SYNC_TX_QUAD_OUT => open, --not needed here
- LINK_TX_READY_OUT => link_tx_ready,
- STATE_OUT => open
- );
-
- -- RSL for RX of SerDes, based on extRSL logic
- -- CAVEAT: reset signals MUST BE sync'ed to recovered RX clock!
- THE_MAIN_RX_RST: main_rx_reset_RS
- port map(
- CLEAR => rst_dual,
- CLK_REF => CLK_125_IN,
- CDR_LOL_IN => rx_cdr_lol,
- CV_IN => sd_rx_cv_error(0),
- LSM_IN => lsm_status,
- LOS_IN => rx_los_low,
- WAP_ZERO_IN => '1', -- not needed here
- -- outputs
- WAP_REQ_OUT => open, -- not needed here
- RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based
- RX_PCS_RST_OUT => rx_pcs_rst, -- CLK_REF based
- LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based
- STATE_OUT => open
- );
-
- -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
- SYNC_RST_SIGS: entity work.signal_sync
- generic map( WIDTH => 2 )
- port map(
- RESET => '0',
- CLK0 => sd_rx_clk,
- CLK1 => sd_rx_clk,
- D_IN(0) => rx_pcs_rst,
- D_IN(1) => rx_serdes_rst,
- D_OUT(0) => rx_pcs_rst_q,
- D_OUT(1) => rx_serdes_rst_q
- );
-
- -- Status signals
- STATUS_OUT(7) <= '0';
- STATUS_OUT(6) <= '0';
- STATUS_OUT(5) <= '0';
- STATUS_OUT(4) <= pcs_rx_en; -- SerDes RX activity
- STATUS_OUT(3) <= pcs_tx_en; -- SerDes TX activity
- STATUS_OUT(2) <= an_complete; -- GbE Autonegotiation completed
- STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
- STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
-
--- -- "Good" debugging pins
--- debug(7 downto 0) <= sd_tx_data;
--- debug(15 downto 8) <= sd_rx_data;
--- debug(16) <= sd_tx_kcntl(0);
--- debug(17) <= sd_rx_kcntl(0);
--- debug(18) <= '0';
--- debug(19) <= '0';
--- -- "Bad" debugging pins
--- debug(20) <= pll_lol;
--- debug(21) <= rx_cdr_lol;
--- debug(22) <= rx_los_low;
--- debug(23) <= sd_rx_cv_error(0);
--- debug(24) <= lsm_status;
--- debug(25) <= mr_main_reset;
--- debug(26) <= mr_an_enable;
--- debug(27) <= mr_restart_an;
--- debug(28) <= mr_page_rx;
--- debug(29) <= an_complete;
--- debug(30) <= an_link_ok;
--- debug(31) <= '0';
--- debug(32) <= link_rx_ready;
--- debug(33) <= link_tx_ready;
- debug(62) <= link_rx_ready;
- debug(63) <= link_tx_ready;
-
- -- SGMII core
- SGMII_GBE_PCS : sgmii_gbe_core
- port map(
- rst_n => synced_rst,
- signal_detect => link_rx_ready,
- gbe_mode => '1',
- sgmii_mode => '0',
- operational_rate => operational_rate,
- debug_link_timer_short => '0',
- force_isolate => '0',
- force_loopback => '0',
- force_unidir => '0',
- rx_compensation_err => open,
- ctc_drop_flag => open,
- ctc_add_flag => open,
- an_link_ok => an_link_ok, --open,
- -- MAC interface
- tx_clk_125 => CLK_125_IN,
- tx_clock_enable_source => tx_clk_en,
- tx_clock_enable_sink => tx_clk_en,
- tx_d => pcs_txd, -- TX data from MAC
- tx_en => pcs_tx_en, -- TX data enable from MAC
- tx_er => pcs_tx_er, -- TX error from MAC
- rx_clk_125 => CLK_125_IN,
- rx_clock_enable_source => rx_clk_en,
- rx_clock_enable_sink => rx_clk_en,
- rx_d => pcs_rxd, -- RX data to MAC
- rx_dv => pcs_rx_en, -- RX data enable to MAC
- rx_er => pcs_rx_er, -- RX error to MAC
- col => open,
- crs => open,
- -- SerDes interface
- tx_data => sd_tx_data, -- TX data to SerDes
- tx_kcntl => sd_tx_kcntl(0), -- TX komma control to SerDes
- tx_disparity_cntl => sd_tx_correct_disp(0), -- idle parity state control in IPG (to SerDes)
- xmit_autoneg => xmit(0),
- serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream
- rx_data => sd_rx_data, -- RX data from SerDes
- rx_kcntl => sd_rx_kcntl(0), -- RX komma control from SerDes
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
- rx_disp_err => sd_rx_disp_error(0), -- RX disparity error from SerDes
- rx_cv_err => sd_rx_cv_error(0), -- RX code violation error from SerDes
- -- Autonegotiation stuff
- mr_an_complete => an_complete,
- mr_page_rx => mr_page_rx,
- mr_lp_adv_ability => mr_lp_adv_ability,
- mr_main_reset => mr_main_reset,
- mr_an_enable => mr_an_enable,
- mr_restart_an => mr_restart_an,
- mr_adv_ability => mr_adv_ability
- );
-
- MAC_AN_READY_OUT <= an_complete;
-
---- SIMPLE ---
- operational_rate <= b"10";
---- /SIMPLE ---
-
---- SIMPLE ---
- mr_main_reset <= rst_dual;
- mr_restart_an <= pulse;
- mr_an_enable <= link_rx_ready;
- mr_adv_ability <= x"0020";
-
- SYNC_PROC: process( CLK_125_IN )
- begin
- if( rising_edge(CLK_125_IN) ) then
- delay_q <= delay_q(6 downto 0) & link_rx_ready;
- end if;
- end process SYNC_PROC;
-
- pulse <= not delay_q(7) and delay_q(6);
---- /SIMPLE ---
-
- -- "Good" debugging pins
- debug(7 downto 0) <= pcs_txd;
- debug(15 downto 8) <= pcs_rxd;
- debug(16) <= pcs_tx_en;
- debug(17) <= pcs_tx_er;
- debug(18) <= pcs_rx_en;
- debug(19) <= pcs_rx_er;
- -- "Bad" debugging pins
- debug(20) <= pll_lol;
- debug(21) <= rx_cdr_lol;
- debug(22) <= rx_los_low;
- debug(23) <= sd_rx_cv_error(0);
- debug(24) <= lsm_status;
- debug(25) <= mr_main_reset;
- debug(26) <= mr_an_enable;
- debug(27) <= mr_restart_an;
- debug(28) <= mr_page_rx;
- debug(29) <= an_complete;
- debug(30) <= an_link_ok;
- debug(31) <= '0';
- debug(32) <= link_rx_ready;
- debug(33) <= link_tx_ready;
-
- MAC: tsmac_gbe
- port map(
- ----------------- clock and reset port declarations ------------------
- hclk => CLK_SYS_IN,
- txmac_clk => CLK_125_IN,
- rxmac_clk => CLK_125_IN,
- reset_n => synced_rst, -- was GSR_N
- ------------------- Input signals to the GMII ----------------
- rxd => pcs_rxd,
- rx_dv => pcs_rx_en,
- rx_er => pcs_rx_er,
- -------------------- Input signals to the CPU I/F -------------------
- haddr => tsm_haddr,
- hdatain => tsm_hdata,
- hcs_n => tsm_hcs_n,
- hwrite_n => tsm_hwrite_n,
- hread_n => tsm_hread_n,
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => MAC_TX_DATA_IN,
- tx_fifoavail => MAC_FIFOAVAIL_IN,
- tx_fifoeof => MAC_FIFOEOF_IN,
- tx_fifoempty => MAC_FIFOEMPTY_IN,
- tx_sndpaustim => x"0000",
- tx_sndpausreq => '0',
- tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full => MAC_RX_FIFOFULL_IN,
- ignore_pkt => '0',
- ---------------- Output signals from the GMII -----------------------
- txd => pcs_txd,
- tx_en => pcs_tx_en,
- tx_er => pcs_tx_er,
- ----------------- Output signals from the CPU I/F -------------------
- hdataout => open,
- hdataout_en_n => tsm_hdataout_en_n,
- hready_n => tsm_hready_n,
- cpu_if_gbit_en => open,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread => MAC_TX_READ_OUT,
- tx_discfrm => MAC_TX_DISCRFRM_OUT,
- tx_staten => MAC_TX_STAT_EN_OUT,
- tx_statvec => MAC_TX_STATS_OUT,
- tx_done => MAC_TX_DONE_OUT,
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error => MAC_RX_FIFO_ERR_OUT,
- rx_stat_vector => MAC_RX_STATS_OUT,
- rx_dbout => MAC_RX_DATA_OUT,
- rx_write => MAC_RX_WRITE_OUT,
- rx_stat_en => MAC_RX_STAT_EN_OUT,
- rx_eof => MAC_RX_EOF_OUT,
- rx_error => MAC_RX_ERROR_OUT
- );
-
- TSMAC_CONTROLLER : trb_net16_gbe_mac_control
- port map(
- CLK => CLK_SYS_IN,
- RESET => RESET,
- -- signals to/from main controller
- MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT,
- MC_RECONF_IN => MAC_RECONF_IN,
- MC_GBE_EN_IN => '1',
- MC_RX_DISCARD_FCS => '0',
- MC_PROMISC_IN => '1',
- MC_MAC_ADDR_IN => (others => '0'),
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => tsm_haddr,
- TSM_HDATA_OUT => tsm_hdata,
- TSM_HCS_N_OUT => tsm_hcs_n,
- TSM_HWRITE_N_OUT => tsm_hwrite_n,
- TSM_HREAD_N_OUT => tsm_hread_n,
- TSM_HREADY_N_IN => tsm_hready_n,
- TSM_HDATA_EN_N_IN => tsm_hdataout_en_n,
- -- Debug
- DEBUG_OUT => open
- );
-
-end architecture RTL;
+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_ARITH.all;
-use IEEE.std_logic_UNSIGNED.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-
-entity gbe_wrapper_single_5G is
- generic(
- DO_SIMULATION : integer range 0 to 1 := 0;
- INCLUDE_DEBUG : integer range 0 to 1 := 0;
- USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
- USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
- RX_PATH_ENABLE : integer range 0 to 1 := 1; --
- FIXED_SIZE_MODE : integer range 0 to 1 := 1; -- only for debugging
- INCREMENTAL_MODE : integer range 0 to 1 := 0; -- only for debugging
- FIXED_SIZE : integer range 0 to 65535 := 10; -- only for debugging
- FIXED_DELAY_MODE : integer range 0 to 1 := 1; -- only for debugging
- UP_DOWN_MODE : integer range 0 to 1 := 0; -- only for debugging
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; -- only for debugging
- FIXED_DELAY : integer range 0 to 16777215 := 16777215; -- only for debugging
- NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4; --
- LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111"
- );
- port(
- CLK_SYS_IN : in std_logic;
- CLK_125_IN : in std_logic;
- RESET : in std_logic;
- GSR_N : in std_logic;
- SD_PRSNT_N_IN : in std_logic;
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic; -- SFP disable
- SD_LED_GREEN_OUT : out std_logic;
- SD_LED_YELLOW_OUT : out std_logic;
- SD_LED_RED_OUT : out std_logic;
- --
- TRIGGER_IN : in std_logic; -- for debug purpose only
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
- CTS_CODE_IN : in std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- SlowControl
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
- ISSUE_REBOOT_OUT : out std_logic;
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- -- IP configuration
- BUS_IP_RX : in CTRLBUS_RX;
- BUS_IP_TX : out CTRLBUS_TX;
- -- Registers config
- BUS_REG_RX : in CTRLBUS_RX;
- BUS_REG_TX : out CTRLBUS_TX;
- -- Forwarder
- FWD_DST_MAC_IN : in std_logic_vector(47 downto 0) := (others => '0');
- FWD_DST_IP_IN : in std_logic_vector(31 downto 0) := (others => '0');
- FWD_DST_UDP_IN : in std_logic_vector(15 downto 0) := (others => '0');
- FWD_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- FWD_DATA_VALID_IN : in std_logic := '0';
- FWD_SOP_IN : in std_logic := '0';
- FWD_EOP_IN : in std_logic := '0';
- FWD_READY_OUT : out std_logic;
- FWD_FULL_OUT : out std_logic;
- --
- MAKE_RESET_OUT : out std_logic;
- --
- STATUS_OUT : out std_logic_vector(15 downto 0);
- DEBUG_OUT : out std_logic_vector(127 downto 0)
- );
-end entity gbe_wrapper_single_5G;
-
-architecture RTL of gbe_wrapper_single_5G is
- signal mac_ready_conf : std_logic;
- signal mac_reconf : std_logic;
- signal mac_an_ready : std_logic;
- signal mac_fifoavail : std_logic;
- signal mac_fifoeof : std_logic;
- signal mac_fifoempty : std_logic;
- signal mac_rx_fifofull : std_logic;
- signal mac_tx_data : std_logic_vector(7 downto 0);
- signal mac_tx_read : std_logic;
- signal mac_tx_discrfrm : std_logic;
- signal mac_tx_stat_en : std_logic;
- signal mac_tx_stats : std_logic_vector(30 downto 0);
- signal mac_tx_done : std_logic;
- signal mac_rx_fifo_err : std_logic;
- signal mac_rx_stats : std_logic_vector(31 downto 0);
- signal mac_rx_data : std_logic_vector(7 downto 0);
- signal mac_rx_write : std_logic;
- signal mac_rx_stat_en : std_logic;
- signal mac_rx_eof : std_logic;
- signal mac_rx_err : std_logic;
-
- signal cfg_gbe_enable : std_logic;
- signal cfg_ipu_enable : std_logic;
- signal cfg_mult_enable : std_logic;
- signal cfg_subevent_id : std_logic_vector(31 downto 0);
- signal cfg_subevent_dec : std_logic_vector(31 downto 0);
- signal cfg_queue_dec : std_logic_vector(31 downto 0);
- signal cfg_readout_ctr : std_logic_vector(23 downto 0);
- signal cfg_readout_ctr_valid : std_logic;
- signal cfg_insert_ttype : std_logic;
- signal cfg_max_sub : std_logic_vector(15 downto 0);
- signal cfg_max_queue : std_logic_vector(15 downto 0);
- signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
- signal cfg_max_single_sub : std_logic_vector(15 downto 0);
- signal cfg_additional_hdr : std_logic;
- signal cfg_soft_rst : std_logic;
- signal cfg_allow_rx : std_logic;
- signal cfg_max_frame : std_logic_vector(15 downto 0);
-
- signal dbg_hist, dbg_hist2 : hist_array;
-
- signal mac_0 : std_logic_vector(47 downto 0);
- signal cfg_max_reply : std_logic_vector(31 downto 0);
-
- signal mlt_cts_number : std_logic_vector(15 downto 0);
- signal mlt_cts_code : std_logic_vector(7 downto 0);
- signal mlt_cts_information : std_logic_vector(7 downto 0);
- signal mlt_cts_readout_type : std_logic_vector(3 downto 0);
- signal mlt_cts_start_readout : std_logic_vector(0 downto 0);
- signal mlt_cts_data : std_logic_vector(31 downto 0);
- signal mlt_cts_dataready : std_logic_vector(0 downto 0);
- signal mlt_cts_readout_finished : std_logic_vector(0 downto 0);
- signal mlt_cts_read : std_logic_vector(0 downto 0);
- signal mlt_cts_length : std_logic_vector(15 downto 0);
- signal mlt_cts_error_pattern : std_logic_vector(31 downto 0);
- signal mlt_fee_data : std_logic_vector(15 downto 0);
- signal mlt_fee_dataready : std_logic_vector(0 downto 0);
- signal mlt_fee_read : std_logic_vector(0 downto 0);
- signal mlt_fee_status : std_logic_vector(31 downto 0);
- signal mlt_fee_busy : std_logic_vector(0 downto 0);
-
- signal mlt_gsc_clk : std_logic;
- signal mlt_gsc_init_dataready : std_logic;
- signal mlt_gsc_init_data : std_logic_vector(15 downto 0);
- signal mlt_gsc_init_packet : std_logic_vector(2 downto 0);
- signal mlt_gsc_init_read : std_logic;
- signal mlt_gsc_reply_dataready : std_logic;
- signal mlt_gsc_reply_data : std_logic_vector(15 downto 0);
- signal mlt_gsc_reply_packet : std_logic_vector(2 downto 0);
- signal mlt_gsc_reply_read : std_logic;
- signal mlt_gsc_busy : std_logic;
-
- signal local_cts_number : std_logic_vector(15 downto 0);
- signal local_cts_code : std_logic_vector(7 downto 0);
- signal local_cts_information : std_logic_vector(7 downto 0);
- signal local_cts_readout_type : std_logic_vector(3 downto 0);
- signal local_cts_start_readout : std_logic;
- signal local_cts_readout_finished : std_logic;
- signal local_cts_status_bits : std_logic_vector(31 downto 0);
- signal local_fee_data : std_logic_vector(15 downto 0);
- signal local_fee_dataready : std_logic;
- signal local_fee_read : std_logic;
- signal local_fee_status_bits : std_logic_vector(31 downto 0);
- signal local_fee_busy : std_logic;
- signal dhcp_done : std_logic;
- signal all_links_ready : std_logic;
- signal monitor_rx_frames : std_logic_vector(31 downto 0);
- signal monitor_rx_bytes : std_logic_vector(31 downto 0);
- signal monitor_tx_frames : std_logic_vector(31 downto 0);
- signal monitor_tx_bytes : std_logic_vector(31 downto 0);
- signal monitor_tx_packets : std_logic_vector(31 downto 0);
- signal monitor_dropped : std_logic_vector(31 downto 0);
- signal sum_rx_frames : std_logic_vector(31 downto 0);
- signal sum_rx_bytes : std_logic_vector(31 downto 0);
- signal sum_tx_frames : std_logic_vector(31 downto 0);
- signal sum_tx_bytes : std_logic_vector(31 downto 0);
- signal sum_tx_packets : std_logic_vector(31 downto 0);
- signal sum_dropped : std_logic_vector(31 downto 0);
-
- signal busip0 : CTRLBUS_TX;
- signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic;
- --attribute nopad : string;
- --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true";
-
- signal dummy_event : std_logic_vector(15 downto 0);
- signal dummy_mode : std_logic;
- signal make_reset0 : std_logic := '0';
- signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
-
- signal cfg_autothrottle : std_logic;
- signal cfg_throttle_pause : std_logic_vector(15 downto 0);
-
- signal issue_reboot : std_logic;
- signal my_ip : std_logic_vector(127 downto 0);
- signal debug : std_logic_vector(127 downto 0);
-
-begin
-
--- assert hits if condition in brackets is true, or overall condition is false
--- assert not (dual_mode = 8) report "Note: DUAL with one slave port detected" severity note;
-
- assert not (NUMBER_OF_GBE_LINKS /= 1) report "Error: only one GbE link allowed" severity error;
- assert not (LINKS_ACTIVE /= b"0001") report "Error: no / wrong GbE interface selected" severity error;
- assert not (LINK_HAS_PING(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
- assert not (LINK_HAS_ARP(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
- assert not (LINK_HAS_DHCP(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
- assert not (LINK_HAS_READOUT(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
- assert not (LINK_HAS_SLOWCTRL(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
- assert not (LINK_HAS_FWD(3 downto 1) /= b"000") report "Error: only interface 0 supported" severity error;
-
- -- debug(127 downto 64) are local
- -- debug(63 downto 0) are media interface
- DEBUG_OUT <= debug;
-
- mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
-
- all_links_ready <= '1' when dhcp_done = '1' else '0';
-
- MAKE_RESET_OUT <= '1' when make_reset0 = '1' else '0';
-
- ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
-
- physical : entity work.gbe_med_interface_single_5G
- port map(
- RESET => RESET,
- GSR_N => GSR_N,
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_OUT => open, -- not needed
- CLK_125_IN => CLK_125_IN,
- CLK_125_RX_OUT => open, -- not needed
- MAC_READY_CONF_OUT => mac_ready_conf,
- MAC_RECONF_IN => mac_reconf,
- MAC_AN_READY_OUT => mac_an_ready,
- MAC_FIFOAVAIL_IN => mac_fifoavail,
- MAC_FIFOEOF_IN => mac_fifoeof,
- MAC_FIFOEMPTY_IN => mac_fifoempty,
- MAC_RX_FIFOFULL_IN => mac_rx_fifofull,
- MAC_TX_DATA_IN => mac_tx_data,
- MAC_TX_READ_OUT => mac_tx_read,
- MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm,
- MAC_TX_STAT_EN_OUT => mac_tx_stat_en,
- MAC_TX_STATS_OUT => mac_tx_stats,
- MAC_TX_DONE_OUT => mac_tx_done,
- MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err,
- MAC_RX_STATS_OUT => mac_rx_stats,
- MAC_RX_DATA_OUT => mac_rx_data,
- MAC_RX_WRITE_OUT => mac_rx_write,
- MAC_RX_STAT_EN_OUT => mac_rx_stat_en,
- MAC_RX_EOF_OUT => mac_rx_eof,
- MAC_RX_ERROR_OUT => mac_rx_err,
- SD_RXD_P_IN => SD_RXD_P_IN,
- SD_RXD_N_IN => SD_RXD_N_IN,
- SD_TXD_P_OUT => SD_TXD_P_OUT,
- SD_TXD_N_OUT => SD_TXD_N_OUT,
- SD_PRSNT_N_IN => SD_PRSNT_N_IN,
- SD_LOS_IN => SD_LOS_IN,
- SD_TXDIS_OUT => SD_TXDIS_OUT,
- STATUS_OUT => STATUS_OUT(7 downto 0),
- DEBUG_OUT => debug(63 downto 0) --open
- );
-
- STATUS_OUT(8) <= dhcp_done; -- DHCP has completed
- STATUS_OUT(15 downto 9) <= (others => '0');
-
- gbe_inst : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- INCLUDE_READOUT => LINK_HAS_READOUT(0),
- INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0),
- INCLUDE_DHCP => LINK_HAS_DHCP(0),
- INCLUDE_ARP => LINK_HAS_ARP(0),
- INCLUDE_PING => LINK_HAS_PING(0),
- INCLUDE_FWD => LINK_HAS_FWD(0),
- FRAME_BUFFER_SIZE => 1,
- READOUT_BUFFER_SIZE => 4,
- SLOWCTRL_BUFFER_SIZE => 2,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY => FIXED_DELAY)
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_IN => CLK_125_IN,
- CLK_RX_125_IN => CLK_125_IN,
- RESET => RESET,
- GSR_N => GSR_N,
- MY_MAC_IN => mac_0,
- DHCP_DONE_OUT => dhcp_done,
- MY_IP_OUT => my_ip(31 downto 0),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot,
- MAC_READY_CONF_IN => mac_ready_conf,
- MAC_RECONF_OUT => mac_reconf,
- MAC_AN_READY_IN => mac_an_ready,
- MAC_FIFOAVAIL_OUT => mac_fifoavail,
- MAC_FIFOEOF_OUT => mac_fifoeof,
- MAC_FIFOEMPTY_OUT => mac_fifoempty,
- MAC_RX_FIFOFULL_OUT => mac_rx_fifofull,
- MAC_TX_DATA_OUT => mac_tx_data,
- MAC_TX_READ_IN => mac_tx_read,
- MAC_TX_DISCRFRM_IN => mac_tx_discrfrm,
- MAC_TX_STAT_EN_IN => mac_tx_stat_en,
- MAC_TX_STATS_IN => mac_tx_stats,
- MAC_TX_DONE_IN => mac_tx_done,
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
- MAC_RX_STATS_IN => mac_rx_stats,
- MAC_RX_DATA_IN => mac_rx_data,
- MAC_RX_WRITE_IN => mac_rx_write,
- MAC_RX_STAT_EN_IN => mac_rx_stat_en,
- MAC_RX_EOF_IN => mac_rx_eof,
- MAC_RX_ERROR_IN => mac_rx_err,
- CTS_NUMBER_IN => mlt_cts_number,
- CTS_CODE_IN => mlt_cts_code,
- CTS_INFORMATION_IN => mlt_cts_information,
- CTS_READOUT_TYPE_IN => mlt_cts_readout_type,
- CTS_START_READOUT_IN => mlt_cts_start_readout(0),
- CTS_DATA_OUT => mlt_cts_data,
- CTS_DATAREADY_OUT => mlt_cts_dataready(0),
- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
- CTS_READ_IN => mlt_cts_read(0),
- CTS_LENGTH_OUT => mlt_cts_length,
- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern,
- FEE_DATA_IN => mlt_fee_data,
- FEE_DATAREADY_IN => mlt_fee_dataready(0),
- FEE_READ_OUT => mlt_fee_read(0),
- FEE_STATUS_BITS_IN => mlt_fee_status,
- FEE_BUSY_IN => mlt_fee_busy(0),
- GSC_CLK_IN => mlt_gsc_clk,
- GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready,
- GSC_INIT_DATA_OUT => mlt_gsc_init_data,
- GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet,
- GSC_INIT_READ_IN => mlt_gsc_init_read,
- GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready,
- GSC_REPLY_DATA_IN => mlt_gsc_reply_data,
- GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet,
- GSC_REPLY_READ_OUT => mlt_gsc_reply_read,
- GSC_BUSY_IN => mlt_gsc_busy,
- SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
- SLV_READ_IN => BUS_IP_RX.read,
- SLV_WRITE_IN => BUS_IP_RX.write,
- SLV_BUSY_OUT => busip0.nack,
- SLV_ACK_OUT => busip0.ack,
- SLV_DATA_IN => BUS_IP_RX.data,
- SLV_DATA_OUT => busip0.data,
- CFG_GBE_ENABLE_IN => cfg_gbe_enable,
- CFG_IPU_ENABLE_IN => cfg_ipu_enable,
- CFG_MULT_ENABLE_IN => cfg_mult_enable,
- CFG_MAX_FRAME_IN => cfg_max_frame,
- CFG_ALLOW_RX_IN => cfg_allow_rx,
- CFG_SOFT_RESET_IN => cfg_soft_rst,
- CFG_SUBEVENT_ID_IN => cfg_subevent_id,
- CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
- CFG_QUEUE_DEC_IN => cfg_queue_dec,
- CFG_READOUT_CTR_IN => cfg_readout_ctr,
- CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
- CFG_MAX_SUB_IN => cfg_max_sub,
- CFG_MAX_QUEUE_IN => cfg_max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
- CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
- CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
- CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
- CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
- FWD_DST_MAC_IN => FWD_DST_MAC_IN,
- FWD_DST_IP_IN => FWD_DST_IP_IN,
- FWD_DST_UDP_IN => FWD_DST_UDP_IN,
- FWD_DATA_IN => FWD_DATA_IN,
- FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
- FWD_SOP_IN => FWD_SOP_IN,
- FWD_EOP_IN => FWD_EOP_IN,
- FWD_READY_OUT => FWD_READY_OUT,
- FWD_FULL_OUT => FWD_FULL_OUT,
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames,
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets,
- MONITOR_DROPPED_OUT => monitor_dropped,
- MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
- MAKE_RESET_OUT => make_reset0
- );
-
- BUS_IP_TX.ack <= busip0.ack when rising_edge(CLK_SYS_IN);
- BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
- BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
-
- real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
- ipu_mult : entity work.gbe_ipu_multiplexer
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- LINK_HAS_READOUT => LINK_HAS_READOUT,
- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
- )
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- RESET => RESET,
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- MLT_CTS_NUMBER_OUT => mlt_cts_number,
- MLT_CTS_CODE_OUT => mlt_cts_code,
- MLT_CTS_INFORMATION_OUT => mlt_cts_information,
- MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
- MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
- MLT_CTS_DATA_IN => mlt_cts_data,
- MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
- MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
- MLT_CTS_READ_OUT => mlt_cts_read,
- MLT_CTS_LENGTH_IN => mlt_cts_length,
- MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
- MLT_FEE_DATA_OUT => mlt_fee_data,
- MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
- MLT_FEE_READ_IN => mlt_fee_read,
- MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
- MLT_FEE_BUSY_OUT => mlt_fee_busy,
- DEBUG_OUT => open
- );
- end generate real_ipu_gen;
-
- dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
- ipu_mult : entity work.gbe_ipu_multiplexer
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- LINK_HAS_READOUT => LINK_HAS_READOUT,
- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
- )
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- RESET => RESET,
- CTS_NUMBER_IN => local_cts_number,
- CTS_CODE_IN => local_cts_code,
- CTS_INFORMATION_IN => local_cts_information,
- CTS_READOUT_TYPE_IN => local_cts_readout_type,
- CTS_START_READOUT_IN => local_cts_start_readout,
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => local_cts_readout_finished,
- CTS_READ_IN => '1',
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => local_cts_status_bits,
- FEE_DATA_IN => local_fee_data,
- FEE_DATAREADY_IN => local_fee_dataready,
- FEE_READ_OUT => local_fee_read,
- FEE_STATUS_BITS_IN => local_fee_status_bits,
- FEE_BUSY_IN => local_fee_busy,
- MLT_CTS_NUMBER_OUT => mlt_cts_number,
- MLT_CTS_CODE_OUT => mlt_cts_code,
- MLT_CTS_INFORMATION_OUT => mlt_cts_information,
- MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
- MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
- MLT_CTS_DATA_IN => mlt_cts_data,
- MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
- MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
- MLT_CTS_READ_OUT => mlt_cts_read,
- MLT_CTS_LENGTH_IN => mlt_cts_length,
- MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
- MLT_FEE_DATA_OUT => mlt_fee_data,
- MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
- MLT_FEE_READ_IN => mlt_fee_read,
- MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
- MLT_FEE_BUSY_OUT => mlt_fee_busy,
- DEBUG_OUT => open
- );
-
- dummy : entity work.gbe_ipu_dummy
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- FIXED_DELAY => FIXED_DELAY
- )
- port map(
- clk => CLK_SYS_IN,
- rst => RESET,
- GBE_READY_IN => all_links_ready,
- CFG_EVENT_SIZE_IN => dummy_event,
- CFG_TRIGGERED_MODE_IN => '0',
- TRIGGER_IN => TRIGGER_IN,
- CTS_NUMBER_OUT => local_cts_number,
- CTS_CODE_OUT => local_cts_code,
- CTS_INFORMATION_OUT => local_cts_information,
- CTS_READOUT_TYPE_OUT => local_cts_readout_type,
- CTS_START_READOUT_OUT => local_cts_start_readout,
- CTS_DATA_IN => (others => '0'),
- CTS_DATAREADY_IN => '0',
- CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
- CTS_READ_OUT => open,
- CTS_LENGTH_IN => (others => '0'),
- CTS_ERROR_PATTERN_IN => local_cts_status_bits,
- -- Data payload interface
- FEE_DATA_OUT => local_fee_data,
- FEE_DATAREADY_OUT => local_fee_dataready,
- FEE_READ_IN => local_fee_read,
- FEE_STATUS_BITS_OUT => local_fee_status_bits,
- FEE_BUSY_OUT => local_fee_busy
- );
-
- -- handler for triggers
- DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
- port map(
- CLK_IPU => CLK_SYS_IN,
- CLK_GBE => CLK_125_IN,
- RESET => RESET,
- --Event information coming from CTS
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- slow control interface
- START_CONFIG_OUT => open,
- BANK_SELECT_OUT => open,
- CONFIG_DONE_IN => '1',
- DATA_GBE_ENABLE_IN => '1',
- DATA_IPU_ENABLE_IN => '1',
- MULT_EVT_ENABLE_IN => '1',
- MAX_SUBEVENT_SIZE_IN => (others => '0'),
- MAX_QUEUE_SIZE_IN => (others => '0'),
- MAX_SUBS_IN_QUEUE_IN => (others => '0'),
- MAX_SINGLE_SUB_SIZE_IN => (others => '0'),
- READOUT_CTR_IN => (others => '0'),
- READOUT_CTR_VALID_IN => '0',
- CFG_AUTO_THROTTLE_IN => '0',
- CFG_THROTTLE_PAUSE_IN => (others => '0'),
- -- PacketConstructor interface
- PC_WR_EN_OUT => open,
- PC_DATA_OUT => open,
- PC_READY_IN => '1',
- PC_SOS_OUT => open,
- PC_EOS_OUT => open,
- PC_EOQ_OUT => open,
- PC_SUB_SIZE_OUT => open,
- PC_TRIG_NR_OUT => open,
- PC_TRIGGER_TYPE_OUT => open,
- MONITOR_OUT => open,
- DEBUG_OUT => open
- );
- end generate dummy_ipu_gen;
-
- SETUP : gbe_setup
- port map(
- CLK => CLK_SYS_IN,
- RESET => RESET,
- -- interface to regio bus
- BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
- BUS_DATA_IN => BUS_REG_RX.data,
- BUS_DATA_OUT => BUS_REG_TX.data,
- BUS_WRITE_EN_IN => BUS_REG_RX.write,
- BUS_READ_EN_IN => BUS_REG_RX.read,
- BUS_ACK_OUT => BUS_REG_TX.ack,
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
- GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
- GBE_QUEUE_DEC_OUT => cfg_queue_dec,
- GBE_MAX_FRAME_OUT => cfg_max_frame,
- GBE_USE_GBE_OUT => cfg_gbe_enable,
- GBE_USE_TRBNET_OUT => cfg_ipu_enable,
- GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
- GBE_READOUT_CTR_OUT => cfg_readout_ctr,
- GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
- GBE_ALLOW_RX_OUT => cfg_allow_rx,
- GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
- GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
- GBE_SOFT_RESET_OUT => cfg_soft_rst,
- GBE_MAX_REPLY_OUT => cfg_max_reply,
- GBE_MAX_SUB_OUT => cfg_max_sub,
- GBE_MAX_QUEUE_OUT => cfg_max_queue,
- GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
- GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
- GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
- GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
- MONITOR_RX_BYTES_IN => sum_rx_bytes,
- MONITOR_RX_FRAMES_IN => sum_rx_frames,
- MONITOR_TX_BYTES_IN => sum_tx_bytes,
- MONITOR_TX_FRAMES_IN => sum_tx_frames,
- MONITOR_TX_PACKETS_IN => sum_tx_packets,
- MONITOR_DROPPED_IN => sum_dropped,
- MONITOR_SELECT_REC_IN => (others => '0'),
- MONITOR_SELECT_REC_BYTES_IN => (others => '0'),
- MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
- MONITOR_SELECT_SENT_IN => (others => '0'),
- MONITOR_SELECT_DROP_IN_IN => (others => '0'),
- MONITOR_SELECT_DROP_OUT_IN => (others => '0'),
- MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg,
- MONITOR_IP_IN => my_ip,
- DUMMY_EVENT_SIZE_OUT => dummy_event,
- DUMMY_TRIGGERED_MODE_OUT => dummy_mode,
- DATA_HIST_IN => (others => (others => '0')),
- SCTRL_HIST_IN => (others => (others => '0'))
- );
-
- NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
- GSC_INIT_DATAREADY_OUT <= '0';
- GSC_INIT_DATA_OUT <= (others => '0');
- GSC_INIT_PACKET_NUM_OUT <= (others => '0');
- GSC_REPLY_READ_OUT <= '1';
- mlt_gsc_clk <= (others => '0');
- mlt_gsc_init_read <= (others => '0');
- mlt_gsc_reply_dataready <= (others => '0');
- mlt_gsc_reply_data <= (others => '0');
- mlt_gsc_reply_packet <= (others => '0');
- mlt_gsc_busy <= (others => '0');
- end generate NOSCTRL_MAP_GEN;
-
- SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate
- ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '1') generate
- mlt_gsc_clk <= GSC_CLK_IN;
- GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready;
- GSC_INIT_DATA_OUT <= mlt_gsc_init_data;
- GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet;
- mlt_gsc_init_read <= GSC_INIT_READ_IN;
- mlt_gsc_reply_dataready <= GSC_REPLY_DATAREADY_IN;
- mlt_gsc_reply_data <= GSC_REPLY_DATA_IN;
- mlt_gsc_reply_packet <= GSC_REPLY_PACKET_NUM_IN;
- GSC_REPLY_READ_OUT <= mlt_gsc_reply_read;
- mlt_gsc_busy <= GSC_BUSY_IN;
- end generate ACTIVE_MAP_GEN;
-
- INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(0) = '0') generate
- mlt_gsc_clk <= '0';
- mlt_gsc_init_read <= '0';
- mlt_gsc_reply_dataready <= '0';
- mlt_gsc_reply_data <= (others => '0');
- mlt_gsc_reply_packet <= (others => '0');
- mlt_gsc_busy <= '0';
- end generate INACTIVE_MAP_GEN;
- end generate SCTRL_MAP_GEN;
-
- sum_rx_bytes <= monitor_rx_bytes;
- sum_rx_frames <= monitor_rx_frames;
- sum_tx_bytes <= monitor_tx_bytes;
- sum_tx_frames <= monitor_tx_frames;
- sum_tx_packets <= monitor_tx_packets;
- sum_dropped <= monitor_dropped;
-
-end architecture RTL;
jspc29 / trbnet.git / commitdiff