library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_api_base is
generic (
INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_SLAVE_READ_OUT : out std_logic;
+ CTRL_SEQNR_RESET : in std_logic;
+
-- Status and control port
STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
architecture trb_net16_api_base_arch of trb_net16_api_base is
- component trb_net16_dummy_fifo is
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic;
- EMPTY_OUT : out std_logic
- );
- end component;
-
- component trb_net16_fifo is
- generic (
- USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
- DEPTH : integer := 6
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);
- WRITE_ENABLE_IN : in std_logic;
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
- READ_ENABLE_IN : in std_logic;
- FULL_OUT : out std_logic;
- EMPTY_OUT : out std_logic
- );
- end component;
-
- component trb_net16_sbuf is
- generic (
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out STD_LOGIC;
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- SYN_READ_IN : in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER : out STD_LOGIC
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := c_YES;
- --even when 0, ERROR_PACKET_IN is used for automatic replys
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT : out std_logic;
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN : in std_logic;
-
- INT_DATAREADY_IN : in std_logic;
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT : out std_logic;
-
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net_sbuf is
- generic (
- DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH;
- VERSION: integer := SBUF_VERSION);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
- end component;
-
-- signals for the APL to INT fifo:
signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0);
signal saved_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
signal current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
-signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal last_fifo_to_apl_read : std_logic;
-signal last_fifo_to_int_read : std_logic;
+ signal saved_fifo_to_int_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal saved_fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal last_fifo_to_apl_read : std_logic;
+ signal last_fifo_to_int_read : std_logic;
signal state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0);
-- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic;
INT_SLAVE_PACKET_NUM_OUT <= (others => '0');
end generate;
- STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
- STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
- STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT;
- STAT_FIFO_TO_INT(7) <= buf_INT_MASTER_DATAREADY_OUT;
- STAT_FIFO_TO_INT(8) <= INT_MASTER_READ_IN;
- STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0);
- STAT_FIFO_TO_INT(12) <= fifo_to_int_read;
- STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before;
- STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
- STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
- STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT;
- STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free;
- STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before;
- STAT_FIFO_TO_INT(19) <= slave_running;
- STAT_FIFO_TO_INT(20) <= buf_APL_RUN_OUT;
- STAT_FIFO_TO_INT(21) <= master_running;
- STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;
- STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT;
- STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
- STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
-
- STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
- STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
- STAT_FIFO_TO_APL(7 downto 4) <= (others => '0');
- STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0);
- STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT;
- STAT_FIFO_TO_APL(11) <= fifo_to_apl_read;
- STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN;
- STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT;
- STAT_FIFO_TO_APL(14) <= fifo_to_apl_full;
- STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty;
- --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
---------------------------------------
-- a sbuf (to_int direction)
state_to_int <= IDLE;
end if;
send_trm_wrong_addr <= '0';
- sequence_counter <= (others => '0');
fifo_was_not_empty <= '0';
elsif CLK_EN = '1' then
state_to_apl <= next_state_to_apl;
state_to_int <= next_state_to_int;
send_trm_wrong_addr <= next_send_trm_wrong_addr;
- sequence_counter <= next_sequence_counter;
fifo_was_not_empty <= next_fifo_was_not_empty;
end if;
end if;
end process;
+ PROC_SEQ_CNT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or CTRL_SEQNR_RESET = '1' then
+ sequence_counter <= (others => '0');
+ else
+ sequence_counter <= next_sequence_counter;
+ end if;
+ end if;
+ end process;
+
----------------------------------------
---
----------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
end process;
- --get target address from active APL
- gentarget1: if API_TYPE = 1 generate
- combined_header_F1 <= APL_TARGET_ADDRESS_IN;
- end generate;
- --save target address for passive api
- gentarget0: if API_TYPE = 0 generate
- reg_hdr_f1: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- combined_header_F1 <= (others => '1');
- elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_long_packet_num_out = c_F0 and CLK_EN = '1' then
- combined_header_F1 <= fifo_to_apl_data_out;
- end if;
- end if;
- end process;
- end generate;
- -- combine the next header
- combined_header_F0 <= APL_MY_ADDRESS_IN;
- combined_header_F2 <= APL_LENGTH_IN;
- combined_header_F3(15 downto 14) <= (others => '0'); -- LAY
- combined_header_F3(13 downto 12) <= (others => '0'); -- VERS
- combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR
- combined_header_F3(3 downto 0) <= APL_DTYPE_IN;
- combined_trailer_F0 <= (others => '0');
- combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16);
- combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else
- APL_ERROR_PATTERN_IN(15 downto 0);
- combined_trailer_F3(15 downto 14) <= (others => '0'); -- res.
- combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS
- combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR
- combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN;
+
+
+---------------------------------------------------------------------
+--Connection to FIFOs
+---------------------------------------------------------------------
+
-- connect Transmitter port
fifo_to_int_data_in <= APL_DATA_IN;
fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0);
fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full);
- APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
+ APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
-- connect receiver
fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN(2) & INT_SLAVE_PACKET_NUM_IN(0);
INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT;
+---------------------------------------------------------------------
+--Running Signals
+---------------------------------------------------------------------
+
RUN_OUT_gen : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
- REG3 : process(CLK)
+---------------------------------------------------------------------
+--Header & Trailer Words
+---------------------------------------------------------------------
+
+
+ --get target address from active APL
+ gentarget1: if API_TYPE = 1 generate
+ combined_header_F1 <= APL_TARGET_ADDRESS_IN;
+ end generate;
+
+ --save target address for passive api
+ gentarget0: if API_TYPE = 0 generate
+ reg_hdr_f1: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ combined_header_F1 <= (others => '1');
+ elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_long_packet_num_out = c_F0 and CLK_EN = '1' then
+ combined_header_F1 <= fifo_to_apl_data_out;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ -- combine the next header
+ combined_header_F0 <= APL_MY_ADDRESS_IN;
+ combined_header_F2 <= APL_LENGTH_IN;
+ combined_header_F3(15 downto 14) <= (others => '0'); -- LAY
+ combined_header_F3(13 downto 12) <= (others => '0'); -- VERS
+ combined_header_F3(11 downto 4) <= sequence_counter; -- SEQNR
+ combined_header_F3(3 downto 0) <= APL_DTYPE_IN;
+ combined_trailer_F0 <= (others => '0');
+ combined_trailer_F1 <= APL_ERROR_PATTERN_IN(31 downto 16);
+ combined_trailer_F2 <= APL_ERROR_PATTERN_IN(15 downto 1) & endpoint_reached when API_TYPE = c_API_PASSIVE else
+ APL_ERROR_PATTERN_IN(15 downto 0);
+ combined_trailer_F3(15 downto 14) <= (others => '0'); -- res.
+ combined_trailer_F3(13 downto 12) <= (others => '0'); -- VERS
+ combined_trailer_F3(11 downto 4) <= sequence_counter; -- SEQNR
+ combined_trailer_F3(3 downto 0) <= APL_DTYPE_IN;
+
+ PROC_REG3 : process(CLK)
begin
if rising_edge(CLK) then
if update_registered_trailer = '1' then
end if;
end process;
---for simulation only
-
+---------------------------------------------------------------------
+--Decode FSM states
+---------------------------------------------------------------------
- process(state_to_apl)
+ process(state_to_apl)
begin
case state_to_apl is
when sa_IDLE => state_bits_to_apl <= "000";
when others => state_bits_to_apl <= "111";
end case;
end process;
+
process(state_to_int)
begin
case state_to_int is
end case;
end process;
+---------------------------------------------------------------------
+--Debugging & Status Signals
+---------------------------------------------------------------------
+
+ STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
+ STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
+ STAT_FIFO_TO_INT(6 downto 4) <= buf_INT_MASTER_PACKET_NUM_OUT;
+ STAT_FIFO_TO_INT(7) <= buf_INT_MASTER_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(8) <= INT_MASTER_READ_IN;
+ STAT_FIFO_TO_INT(11 downto 9) <= fifo_to_int_data_out(2 downto 0);
+ STAT_FIFO_TO_INT(12) <= fifo_to_int_read;
+ STAT_FIFO_TO_INT(13) <= fifo_to_int_read_before;
+ STAT_FIFO_TO_INT(14) <= fifo_to_int_full;
+ STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
+ STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free;
+ STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before;
+ STAT_FIFO_TO_INT(19) <= slave_running;
+ STAT_FIFO_TO_INT(20) <= buf_APL_RUN_OUT;
+ STAT_FIFO_TO_INT(21) <= master_running;
+ STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;
+ STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT;
+ STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
+ STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl;
+
+ STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
+ STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
+ STAT_FIFO_TO_APL(7 downto 4) <= (others => '0');
+ STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0);
+ STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT;
+ STAT_FIFO_TO_APL(11) <= fifo_to_apl_read;
+ STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN;
+ STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT;
+ STAT_FIFO_TO_APL(14) <= fifo_to_apl_full;
+ STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty;
+ --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
+ STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
+
end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+library work;
+use work.trb_net_std.all;
+
+package trb_net_components is
+
+ component trb_net16_dummy_fifo is
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic;
+ EMPTY_OUT : out std_logic
+ );
+ end component;
+
+ component trb_net16_fifo is
+ generic (
+ USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+ DEPTH : integer := 6
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic;
+ EMPTY_OUT : out std_logic
+ );
+ end component;
+
+ component trb_net16_sbuf is
+ generic (
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out STD_LOGIC;
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
+ SYN_READ_IN : in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER : out STD_LOGIC
+ );
+ end component;
+
+ component trb_net16_term is
+ generic (
+ USE_APL_PORT : integer range 0 to 1 := c_YES;
+ --even when 0, ERROR_PACKET_IN is used for automatic replys
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
+ --if secure_mode is not used, apl must provide error pattern and dtype until
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ INT_DATAREADY_OUT : out std_logic;
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_IN : in std_logic;
+
+ INT_DATAREADY_IN : in std_logic;
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_OUT : out std_logic;
+
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net_sbuf is
+ generic (
+ DATA_WIDTH : integer := 18;
+ VERSION: integer := std_SBUF_VERSION);
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+ SYN_READ_IN: in STD_LOGIC;
+ STAT_BUFFER: out STD_LOGIC
+ );
+ end component;
+
+
+end package;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff