with specialized adaptor or interface boards. This way a wide range of data acquisition applications
is possible. The FPGAs have an internal flash storage for its design configuration.
When the FPGA is powered or reset, it retrieves and loads the configuration from this flash.
-
The TRB3 hardware platform and the associated software framework are developed and maintained
by the TRB collaboration.
+
In this set-up, the TRB3 is used as a network controlled data readout board for the MIMOSA26 MAPS.
+The connection to the converter board is achieved by attaching an ADA-AddOn board to one
+of the peripheral extension connectors. This board is a passive adaptor that provides two 80 pin
+flat cable connectors, compatible with the connector on the converter board.
+This way up to two\footnote{?? not implemented yet, only one converter board can be operated
+due to the roc code ??} converter boards can be operated with one peripheral FPGA.
\subsection{FPGA design entities (draft!)}
The FPGA design is internally divided into individual modules, the so called entities.
to a data acquisition computer via TRBnet where the data is finally stored.
\subsubsection{JTAG controller}
\label{sec:JTAG_controller}
-While the ROC is concerned with the data coming from the sensor, the JTAG controller\footnote{
-Developed by Bertram Neuman during his master's thesis} handles the
+While the ROC is concerned with the data coming from the sensor, the JTAG
+controller\footnote{Developed by Bertram Neuman during his master's thesis} handles the
communication to the sensor. The MIMOSA26 sensor possesses a JTAG interface (a synchronous serial
data interface) that provides access to the settings registers of the chip.
Multiple sensors can have their JTAG interfaces connected in series (comparable to shift registers)