first version of DS TRB5sc

diff --git a/template/config.vhd b/template/config.vhd
index 5a9fa379712722616448ab30d96f12e458d93a96..9b49cdc88ef33ec21a5bda6c6e588b060f5ab0d2 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -8,11 +8,19 @@ package config is
 ------------------------------------------------------------------------------
 --Begin of design configuration
 ------------------------------------------------------------------------------
---set to 0 for backplane serdes, set to 1 for SFP serdes
-  constant SERDES_NUM             : integer := 1;
+-- FPGA type    
+  constant FPGA_TYPE              : integer  := 5;  --3: ECP3, 5: ECP5
+
+  constant FPGA_SIZE              : string   := "85KUM";
+
+-- Link speed
+  constant LINK_SPEED             : integer  := 125; -- 125: 1.25Gbps, 200: 2.00Gbps
+
+-- 0 = backplane, 1 = SFP
+  constant SERDES_NUM             : integer  := 1;
+  
 
 --TDC settings
-  constant FPGA_TYPE               : integer  := 5;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
   constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5;  -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 2;  --the nearest power of two, for convenience reasons 
@@ -55,8 +63,6 @@ package config is
     constant TRIG_GEN_INPUT_NUM     : integer  := 32;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 4;
     constant MONITOR_INPUT_NUM      : integer  := 32;        
-
-    constant FPGA_SIZE : string := "85KUM";
     
 ------------------------------------------------------------------------------
 --End of design configuration

diff --git a/template/config_compile_gsi.pl b/template/config_compile_gsi.pl
index ded4aa601ea5fa6106fb0f56f9f435fe1c1b6b6e..dfac2f8e14fac89101603082d72e154bc4dbab07 100644 (file)
--- a/template/config_compile_gsi.pl
+++ b/template/config_compile_gsi.pl
@@ -14,7 +14,7 @@ nodelist_file                => '../nodelist.txt',
 pinout_file                  => 'trb5sc_tdc',
 par_options                  => '../par.p2t',
     
-include_TDC                  => 1,
+include_TDC                  => 0,
 include_GBE                  => 0,
 
 firefox_open                 => 0,

diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj
index b420c9d1d3622add2ba48060cba0710d4eeaab20..612f7662db1c9204e24d250da0ace2ad49cc703b 100644 (file)
--- a/template/trb5sc_template.prj
+++ b/template/trb5sc_template.prj
@@ -123,37 +123,30 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 
 #Media interface
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd"
 
 
 #########################################
 #channel 0, backplane
-#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"      
-#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_200M/serdes_sync_0_200M.vhd"      
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_125M/serdes_sync_0_125M.vhd"      
 
 #channel 1, SFP
-#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
-#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1_200M/serdes_sync_0_200M.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1_125M/serdes_sync_0_125M.vhd"
 ##########################################
 
-
-#########################################
-#channel 0, backplane
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"      
-
-#channel 1, SFP
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
-##########################################
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
-add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_200M.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_125M.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_200M_softlogic.v"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_125M_softlogic.v"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
 

diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd
index adc0edaa5c7de5b79affad963e19890c824e76e5..30fd2ab4ee7a1efbf534bb0e26c2d65763958b6d 100644 (file)
--- a/template/trb5sc_template.vhd
+++ b/template/trb5sc_template.vhd
@@ -8,7 +8,7 @@ use work.config.all;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
-use work.med_sync_define.all;
+use work.med_sync_define_RS.all;
 
 entity trb5sc_template is
   port(
@@ -131,6 +131,17 @@ architecture arch of trb5sc_template is
   
   signal link_stat_in_reg : std_logic;
 
+  signal link_clock                  : std_logic;
+  signal init_quad                   : std_logic;
+  signal master_clk_i                : std_logic;
+  signal tx_pll_lol_dual_a           : std_logic;
+  signal tx_clk_avail_i              : std_logic;
+  signal word_sync_i                 : std_logic;
+  signal tx_pcs_rst_i                : std_logic;
+  signal link_tx_ready_i             : std_logic;
+  signal debug_i                     : std_logic_vector(31 downto 0);
+  signal tx_fsm_state                : std_logic_vector(3 downto 0);
+  
 begin
 
 trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);
@@ -154,46 +165,93 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
       DEBUG_OUT      => debug_clock_reset
     );
 
-  THE_CAL_PLL : entity work.pll_in125_out50
-    port map(
-      CLKI  => CLK_125,
-      CLKOP => clk_cal
-    );
+  init_quad <= not GSR_N;
+    
+  -- select link speed, wrong values are catched in media interface
+  link_clock <= CLK_125      when (LINK_SPEED = 125) else
+                clk_full_osc when (LINK_SPEED = 200) else
+                '0';
+
+--  THE_CAL_PLL : entity work.pll_in125_out50
+--    port map(
+--      CLKI  => CLK_125,
+--      CLKOP => clk_cal
+--    );
+
+--  clk_cal <= clk_sys; -- BUG
 
 -------------------------------------------------------------------------------
 -- TrbNet Uplink
 -------------------------------------------------------------------------------
-  THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
+  THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_RS
     generic map(
       SERDES_NUM    => 0,
-      IS_SYNC_SLAVE => c_YES
+      IS_MODE       => c_IS_SLAVE
     )
     port map(
-      CLK_REF_FULL      => clk_full_osc,
-      CLK_INTERNAL_FULL => clk_full_osc,
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear_i,
-      --Internal Connection
-      MEDIA_MED2INT     => med2int(0),
-      MEDIA_INT2MED     => int2med(0),
-      --Sync operation
-      RX_DLM            => open,
-      RX_DLM_WORD       => open,
-      TX_DLM            => open,
-      TX_DLM_WORD       => open,
+      -- Clocks and reset
+      CLK_REF_FULL       => link_clock,
+      SYSCLK             => clk_sys,
+      CLEAR              => init_quad,
+      RESET              => reset_i,
+      -- Media Interface TX/RX
+      MEDIA_MED2INT      => med2int(0),
+      MEDIA_INT2MED      => int2med(0),
+      -- komma operation
+      RX_DLM_OUT         => open,
+      RX_DLM_WORD_OUT    => open,
+      TX_DLM_IN          => '0',
+      TX_DLM_WORD_IN     => x"00",
+      RX_RST_OUT         => open,
+      RX_RST_WORD_OUT    => open,
+      TX_RST_IN          => '0',
+      TX_RST_WORD_IN     => x"00",
+      -- phase measurement
+      PING_OUT           => open,
+      PONG_OUT           => open,
+      PONG_CLK_OUT       => open,
+      -- sync operation
+      WORD_SYNC_IN       => word_sync_i,
+      WORD_SYNC_OUT      => word_sync_i,
+      MASTER_CLK_IN      => master_clk_i,
+      MASTER_CLK_OUT     => master_clk_i,
+      LINK_TX_NULL_IN    => '0',
+      LINK_RX_NULL_OUT   => open,
+      TX_PLL_LOL_OUT     => tx_pll_lol_dual_a,
+      TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
+      TX_PCS_RST_IN      => tx_pcs_rst_i,
+      SYNC_TX_PLL_IN     => '0',
+      LINK_TX_READY_IN   => link_tx_ready_i,
+      DISABLE_LINK_IN    => '0',
+      WAP_REQUESTED_IN   => x"0",
       --SFP Connection
-      SD_PRSNT_N_IN     => sfp_prsnt_i,
-      SD_LOS_IN         => sfp_los_i,
-      SD_TXDIS_OUT      => sfp_txdis_i,
+      SD_PRSNT_N_IN      => sfp_prsnt_i,
+      SD_LOS_IN          => sfp_los_i,
+      SD_TXDIS_OUT       => sfp_txdis_i,
       --Control Interface
-      BUS_RX            => bussci_rx,
-      BUS_TX            => bussci_tx,      
+      BUS_RX             => bussci_rx,
+      BUS_TX             => bussci_tx,
       -- Status and control port
-      STAT_DEBUG    => med_stat_debug(63 downto 0),
-      CTRL_DEBUG    => open
+      STAT_DEBUG         => med_stat_debug(63 downto 0),
+      CTRL_DEBUG         => open,
+      DEBUG_OUT          => debug_i
     );
 
+  THE_MAIN_TX_RST: main_tx_reset_RS
+  port map (
+    CLEAR                => init_quad,
+    CLK_REF              => link_clock,
+    TX_PLL_LOL_QD_A_IN   => tx_pll_lol_dual_a,
+    TX_PLL_LOL_QD_B_IN   => '0',
+    TX_PLL_LOL_QD_C_IN   => '0',
+    TX_PLL_LOL_QD_D_IN   => '0',
+    TX_CLOCK_AVAIL_IN    => tx_clk_avail_i,
+    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i,
+    SYNC_TX_QUAD_OUT     => open,
+    LINK_TX_READY_OUT    => link_tx_ready_i,
+    STATE_OUT            => tx_fsm_state
+  );
+
   gen_sfp_con : if SERDES_NUM = 1 generate
     sfp_los_i   <= SFP_LOS;
     sfp_prsnt_i <= SFP_MOD_0; 
@@ -204,7 +262,23 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
     sfp_prsnt_i  <= BACK_GPIO(1); 
     BACK_GPIO(0) <= sfp_txdis_i;
   end generate;  
-        
+
+  HDR_IO(15 downto 12) <= tx_fsm_state;
+  HDR_IO(11)           <= init_quad;
+  HDR_IO(10)           <= clear_i;
+  HDR_IO(9)            <= tx_clk_avail_i;
+  HDR_IO(8)            <= tx_pll_lol_dual_a;
+  HDR_IO(7 downto 0)   <= debug_i(15 downto 8);
+  
+  LED(8)         <= not '1';
+  LED(7)         <= not debug_i(2);
+  LED(6)         <= not debug_i(1);
+  LED(5)         <= not debug_i(0);
+  LED(4)         <= not tx_clk_avail_i;
+  LED(3)         <= not tx_pll_lol_dual_a;
+  LED(2)         <= not reset_i;
+  LED(1)         <= not clear_i;
+
 -------------------------------------------------------------------------------
 -- Endpoint
 -------------------------------------------------------------------------------
@@ -299,7 +373,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
       SPI_MISO_IN       => spi_miso,
       SPI_CLK_OUT       => spi_clk,
       --Header
-      HEADER_IO         => HDR_IO(9 downto 0),
+      HEADER_IO         => open, --HDR_IO(9 downto 0),
       ADDITIONAL_REG(0) => led_off,
       --LCD
       LCD_DATA_IN       => (others => '0'),
@@ -355,7 +429,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
 
   assert     DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
 
-  HDR_IO(15 downto 10) <= (others => '0');
+  --HDR_IO(15 downto 10) <= (others => '0');
   TEST(13 downto 1)    <= (others => '0');
   TEST(14) <= flash_ncs_i;
   FLASH_NCS <= flash_ncs_i;
@@ -366,7 +440,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
   LED_SFP_GREEN  <= not med2int(0).stat_op(9) or led_off;
   LED_SFP_RED    <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
   LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
-  LED            <= x"F0";
+--  LED            <= x"F0";
   LED_RJ_GREEN   <= "00";
   LED_RJ_RED     <= "11";
   LED_EXT_CLOCK  <= IN_SELECT_EXT_CLOCK or led_off;
@@ -403,9 +477,9 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
 -------------------------------------------------------------------------------
 -- No trigger/data endpoint included
 -------------------------------------------------------------------------------
--- readout_tx(0).data_finished <= '1';
--- readout_tx(0).data_write    <= '0';
--- readout_tx(0).busy_release  <= '1';    
+--  readout_tx(0).data_finished <= '1';
+--  readout_tx(0).data_write    <= '0';
+--  readout_tx(0).busy_release  <= '1';    
   
 end architecture;