second channel of flexi pcs txk signal was wrong

diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd
index 4910dee63d98348ddda5b5f176a8a4d15f13e417..e7c006ee42517eebaca68e555be49d9edf4cb4ca 100644 (file)
--- a/optical_link/hub.vhd
+++ b/optical_link/hub.vhd
@@ -425,7 +425,7 @@ architecture hub of hub is
   signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
   signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
   signal global_reset_i : std_logic;
-  signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
+  signal global_reset_cnt : std_logic_vector(3 downto 0);
   signal registered_signals : std_logic_vector(7 downto 0);
   signal hub_register_0a_i_synch : std_logic_vector(7 downto 0);
   signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
@@ -476,7 +476,7 @@ begin
         tx_rst_0        => '0',
         rx_rst_0        => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0),
         txd_0           => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--
-        tx_k_0          => tx_k_i(bit_index*8+1 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
+        tx_k_0          => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
         tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),
         tx_disp_sel_0   => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00",
         tx_crc_init_0   => "00",
@@ -491,7 +491,7 @@ begin
         tx_rst_1        => '0',
         rx_rst_1        => rx_rst_i(1+bit_index*4),
         txd_1           => txd_synch_i(31+bit_index*64 downto 16+bit_index*64),
-        tx_k_1          => tx_k_i(bit_index*8+1 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
+        tx_k_1          => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
         tx_force_disp_1      => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8),
         tx_disp_sel_1        => "00",
         tx_crc_init_1        => "00",