signal int2med : int2med_array_t(0 to INTERFACE_NUM); -- 1 more due to uplink
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx, buscts_rx, buscrireg_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdccal_tx, buscts_tx, buscrireg_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx , bustdccal_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx : CTRLBUS_TX;
signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
generic map (
- INCLUDE_READOUT => '1',
+ INCLUDE_READOUT => '0',
READOUT_BUFFER_SIZE => 4
)
port map (
BUS_REG_RX => buscrireg_rx,
BUS_REG_TX => buscrireg_tx,
-
+
+ BUS_DBG_RX => busCriDatadbgReg_rx,
+ BUS_DBG_TX => busCriDatadbgReg_tx,
+
TIMER_TICKS_IN(0) => timer.tick_us,
TIMER_TICKS_IN(1) => timer.tick_ms
);
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 10,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"e000",
- 7 => x"ef00", 8 => x"a000", 9 => x"8300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 12,
- 7 => 8 , 8 => 11, 9 => 8, others => 0),
+ PORT_NUMBER => 11,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"e000",
+ 7 => x"ef00", 8 => x"a000", 9 => x"8300", 10 => x"e100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 4,
+ 7 => 8 , 8 => 11, 9 => 8, 10 => 8, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(7) => busdebug_rx,
BUS_RX(8) => buscts_rx,
BUS_RX(9) => buscrireg_rx,
+ BUS_RX(10)=> busCriDatadbgReg_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bustc_tx,
BUS_TX(2) => bussci_tx(0),
BUS_TX(7) => busdebug_tx,
BUS_TX(8) => buscts_tx,
BUS_TX(9) => buscrireg_tx,
+ BUS_TX(10)=> busCriDatadbgReg_tx,
STAT_DEBUG => open
);
BUS_REG_RX : in CTRLBUS_RX;
BUS_REG_TX : out CTRLBUS_TX;
+ BUS_DBG_RX : in CTRLBUS_RX;
+ BUS_DBG_TX : out CTRLBUS_TX;
+
TIMER_TICKS_IN : in std_logic_vector( 1 downto 0)
);
end entity;
signal cfg_soft_rst : std_logic;
signal cfg_allow_rx : std_logic;
signal cfg_max_frame : std_logic_vector(15 downto 0);
-
+
+ --DEBUG SIGNALS:
+ signal debug_resp_control : std_logic_vector(63 downto 0);
+ signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0);
+ signal last_cts_readout_finished, last_cts_readout_start : std_logic;
begin
STAT_ADDR_OUT => open,
STAT_DATA_RDY_OUT => open,
STAT_DATA_ACK_IN => '0',
- DEBUG_OUT => open,--MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
+ DEBUG_OUT => debug_resp_control,--MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
-- END OF INTERFACE
-- CTS interface
THE_IOBUF_1 : trb_net16_term_buf
port map (
-- Misc
- CLK => CLK ,
+ CLK => CLK,
RESET => reset_i_mux_io,
CLK_EN => CLK_EN,
-- Media direction port
MED_READ_OUT => io_read_out(1)
);
- --Clean Data Output
- CTS_READOUT_FINISHED_OUT <= '0';
- CTS_STATUS_BITS_OUT <= (others => '0');
- FEE_READ_OUT <= '0';
+ --Terminate Data
+ THE_TrbNetData : entity work.trb_net16_gbe_ipu_interface
+ generic map(
+ DO_SIMULATION => 0
+ )
+ port map (
+ CLK_IPU => CLK,
+ CLK_GBE => CLK,
+ RESET => reset_i_mux_io,
+
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_READ_IN => '1',
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ -- slow control interface
+ START_CONFIG_OUT => open,
+ BANK_SELECT_OUT => open,
+ CONFIG_DONE_IN => '1',
+ DATA_GBE_ENABLE_IN => '1',
+ DATA_IPU_ENABLE_IN => '0', -- never used in code
+ MULT_EVT_ENABLE_IN => '0',
+ MAX_SUBEVENT_SIZE_IN => x"ffff",
+ MAX_QUEUE_SIZE_IN => x"ffff",
+ MAX_SUBS_IN_QUEUE_IN => x"ffff",
+ MAX_SINGLE_SUB_SIZE_IN => x"ffff",
+ READOUT_CTR_IN => x"000000",
+ READOUT_CTR_VALID_IN => '0',
+ CFG_AUTO_THROTTLE_IN => '0',
+ CFG_THROTTLE_PAUSE_IN => (others => '0'),
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => open,
+ PC_DATA_OUT => open,
+ PC_READY_IN => '1',
+ PC_SOS_OUT => open,
+ PC_EOS_OUT => open,
+ PC_EOQ_OUT => open,
+ PC_SUB_SIZE_OUT => open,
+ PC_TRIG_NR_OUT => open,
+ PC_TRIGGER_TYPE_OUT => open,
+ MONITOR_OUT => open,
+ DEBUG_OUT => open
+ );
+-- --Clean Data Output
+-- CTS_READOUT_FINISHED_OUT <= '1';
+-- CTS_STATUS_BITS_OUT <= (others => '0');
+-- FEE_READ_OUT <= '0'; --maybe high if idle?
end generate no_readout_gen;
SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2
);
+
+
+THE_CTS_READOUT_FINISHED_CNT : process begin
+ wait until rising_edge(CLK);
+
+ if RESET = '1' then
+ last_cts_readout_finished <= '0';
+ last_cts_readout_start <= '0';
+ readout_finished_cnt <= 0;
+ readout_start_cnt <= 0;
+ else
+ last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT;
+ last_cts_readout_start <= CTS_START_READOUT_IN;
+ if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then
+ readout_finished_cnt <= readout_finished_cnt + 1;
+ end if;
+
+ if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then
+ readout_start_cnt <= readout_start_cnt + 1;
+ end if;
+ end if;
+end process;
+
+
+THE_CRI_READOUT_DEBUG : process begin
+ wait until rising_edge(CLK);
+ BUS_DBG_TX.ack <= '0';
+ BUS_DBG_TX.nack <= '0';
+ BUS_DBG_TX.unknown <= '0';
+
+ if BUS_DBG_RX.read = '1' then
+ if BUS_DBG_RX.addr(7 downto 0) = x"00" then
+ BUS_DBG_TX.data <= debug_resp_control(31 downto 0);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"01" then
+ BUS_DBG_TX.data <= debug_resp_control(63 downto 32);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"02" then
+ BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN;
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"03" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt);
+ BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable;
+ BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable;
+ BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable;
+ BUS_DBG_TX.data(31 downto 28) <= "0000";
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ elsif BUS_DBG_RX.write = '1' then
+ --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
+ -- MUX_cal_sw <= BUS_DBG_RX.data(0);
+ --end if;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+ end process;
+
end architecture;
jspc29 / dirich.git / commitdiff