downstream: no tx-fifo for sync operation but does have rx-fifo for reply (async)
upstream: no rx-fifo for sync operation but does have tx-fifo for reply (asynx)
Clock domains now separated.
SOURCE:
tx-clock=fabric-clock (200MHz). THis is the origin of SODA/master-clock
rx-clock=fabric clock. Phase differences taken care of by rx-fifo
CLIENT:
rx-clock=reconstructed clock
tx-clock=rx-clock
<Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="source/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/soda_source.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
+ <Source name="source/med_ecp3_sfp_sync_down.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_downstream.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
+ <Options/>
+ </Source>
+ <Source name="source/serdes_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="source/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodasource"/>
</Source>
<Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
architecture TestBench of TB_soda_chain is\r
\r
-- Clock period definitions
- constant clk_period: time:= 4ns;
+ constant sysclk_period: time:= 5ns;
+ constant sodaclk_period: time:= 4.999ns;
\r
\r
--Inputs
signal rst_S : std_logic;
- signal clk_S : std_logic;
+ signal sys_clk_S : std_logic;
+ signal soda_clk_S : std_logic;
signal enable_S : std_logic := '0';
signal SOB_S : std_logic := '0';
signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
THE_SOB_SOURCE : soda_start_of_burst_faker
port map(
- SYSCLK => clk_S,
+ SYSCLK => sys_clk_S,
RESET => rst_S,
SODA_BURST_PULSE_OUT => SOB_S
);
\r
THE_SODA_SOURCE : soda_source
port map(
- SYSCLK => clk_S,
+ SYSCLK => sys_clk_S,
RESET => rst_S,
CLEAR => '0',
CLK_EN => '1',
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
SODA_ACK_OUT => soda_ack,\r
- LEDS_OUT => soda_leds,
- TEST_LINE => open,\r
- STAT => open
+ LEDS_OUT => soda_leds
);
A_SODA_HUB : soda_hub
port map(
- SYSCLK => clk_S,
+ SYSCLK => sys_clk_S,
+ SODACLK => soda_clk_S,
RESET => rst_S,
CLEAR => '0',
CLK_EN => '1',
\r
A_SODA_CLIENT : soda_client
port map(
- SYSCLK => clk_S,
+ SYSCLK => sys_clk_S,
+ SODACLK => soda_clk_S,
RESET => rst_S,
CLEAR => '0',
CLK_EN => '1',
SODA_READ_IN => soda_read,
SODA_WRITE_IN => soda_write,
SODA_ACK_OUT => soda_ack,\r
- STAT => open
+ LEDS_OUT => open,
+ LINK_DEBUG_IN => (others => '0')
);
end generate;
soda_addr <= "0000";
soda_data_in <= x"08000000"; -- soda_reset
soda_write <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_write <= '0';
- wait for clk_period;
+ wait for sysclk_period;
soda_addr <= "0000";
soda_data_in <= x"00000000"; -- soda_reset
soda_write <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_write <= '0';
------------------------------------------------------------------------------------------------------------
wait for 2us;
soda_addr <= "0100";
soda_data_in <= x"FFFFFFFD"; --
soda_write <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_write <= '0';
------------------------------------------------------------------------------------------------------------
wait for 700us;
soda_addr <= "0000";
soda_data_in <= x"40000000"; -- time_calibration
soda_write <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_write <= '0';
------------------------------------------------------------------------------------------------------------
wait for 700us;
soda_addr <= "0100";
soda_data_in <= x"FFFFFFFE"; -- time_calibration
soda_write <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_write <= '0';
------------------------------------------------------------------------------------------------------------
wait for 100us;
soda_addr <= "1001";
soda_read <= '1';
- wait for clk_period;
+ wait for sysclk_period;
soda_read <= '0';
end process;
------------------------------------------------------------------------------------------------------------
-- Clock process definitions
------------------------------------------------------------------------------------------------------------
- clk_proc :process
- begin
- clk_S <= '0';
- wait for clk_period/2;
- clk_S <= '1';
- wait for clk_period/2;
- end process;
-
- -- reset process
- reset_proc: process
- begin
-rst_S <= '1';
-wait for clk_period * 5;
-rst_S <= '0';
-wait;
- end process;
-\r
--- burst_proc :process
--- begin
---SOB_S <= '0';
---wait for 2.35us;
---SOB_S <= '1';
---wait for 50ns;
--- end process;
+ sysclk_proc :process
+ begin
+ sys_clk_S <= '0';
+ wait for sysclk_period/2;
+ sys_clk_S <= '1';
+ wait for sysclk_period/2;
+ end process;
+
+ sodaclk_proc :process
+ begin
+ soda_clk_S <= '0';
+ wait for sodaclk_period/2;
+ soda_clk_S <= '1';
+ wait for sodaclk_period/2;
+ end process;
+
+------------------------------------------------------------------------------------------------------------
+-- reset process
+------------------------------------------------------------------------------------------------------------
+ reset_proc: process
+ begin
+ rst_S <= '1';
+ wait for sysclk_period * 5;
+ rst_S <= '0';
+ wait;
+ end process;
\r
end TestBench;\r
\r
CH0_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
-INT_ALL "ENABLED"
-QD_REFCK2CORE "ENABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
end serdes_sync_downstream;
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch0_s <= rx_los_low_ch0_sig;
rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
CH0_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
-INT_ALL "ENABLED"
-QD_REFCK2CORE "ENABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
end serdes_sync_upstream;
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch0_s <= rx_los_low_ch0_sig;
rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
entity soda_client is
port(
SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- recovered clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
architecture Behavioral of soda_client is
--SODA
-
- signal enable_S : std_logic := '0';
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
signal soda_cmd_valid_S : std_logic := '0';
signal start_of_superburst_S : std_logic := '0';
type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
signal CURRENT_STATE, NEXT_STATE: STATES;
- -- slave bus signals
+-- slave bus signals
signal bus_ack_x : std_logic;
signal bus_ack : std_logic;
signal store_wr_x : std_logic;
signal tx_dlm_out_S : std_logic;
\r
-- debug\r
-signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0');
-signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
-signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
-signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
-signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
begin
packet_handler : soda_packet_handler
port map(
- SYSCLK => SYSCLK,
- RESET => RESET,
- CLEAR => '0',
- CLK_EN => '1',
+ SODACLK => SODACLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => '1',
--Internal Connection
- START_OF_SUPERBURST => start_of_superburst_S,
- SUPER_BURST_NR => super_burst_nr_S,
- SODA_CMD_VALID_S => soda_cmd_valid_S,
- SODA_CMD_WORD_S => soda_cmd_word_S,
- CRC_VALID_OUT => crc_valid_S,\r
- CRC_DATA_OUT => crc_data_S,
- RX_DLM_IN => RX_DLM_IN,
- RX_DLM_WORD_IN => RX_DLM_WORD_IN
+ START_OF_SUPERBURST_OUT => start_of_superburst_S,
+ SUPER_BURST_NR_OUT => super_burst_nr_S,
+ SODA_CMD_VALID_OUT => soda_cmd_valid_S,
+ SODA_CMD_WORD_OUT => soda_cmd_word_S,
+ CRC_VALID_OUT => crc_valid_S,\r
+ CRC_DATA_OUT => crc_data_S,
+ RX_DLM_IN => RX_DLM_IN,
+ RX_DLM_WORD_IN => RX_DLM_WORD_IN
);
reply_packet_builder : soda_reply_pkt_builder \r
port map(
- SYSCLK => SYSCLK,
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => CLK_EN,
CURRENT_STATE <= NEXT_STATE;
bus_ack <= bus_ack_x;
store_wr <= store_wr_x;
- store_rd <= store_rd_x;
+ store_rd <= store_rd_x;
end if;
end if;
end process STATE_MEM;
BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts
);
port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
--Internal Connection
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
+ SODA_BURST_PULSE_IN : in std_logic := '0'; --
+ START_OF_SUPERBURST_OUT : out std_logic := '0';
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
);
end component;
component soda_packet_builder
port(
- SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
component soda_packet_handler
port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
--Internal Connection
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0');
- SODA_CMD_VALID_S : out std_logic := '0';
- SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0');
- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- CRC_VALID_OUT : out std_logic := '0';\r
- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic;
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
+ START_OF_SUPERBURST_OUT : out std_logic := '0';
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_VALID_OUT : out std_logic := '0';
+ SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ CRC_VALID_OUT : out std_logic := '0';\r
+ CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic;
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
end component;
\r
component soda_hub
port(
SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- recovered clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
component soda_client -- box containing soda_source components
port(
SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- recovered clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
component soda_reply_pkt_builder\r
port(\r
- SYSCLK : in std_logic; -- fabric clock\r
+ SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
--Internal Connection
- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET;
+ -- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET;
EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic := '0';
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
SODA_BURST_PULSE_OUT : out std_logic := '0'
);
end component;
+
+ component posedge_to_pulse
+ port (
+ IN_CLK : in std_logic;
+ OUT_CLK : in std_logic;
+ CLK_EN : in std_logic;
+ SINGAL_IN : in std_logic;
+ PULSE_OUT : out std_logic
+ );
+ end component;
\r
end package;
entity soda_hub is
port(
SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
hub_packet_handler : soda_packet_handler
port map(
- SYSCLK => SYSCLK,
- RESET => RESET,
- CLEAR => '0',
- CLK_EN => '1',
+ SODACLK => SODACLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => '1',
--Internal Connection
- START_OF_SUPERBURST => start_of_superburst_S,
- SUPER_BURST_NR => super_burst_nr_S,
- SODA_CMD_VALID_S => soda_cmd_valid_S,
- SODA_CMD_WORD_S => soda_cmd_word_S,
- EXPECTED_REPLY_OUT => expected_reply_S,
- CRC_VALID_OUT => crc_valid_S,\r
- CRC_DATA_OUT => crc_data_S,
- RX_DLM_IN => RXTOP_DLM_IN,
- RX_DLM_WORD_IN => RXTOP_DLM_WORD_IN
+ START_OF_SUPERBURST_OUT => start_of_superburst_S,
+ SUPER_BURST_NR_OUT => super_burst_nr_S,
+ SODA_CMD_VALID_OUT => soda_cmd_valid_S,
+ SODA_CMD_WORD_OUT => soda_cmd_word_S,
+ EXPECTED_REPLY_OUT => expected_reply_S,
+ CRC_VALID_OUT => crc_valid_S,\r
+ CRC_DATA_OUT => crc_data_S,
+ RX_DLM_IN => RXTOP_DLM_IN,
+ RX_DLM_WORD_IN => RXTOP_DLM_WORD_IN
);
reply_packet_builder : soda_reply_pkt_builder \r
port map(
- SYSCLK => SYSCLK,
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => CLK_EN,
packet_builder : soda_packet_builder
port map(
- SYSCLK => SYSCLK,
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => CLK_EN,
CLEAR => '0',
CLK_EN => '1',
--Internal Connection
- LAST_PACKET => last_packet_sent_S,
+-- LAST_PACKET => last_packet_sent_S,
EXPECTED_REPLY_IN => expected_reply_S,
RX_DLM_IN => RXBTM_DLM_IN(i),
RX_DLM_WORD_IN => RXBTM_DLM_WORD_IN(i),
\r
entity soda_packet_builder is\r
port(\r
- SYSCLK : in std_logic; -- fabric clock\r
+ SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
\r
tx_crc8: soda_d8crc8
port map(
- CLOCK => SYSCLK,
+ CLOCK => SODACLK,
RESET => RESET,
SOC_IN => soc_S,
DATA_IN => crc_datain_S,
TX_DLM_OUT <= soda_pkt_valid_S;\r
\r
\r
- packet_fsm_proc : process(SYSCLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)\r
+ packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)\r
begin\r
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
if (RESET='1') then\r
packet_state_S <= c_IDLE;\r
else\r
end if;\r
end process;\r
\r
- soda_packet_fill_proc : process(SYSCLK, packet_state_S)\r
+ soda_packet_fill_proc : process(SODACLK, packet_state_S)\r
begin\r
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
case packet_state_S is\r
when c_IDLE =>\r
TIME_CAL_OUT <= '0';\r
end process;\r
\r
\r
- crc_gen_proc : process(SYSCLK, packet_state_S)\r
+ crc_gen_proc : process(SODACLK, packet_state_S)\r
begin\r
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
case packet_state_S is\r
when c_IDLE =>\r
crc_data_valid_S <= '0';\r
entity soda_packet_handler is
port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
--Internal Connection
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0');
- SODA_CMD_VALID_S : out std_logic := '0';
- SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0');
- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- CRC_VALID_OUT : out std_logic := '0';\r
- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic;
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
+ START_OF_SUPERBURST_OUT : out std_logic := '0';
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_VALID_OUT : out std_logic := '0';
+ SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ CRC_VALID_OUT : out std_logic := '0';\r
+ CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic;
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
end soda_packet_handler;
begin
- packet_fsm_proc : process(SYSCLK)
+ packet_fsm_proc : process(SODACLK)
begin
- if rising_edge(SYSCLK) then
+ if rising_edge(SODACLK) then
if (RESET='1') then
packet_state_S <= c_RST;
else
end if;
end process;
- soda_packet_collector_proc : process(SYSCLK, packet_state_S)
+ soda_packet_collector_proc : process(SODACLK, packet_state_S)
begin
- if rising_edge(SYSCLK) then
+ if rising_edge(SODACLK) then
case packet_state_S is
when c_RST =>
- START_OF_SUPERBURST <= '0';
- soda_cmd_valid_S <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
+ SODA_CMD_VALID_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_IDLE =>
- START_OF_SUPERBURST <= '0';
- soda_cmd_valid_S <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
+ SODA_CMD_VALID_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_SODA_PKT1 =>
soda_pkt_valid_S <= '1';
EXPECTED_REPLY_OUT <= soda_pkt_word_S(7 downto 0);
if (soda_pkt_word_S(31)= '1') then
- START_OF_SUPERBURST <= '1';
- SUPER_BURST_NR <= soda_pkt_word_S(30 downto 0);
+ START_OF_SUPERBURST_OUT <= '1';
+ SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0);
else
- soda_cmd_valid_S <= '1';
- soda_cmd_word_S <= soda_pkt_word_S(30 downto 0);
+ SODA_CMD_VALID_OUT <= '1';
+ SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);
end if;
when others =>
- START_OF_SUPERBURST <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
- soda_cmd_valid_S <= '0';
- soda_cmd_word_S <= (others=>'0');
+ SODA_CMD_VALID_OUT <= '0';
+ SODA_CMD_WORD_OUT <= (others=>'0');
end case;
end if;
end process;
- crc_check_proc : process(SYSCLK, packet_state_S)
+ crc_check_proc : process(SODACLK, packet_state_S)
begin
- if rising_edge(SYSCLK) then
+ if rising_edge(SODACLK) then
case packet_state_S is
when c_RST=>
CRC_VALID_OUT <= '0';
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
--Internal Connection
- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET;
+-- LAST_PACKET _IN : in t_PACKET_TYPE_SENT := c_NO_PACKET;
EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic := '0';
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
\r
entity soda_reply_pkt_builder is\r
port(\r
- SYSCLK : in std_logic; -- fabric clock\r
+ SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
\r
begin\r
- reply_fsm_proc : process(SYSCLK)
+ reply_fsm_proc : process(SODACLK)
begin
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
if (RESET='1') then
packet_state_S <= c_IDLE;
else
end if;
end process;
- collect_reply_proc : process(SYSCLK)
+ collect_reply_proc : process(SODACLK)
begin
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
if (RESET='1') then
TX_DLM_OUT <= '0';\r
TX_DLM_WORD_OUT <= (others=>'0');
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
LEDS_OUT : out std_logic_vector(3 downto 0)
--- TEST_LINE : out std_logic_vector(15 downto 0);
--- STAT : out std_logic_vector(31 downto 0) -- DEBUG
);
end soda_source;
superburst_gen : soda_superburst_generator
generic map(BURST_COUNT => 16)
port map(
- SYSCLK => SYSCLK,
- RESET => RESET,
- CLEAR => '0',
- CLK_EN => CLK_EN,
+ SODACLK => SYSCLK, -- Here sysclk is the same as sodaclk; we are still at the source
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => CLK_EN,
--Internal Connection
- SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
- START_OF_SUPERBURST => start_of_superburst_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S
+ SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
+ START_OF_SUPERBURST_OUT => start_of_superburst_S,
+ SUPER_BURST_NR_OUT => super_burst_nr_S
);
packet_builder : soda_packet_builder
port map(
- SYSCLK => SYSCLK,
+ SODACLK => SYSCLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => CLK_EN,
CLEAR => '0',
CLK_EN => '1',
--Internal Connection
- LAST_PACKET => last_packet_sent_S,
+-- LAST_PACKET => last_packet_sent_S,
EXPECTED_REPLY_IN => expected_reply_S,
RX_DLM_IN => RX_DLM_IN,
RX_DLM_WORD_IN => RX_DLM_WORD_IN,
-----------------------------------------------------------
-- Transmission history for reply-checking --
-----------------------------------------------------------
- packet_history_proc : process(SYSCLK)
- begin
- if rising_edge(SYSCLK) then
- if( RESET = '1' ) then
- last_packet_sent_S <= c_NO_PACKET;
- elsif (start_of_superburst_S='1') then
- last_packet_sent_S <= c_BST_PACKET;
- elsif (soda_cmd_strobe_S='1') then
- last_packet_sent_S <= c_CMD_PACKET;
- end if;
- end if;
- end process;
+-- packet_history_proc : process(SYSCLK)
+-- begin
+-- if rising_edge(SYSCLK) then
+-- if( RESET = '1' ) then
+-- last_packet_sent_S <= c_NO_PACKET;
+-- elsif (start_of_superburst_S='1') then
+-- last_packet_sent_S <= c_BST_PACKET;
+-- elsif (soda_cmd_strobe_S='1') then
+-- last_packet_sent_S <= c_CMD_PACKET;
+-- end if;
+-- end if;
+-- end process;
---------------------------------------------------------
-- RegIO Statemachine
BURST_COUNT : natural range 1 to 256 := 16 -- number of bursts to be counted between super-bursts
);
port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
--Internal Connection
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
+ SODA_BURST_PULSE_IN : in std_logic := '0'; --
+ START_OF_SUPERBURST_OUT : out std_logic := '0';
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
);
end soda_superburst_generator;
constant cBURST_COUNT : std_logic_vector(7 downto 0) := conv_std_logic_vector(BURST_COUNT - 1,8);
- signal clk_S : std_logic;
- signal rst_S : std_logic;
signal soda_burst_pulse_S : std_logic := '0';
signal start_of_superburst_S : std_logic := '0';
signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
begin
- clk_S <= SYSCLK;
- rst_S <= RESET;
- START_OF_SUPERBURST <= start_of_superburst_S;
SUPER_BURST_NR_OUT <= super_burst_nr_S;
- burst_pulse_edge_proc : process(clk_S, rst_S, SODA_BURST_PULSE_IN, soda_burst_pulse_S, burst_counter_S)
+ burst_pulse_edge_proc : process(SODACLK)
begin
- if rising_edge(clk_S) then
+ if rising_edge(SODACLK) then
soda_burst_pulse_S <= SODA_BURST_PULSE_IN;
- if (rst_S='1') then
+ if (RESET='1') then
burst_counter_S <= cBURST_COUNT;
- start_of_superburst_S <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
super_burst_nr_S <= (others => '0');
elsif ((SODA_BURST_PULSE_IN = '1') and (soda_burst_pulse_S = '0')) then
if (burst_counter_S = x"00") then
- start_of_superburst_S <= '1';
+ START_OF_SUPERBURST_OUT <= '1';
super_burst_nr_S <= super_burst_nr_S + 1;
burst_counter_S <= cBURST_COUNT;
else
- start_of_superburst_S <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
burst_counter_s <= burst_counter_s - 1;
end if;
else
- start_of_superburst_S <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
end if;
end if;
end process;
-
end Behavioral;
signal rx_dlm_word : std_logic_vector(7 downto 0);
--SODA
- signal rst_S : std_logic;
- signal clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_cmd_strobe_S : std_logic := '0';
- signal SOS_S : std_logic := '0';
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal SOB_S : std_logic := '0';
- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
- signal dlm_valid_S : std_logic;
+-- signal rst_S : std_logic;
+-- signal clk_S : std_logic;
+-- signal enable_S : std_logic := '0';
+-- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
+-- signal soda_cmd_strobe_S : std_logic := '0';
+-- signal SOS_S : std_logic := '0';
+-- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
+-- signal SOB_S : std_logic := '0';
+-- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
+-- signal dlm_valid_S : std_logic;
begin
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- The Soda Central
---------------------------------------------------------------------------
--- tx_dlm_i <= '0';
--- tx_dlm_word <= x"00";
+
THE_SOB_SOURCE : soda_start_of_burst_faker
port map(
SYSCLK => clk_sys_i,
jspc29 / soda.git / commitdiff