added proper LED behavior to sync media interface

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..f8c0b32
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,14 @@
+*~
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+workdir
+*.kate-swp

diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd
index 2db5279b8e887801e42261277273c416b93005d9..2145c26bd552dc5e7f5b3eb1f51210af29aadbb0 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync.vhd
@@ -13,11 +13,10 @@ use work.med_sync_define.all;
 entity med_ecp3_sfp_sync is
   generic(
     SERDES_NUM : integer range 0 to 3 := 0;
---     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
     IS_SYNC_SLAVE   : integer := c_NO       --select slave mode
     );
   port(
-    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+    CLK                : in  std_logic; -- *internal* 200 MHz reference clock
     SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
     RESET              : in  std_logic; -- synchronous reset
     CLEAR              : in  std_logic; -- asynchronous reset
@@ -159,6 +158,13 @@ signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
 signal start_timer       : unsigned(18 downto 0) := (others => '0');
 
+signal rx_dlm_i               : std_logic;
+signal led_dlm, last_led_dlm  : std_logic;
+signal led_ok                 : std_logic;
+signal led_tx, last_led_tx    : std_logic;
+signal led_rx, last_led_rx    : std_logic;
+signal timer    : unsigned(20 downto 0);
+
 begin
 
 clk_200_internal <= CLK;
@@ -355,7 +361,7 @@ THE_RX_CONTROL : rx_control
     START_POSITION_OUT             => start_retr_position_i,
 
     --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    RX_DLM                         => RX_DLM,
+    RX_DLM                         => rx_dlm_i,
     RX_DLM_WORD                    => RX_DLM_WORD,
     
     SEND_LINK_RESET_OUT            => send_link_reset_i,
@@ -367,7 +373,7 @@ THE_RX_CONTROL : rx_control
     STAT_REG_OUT                   => stat_rx_control_i
     );   
     
-    
+RX_DLM <= rx_dlm_i;
     
 -------------------------------------------------      
 -- SCI
@@ -452,6 +458,24 @@ begin
   
 end process;
 
+-------------------------------------------------      
+-- Generate LED signals
+-------------------------------------------------   
+led_ok <= rx_allow and tx_allow when rising_edge(SYSCLK); 
+led_rx <= (MED_DATAREADY_OUT or led_rx or last_led_rx)  and not timer(20) when rising_edge(SYSCLK);
+led_tx <= (MED_DATAREADY_IN or led_tx or last_led_tx)  and not timer(20) when rising_edge(SYSCLK);
+led_dlm <= (led_dlm or rx_dlm_i or last_led_dlm) and not timer(20) when rising_edge(clk_200_i);
+
+ROC_TIMER : process begin
+  wait until rising_edge(SYSCLK);
+  timer <= timer + 1 ;
+  if timer(20) = '1' then
+    timer <= (others => '0');
+    last_led_rx <= led_rx;
+    last_led_tx <= led_tx;
+    last_led_dlm <= led_dlm;
+  end if;
+end process;
 
 -------------------------------------------------      
 -- Debug Registers
@@ -489,10 +513,10 @@ internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0
 STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
 STAT_OP(14) <= '0';
 STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12) <= '0';
-STAT_OP(11) <= '0';
-STAT_OP(10) <= rx_allow;
-STAT_OP(9)  <= tx_allow;
+STAT_OP(12) <= led_dlm;
+STAT_OP(11) <= led_tx;
+STAT_OP(10) <= led_rx;
+STAT_OP(9)  <= led_ok;
 STAT_OP(8 downto 4) <= (others => '0');
 STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
 end architecture;