type STATES is (IDLE, BADTRG, TRGFND, LVL1FND, WAITREL, TOCFND, RELEASE, DONE);
signal CURRENT_STATE, NEXT_STATE: STATES;
-signal toc_ce : std_logic;
+signal toc_ce : std_logic; -- count enable for TRG/LVL1 timeout
signal next_toc_ce : std_logic;
-signal toc_rst : std_logic;
+signal toc_rst : std_logic; -- reset for timout
signal next_toc_rst : std_logic;
+signal trg_rel : std_logic; -- release LVL1 channel
+signal next_trg_rel : std_logic;
+signal trg_rst : std_logic; -- reset trg_found latch
+signal next_trg_rst : std_logic;
+signal val_trg : std_logic; -- valid timing + LVL1 trigger
+signal next_val_trg : std_logic;
+signal val_ttl_trg : std_logic; -- valid timingtriggerless trigger (who invented that name?)
+signal next_val_ttl_trg : std_logic;
+signal invalid_trg : std_logic; -- invalid trigger: LVL1 missing, or wrong information
+signal next_invalid_trg : std_logic;
+
+signal data_valid : std_logic;
+signal next_data_valid : std_logic;
+
signal bsm_x : std_logic_vector(3 downto 0);
-- Signals
signal timeout_ctr : unsigned(8 downto 0);
signal timeout_found : std_logic;
signal next_timeout_found : std_logic;
+signal trg_num_match : std_logic;
+signal next_trg_num_match : std_logic;
signal debug : std_logic_vector(15 downto 0);
---------------------------------------------------------------------------
-- Debug signals
---------------------------------------------------------------------------
-debug(15 downto 4) <= (others => '0');
-debug(3 downto 0) <= bsm_x; -- state bits
+debug(15 downto 12) <= bsm_x;
+debug(11 downto 9) <= (others => '0');
+debug(8 downto 0) <= std_logic_vector(timeout_ctr);
DEBUG_OUT <= debug;
+---------------------------------------------------------------------------
+-- One process for registering combinatorial signals
+---------------------------------------------------------------------------
+THE_SYNC_PROC: process( CLOCK )
+begin
+ if( rising_edge(CLOCK) ) then
+ timeout_found <= next_timeout_found;
+ trg_num_match <= next_trg_num_match;
+ data_valid <= next_data_valid;
+ end if;
+end process THE_SYNC_PROC;
+
---------------------------------------------------------------------------
-- fake timing trigger has only 10ns length!
---------------------------------------------------------------------------
end process THE_RISING_EDGE_PROC;
-- latch the result for state machine
--- BUG: reset missing!
THE_LATCH_PROC: process( CLOCK )
begin
if( rising_edge(CLOCK) ) then
- if ( RESET = '1' ) then
+ if ( (RESET = '1') or (trg_rst = '1') ) then
timing_trg_found <= '0';
elsif( timing_trg_rising = '1' ) then
timing_trg_found <= '1';
end if;
end process THE_LATCH_PROC;
-LVL1_VALID_TIMING_TRG_OUT <= timing_trg_rising; -- BUG
-
-LVL1_VALID_NOTIMING_TRG_OUT <= timing_trg_comb; -- BUG
-
---------------------------------------------------------------------------
-- Timeout counter for LVL1
---------------------------------------------------------------------------
end process THE_TIMEOUT_CTR_PROC;
-- 5.12us maximum
+-- Jan, be fast :-)
next_timeout_found <= '1' when ( timeout_ctr = b"1_1111_1111" ) else '0';
-THE_SYNC_PROC: process( CLOCK )
-begin
- if( rising_edge(CLOCK) ) then
- timeout_found <= next_timeout_found;
- end if;
-end process THE_SYNC_PROC;
-
---------------------------------------------------------------------------
-- State machine
---------------------------------------------------------------------------
CURRENT_STATE <= IDLE;
toc_ce <= '0';
toc_rst <= '1';
+ trg_rel <= '0';
+ trg_rst <= '0';
+ val_trg <= '0';
+ val_ttl_trg <= '0';
+ invalid_trg <= '0';
else
CURRENT_STATE <= NEXT_STATE;
toc_ce <= next_toc_ce;
toc_rst <= next_toc_rst;
+ trg_rel <= next_trg_rel;
+ trg_rst <= next_trg_rst;
+ val_trg <= next_val_trg;
+ val_ttl_trg <= next_val_ttl_trg;
+ invalid_trg <= next_invalid_trg;
end if;
end if;
end process STATE_MEM;
NEXT_STATE <= IDLE; -- avoid latches
next_toc_ce <= '0';
next_toc_rst <= '0';
+ next_trg_rel <= '0';
+ next_trg_rst <= '0';
+ next_val_trg <= val_trg;
+ next_val_ttl_trg <= val_ttl_trg;
+ next_invalid_trg <= invalid_trg;
case CURRENT_STATE is
when IDLE => bsm_x <= x"0";
if ( (timing_trg_found = '1') ) then
(LVL1_TRG_TYPE_IN(3) = '1') and (LVL1_TRG_INFORMATION_IN(7) = '1')) then
-- timingtriggerless trigger found
NEXT_STATE <= LVL1FND;
+ next_val_ttl_trg <= '1';
elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and
((LVL1_TRG_TYPE_IN(3) = '0') or (LVL1_TRG_INFORMATION_IN(7) = '0')) ) then
-- missing timing trigger
NEXT_STATE <= BADTRG;
+ next_invalid_trg <= '1';
else
NEXT_STATE <= IDLE;
end if;
when TRGFND => bsm_x <= x"1";
if ( LVL1_TRG_RECEIVED_IN = '1' ) then
-- suitable LVL1 information has arrived
- NEXT_STATE <= WAITREL;
+ NEXT_STATE <= LVL1FND;
next_toc_rst <= '1';
+ next_val_trg <= '1';
elsif( timeout_found = '1' ) then
-- LVL1 did not arrive in time
NEXT_STATE <= TOCFND;
next_toc_rst <= '1';
+ next_trg_rst <= '1';
+ next_invalid_trg <= '1';
else
-- wait for either timeout or LVL1
NEXT_STATE <= TRGFND;
end if;
when TOCFND => bsm_x <= x"2";
NEXT_STATE <= IDLE;
- when WAITREL => bsm_x <= x"3";
+ when LVL1FND => bsm_x <= x"3";
+ NEXT_STATE <= WAITREL;
+ when WAITREL => bsm_x <= x"4";
if( LVL1_TRG_RELEASE_IN = '1' ) then
-- FEE logic releases trigger
- NEXT_STATE <= DONE;
+ NEXT_STATE <= RELEASE;
+ next_trg_rel <= '1';
+ next_trg_rst <= '1';
else
-- FEE logic still busy
NEXT_STATE <= WAITREL;
end if;
- when BADTRG => bsm_x <= x"4";
+ when BADTRG => bsm_x <= x"5";
NEXT_STATE <= RELEASE;
- when RELEASE => bsm_x <= x"5";
- NEXT_STATE <= DONE;
- when DONE => bsm_x <= x"6";
+ next_trg_rst <= '1';
+ when RELEASE => bsm_x <= x"6";
+ NEXT_STATE <= DONE;
+ next_val_trg <= '0';
+ next_val_ttl_trg <= '0';
+ next_invalid_trg <= '0';
+ when DONE => bsm_x <= x"7";
if( LVL1_TRG_RECEIVED_IN = '0' ) then
NEXT_STATE <= IDLE;
else
end case;
end process STATE_TRANSFORM;
---type STATES is (IDLE, BADTRG, TRGFND, LVL1FND, WAITREL, TOCFND, DONE);
-
+next_data_valid <= '1' when ( CURRENT_STATE = WAITREL ) else '0';
+
+LVL1_TRG_RELEASE_OUT <= trg_rel;
+
+LVL1_TRG_DATA_VALID_OUT <= data_valid;
+LVL1_VALID_TIMING_TRG_OUT <= val_trg;
+LVL1_VALID_NOTIMING_TRG_OUT <= val_ttl_trg;
+LVL1_INVALID_TRG_OUT <= invalid_trg;
---------------------------------------------------------------------------
--- Internal trigger counter
+-- Internal trigger counter, compare internal and external counters
---------------------------------------------------------------------------
THE_INTERNAL_TRG_CTR_PROC: process( CLOCK )
begin
end if;
end process THE_INTERNAL_TRG_CTR_PROC;
-lvl1_int_trg_ce <= '0';
+THE_INC_CTR_PROC: process( CLOCK )
+begin
+ if( rising_edge(CLOCK) ) then
+ lvl1_int_trg_ce <= trg_rel;
+ end if;
+end process THE_INC_CTR_PROC;
+
+next_trg_num_match <= '1' when ( lvl1_int_trg_number = unsigned(LVL1_TRG_NUMBER_IN) )
+ else '0';
LVL1_INT_TRG_NUMBER_OUT <= std_logic_vector(lvl1_int_trg_number);
---------------------------------------------------------------------------
--This code is copied from endpoint_hades_full
--- -------------------------------------------------
--- -- Check LVL1 trigger number
--- -------------------------------------------------
--- proc_internal_trigger_number : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if reset_no_link = '1' then
--- int_trigger_num <= (others => '0');
--- elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then
--- int_trigger_num <= int_trigger_num + 1;
--- elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then
--- int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
--- end if;
--- end if;
--- end process;
---
--- proc_check_trigger_number : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
--- trigger_number_match <= '1';
--- elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then
--- if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then
--- trigger_number_match <= '1';
--- else
--- trigger_number_match <= '0';
--- end if;
--- end if;
--- end if;
--- end process;
---
---
-- proc_detect_trigger_receive : process(CLK)
-- begin
-- if rising_edge(CLK) then
jspc29 / trbnet.git / commitdiff