*** empty log message ***

diff --git a/lattice/ecp2m/pll_in100_out20.lpc b/lattice/ecp2m/pll_in100_out20.lpc
new file mode 100644 (file)
index 0000000..e2073f6
--- /dev/null
+++ b/lattice/ecp2m/pll_in100_out20.lpc
@@ -0,0 +1,56 @@
+[Device]
+Family=latticeecp2m
+PartType=LFE2M20E
+PartName=LFE2M20E-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.1
+ModuleName=pll_in100_out20
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=02/08/2010
+Time=17:18:54
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=100
+OFrq=20.000000
+KFrq=
+U_OFrq=20
+U_KFrq=50
+OP_Tol=0.0
+OK_Tol=0.0
+Div=5
+Mult=1
+Post=64
+SecD=2
+fb_mode=CLKOP
+PhaseDuty=Static
+DelayControl=AUTO_NO_DELAY
+External=AUTO
+PCDR=0
+ClkOPBp=0
+EnCLKOS=0
+ClkOSBp=0
+Phase=0.0
+Duty=8
+DPD=50% Duty
+EnCLKOK=0
+ClkOKBp=0
+ClkRst=0

diff --git a/lattice/ecp2m/pll_in100_out20.vhd b/lattice/ecp2m/pll_in100_out20.vhd
new file mode 100644 (file)
index 0000000..8b0b95c
--- /dev/null
+++ b/lattice/ecp2m/pll_in100_out20.vhd
@@ -0,0 +1,120 @@
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module  Version: 5.1
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out20 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 20 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e 
+
+-- Mon Feb  8 17:18:55 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity pll_in100_out20 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in100_out20 : entity is true;
+end pll_in100_out20;
+
+architecture Structure of pll_in100_out20 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+    signal CLK_t: std_logic;
+
+    -- local component declarations
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    component EPLLD
+    -- synopsys translate_off
+        generic (PLLCAP : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                DUTY : in Integer; PHASEADJ : in String; 
+                PHASE_CNTL : in String; CLKOK_DIV : in Integer; 
+                CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; 
+                CLKI_DIV : in Integer);
+    -- synopsys translate_on
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; 
+            CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    attribute PLLCAP : string; 
+    attribute PLLTYPE : string; 
+    attribute CLKOK_BYPASS : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute CLKOK_DIV : string; 
+    attribute CLKOS_BYPASS : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute CLKOP_BYPASS : string; 
+    attribute PHASE_CNTL : string; 
+    attribute FDEL : string; 
+    attribute DUTY : string; 
+    attribute PHASEADJ : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute CLKOP_DIV : string; 
+    attribute CLKFB_DIV : string; 
+    attribute CLKI_DIV : string; 
+    attribute FIN : string; 
+    attribute PLLCAP of PLLDInst_0 : label is "AUTO";
+    attribute PLLTYPE of PLLDInst_0 : label is "AUTO";
+    attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED";
+    attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000";
+    attribute CLKOK_DIV of PLLDInst_0 : label is "2";
+    attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED";
+    attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "20.000000";
+    attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED";
+    attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC";
+    attribute FDEL of PLLDInst_0 : label is "0";
+    attribute DUTY of PLLDInst_0 : label is "8";
+    attribute PHASEADJ of PLLDInst_0 : label is "0.0";
+    attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000";
+    attribute CLKOP_DIV of PLLDInst_0 : label is "64";
+    attribute CLKFB_DIV of PLLDInst_0 : label is "1";
+    attribute CLKI_DIV of PLLDInst_0 : label is "5";
+    attribute FIN of PLLDInst_0 : label is "100.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLDInst_0: EPLLD
+        -- synopsys translate_off
+        generic map (PLLCAP=> "AUTO", CLKOK_BYPASS=> "DISABLED", 
+        CLKOK_DIV=>  2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        PHASE_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", CLKOP_DIV=>  64, 
+        CLKFB_DIV=>  1, CLKI_DIV=>  5)
+        -- synopsys translate_on
+        port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, 
+            LOCK=>LOCK, CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+    CLK_t <= CLK;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of pll_in100_out20 is
+    for Structure
+        for all:VLO use entity ecp2m.VLO(V); end for;
+        for all:EPLLD use entity ecp2m.EPLLD(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/pinout/shower_fpga2.lpf b/pinout/shower_fpga2.lpf
index db0fdaeb7cbede166eb67bfc7864806c4bf3d9fb..53462a450380013c11720bf36d6ccf26e0069f5c 100644 (file)
--- a/pinout/shower_fpga2.lpf
+++ b/pinout/shower_fpga2.lpf
@@ -18,7 +18,6 @@
   LOCATE COMP  "CLK_125_IN"    SITE "P28";  #F2_GPCLOCK125_P
   IOBUF  PORT  "CLK_125_IN"    IO_TYPE=LVDS25 PULLMODE=NONE ;
 
-
 #####################################################################
 # Test connector
 #####################################################################

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index bfd7377f8c41bc21b5f2b8005b7f38e7e2db409a..415f9f3f068653839527b5ef489f617f469c9c59 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -772,7 +772,7 @@ begin
   proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger )
     begin
       buf_LVL1_ERROR_PATTERN_IN     <= LVL1_ERROR_PATTERN_IN;
-      buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match;
+      buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16);
       buf_LVL1_ERROR_PATTERN_IN(17) <= not got_timing_trigger or LVL1_ERROR_PATTERN_IN(17);
     end process;
 

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 68ff2067f6e22b46083d14e8b2c2d744f0816977..467f9cc510393c8ce97bb6988cf9df54476b7bd7 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -397,7 +397,7 @@ package trb_net_components is
       REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
       REGIO_IDRAM_WR_IN         : in  std_logic := '0';
       REGIO_ONEWIRE_INOUT       : inout std_logic;
-      REGIO_ONEWIRE_MONITOR_IN  : in  std_logic;
+      REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
       REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
 
       TRIGGER_MONITOR_IN        : in  std_logic;  --strobe when timing trigger received
@@ -1457,6 +1457,15 @@ package trb_net_components is
 
 
 
+  component pll_in100_out20 is
+    port (
+      CLK: in std_logic;
+      CLKOP: out std_logic;
+      LOCK: out std_logic
+      );
+  end component;
+
+
   component pll_in200_out100 is
     port (
       CLK: in std_logic;

diff --git a/trb_net_std.vhd b/trb_net_std.vhd
index 74e76369dea40f33716f5f0c1a03a264dbcba305..9698f7c76c2ac613a4625c4888d6d5e0e2c6441c 100644 (file)
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@ -10,6 +10,16 @@ package trb_net_std is
   type array_32_t is array(integer range <>) of std_logic_vector(31 downto 0);
 
 
+--Trigger types
+  constant TRIG_PHYS         : std_logic_vector(3 downto 0) := x"1";
+  constant TRIG_MDC_CAL      : std_logic_vector(3 downto 0) := x"9";
+  constant TRIG_SHW_CAL      : std_logic_vector(3 downto 0) := x"A";
+  constant TRIG_SHW_PED      : std_logic_vector(3 downto 0) := x"B";
+--Trigger Info
+  constant TRIG_SUPPRESS_BIT : integer range 0 to 15 := 0;
+
+
+
 -- some basic definitions for the whole network
 -----------------------------------------------