signal stored_src_port : std_logic_vector(15 downto 0);\r
signal stored_dst_port : std_logic_vector(15 downto 0);\r
\r
--- signal fifo_pl_wr_x : std_logic;\r
signal fifo_pl_wr : std_logic;\r
signal fifo_hd_wr_x : std_logic;\r
signal fifo_hd_wr : std_logic;\r
-- generate a "emergency stop" signal\r
mac_rx_eof_qq <= mac_rx_eof_q when rising_edge(CLK);\r
\r
- -- FSM to decode the incoming stream\r
+ -- FSM to decode the incoming stream\r
PROC_DECODE_FSM: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
DECODE_CS <= IDLE;\r
--- fifo_pl_wr <= '0';\r
fifo_hd_wr <= '0';\r
drop_frame <= '0';\r
rst_bytes <= '1';\r
elsif( rising_edge(CLK) ) then\r
DECODE_CS <= DECODE_NS;\r
--- fifo_pl_wr <= fifo_pl_wr_x;\r
fifo_hd_wr <= fifo_hd_wr_x;\r
drop_frame <= drop_frame_x;\r
rst_bytes <= rst_bytes_x;\r
is_my_mac_x, is_broadcast_x, is_arp_x, is_ipv4_x, is_udp_x,\r
is_version_x, is_sctrl_x, is_icmp_x )\r
begin\r
--- fifo_pl_wr_x <= '0';\r
fifo_hd_wr_x <= '0';\r
drop_frame_x <= '0';\r
rst_bytes_x <= '0';\r
if( (mac_rx_eof_q = '0') ) then\r
-- payload available, store it\r
DECODE_NS <= STORE_FRAME;\r
--- fifo_pl_wr_x <= '1';\r
else\r
-- empty payload, must never happen with ARP, so we drop it\r
DECODE_NS <= LAST_BYTE;\r
if( (mac_rx_eof_q = '0') ) then\r
-- payload available\r
DECODE_NS <= STORE_FRAME;\r
--- fifo_pl_wr_x <= '1';\r
else\r
-- empty payload, must never happen with ICMP, so we drop it\r
DECODE_NS <= LAST_BYTE;\r
if( (mac_rx_eof_q = '0') ) then\r
-- payload available\r
DECODE_NS <= STORE_FRAME;\r
--- fifo_pl_wr_x <= '1';\r
else\r
-- empty payload, store raw frame, check that later?\r
DECODE_NS <= LAST_BYTE;\r
\r
when STORE_FRAME =>\r
decode_fsm <= x"3";\r
--- fifo_pl_wr_x <= '1';\r
if( MAC_RX_EOF_IN = '1' ) then\r
DECODE_NS <= LAST_BYTE;\r
fifo_hd_wr_x <= '1';\r
end case;\r
end process PROC_DECODE_TRANSITIONS;\r
\r
--- -- counter for decoding the byte stream\r
--- PROC_DECODE_CTR: process( CLK, RESET )\r
--- begin\r
--- if ( RESET = '1' ) then\r
--- decode_ctr <= (others => '0');\r
--- elsif( rising_edge(CLK) ) then\r
--- if( (DECODE_CS = STORE_HEADER) or (DECODE_CS = STORE_FRAME) ) then\r
--- decode_ctr <= decode_ctr + 1;\r
--- else\r
--- decode_ctr <= (others => '0');\r
--- end if;\r
--- end if;\r
--- end process PROC_DECODE_CTR;\r
-\r
-- counter for decoding the byte stream\r
PROC_DECODE_CTR: process( CLK, RESET )\r
begin\r
end if;\r
end process PROC_RX_FIFO_SYNC;\r
\r
+ PROC_STORE_FIRST_BYTE: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( (DECODE_CS = DELAY) ) then\r
+ stored_dst_mac(7 downto 0) <= (others => '0');\r
+ elsif( (DECODE_CS = IDLE) and (MAC_RX_EN_IN = '1') and (decode_ctr = x"00") ) then\r
+ stored_dst_mac(7 downto 0) <= MAC_RXD_IN;\r
+ end if;\r
+ end if;\r
+ end process PROC_STORE_FIRST_BYTE;\r
+\r
+ PROC_STORE_SECOND_BYTE: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( (DECODE_CS = DELAY) ) then\r
+ stored_dst_mac(15 downto 8) <= (others => '0');\r
+ elsif( (DECODE_CS = STORE_HEADER) and (MAC_RX_EN_IN = '1') and (decode_ctr = x"00") ) then\r
+ stored_dst_mac(15 downto 8) <= MAC_RXD_IN;\r
+ end if;\r
+ end if;\r
+ end process PROC_STORE_SECOND_BYTE;\r
+\r
-- storing the relevant parts of headers for decision and further usage\r
- PROC_STORE_INFO: process( CLK, RESET )\r
+ PROC_STORE_INFO: process( CLK )\r
begin\r
- if ( RESET = '1' ) then\r
- stored_src_mac <= (others => '0');\r
- stored_dst_mac <= (others => '0');\r
- stored_ethertype <= (others => '0');\r
- stored_version <= (others => '0');\r
- stored_protocol <= (others => '0');\r
- stored_src_ip <= (others => '0');\r
- stored_dst_ip <= (others => '0');\r
- stored_src_port <= (others => '0');\r
- stored_dst_port <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
--- if( (MAC_RX_EN_IN = '1') and (mac_rx_en_q = '0') ) then\r
--- -- early bird\r
--- stored_dst_mac(7 downto 0) <= MAC_RXD_IN; -- FUCKING BUG!!!!\r
--- end if;\r
- if( (mac_rx_en_q = '1') and (DECODE_CS = STORE_HEADER) ) then\r
+ if( rising_edge(CLK) ) then\r
+ if( (DECODE_CS = DELAY) ) then\r
+ stored_dst_mac(47 downto 16) <= (others => '0');\r
+ stored_src_mac <= (others => '0');\r
+ stored_ethertype <= (others => '0');\r
+ stored_version <= (others => '0');\r
+ stored_protocol <= (others => '0');\r
+ stored_src_ip <= (others => '0');\r
+ stored_dst_ip <= (others => '0');\r
+ stored_src_port <= (others => '0');\r
+ stored_dst_port <= (others => '0');\r
+ elsif( (DECODE_CS = STORE_HEADER) and (MAC_RX_EN_IN = '1') ) then\r
case decode_ctr is\r
- when x"00" => stored_dst_mac(15 downto 8) <= MAC_RXD_IN;\r
- stored_dst_mac(7 downto 0) <= mac_rxd_q;\r
when x"01" => stored_dst_mac(23 downto 16) <= MAC_RXD_IN;\r
when x"02" => stored_dst_mac(31 downto 24) <= MAC_RXD_IN;\r
when x"03" => stored_dst_mac(39 downto 32) <= MAC_RXD_IN;\r
when others => null;\r
end case;\r
end if;\r
--- if( (DECODE_CS = WRITE_HDR) ) then\r
- if( (DECODE_CS = DELAY) ) then\r
- stored_src_mac <= (others => '0');\r
- stored_dst_mac <= (others => '0');\r
- stored_ethertype <= (others => '0');\r
- stored_version <= (others => '0');\r
- stored_protocol <= (others => '0');\r
- stored_src_ip <= (others => '0');\r
- stored_dst_ip <= (others => '0');\r
- stored_src_port <= (others => '0');\r
- stored_dst_port <= (others => '0');\r
- end if;\r
end if;\r
end process PROC_STORE_INFO;\r
\r
GSC_INIT_READ_IN : in std_logic;\r
GSC_REPLY_DATAREADY_IN : in std_logic;\r
GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);\r
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);\r
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); -- not used\r
GSC_REPLY_READ_OUT : out std_logic;\r
GSC_BUSY_IN : in std_logic;\r
MAKE_RESET_OUT : out std_logic;\r
\r
attribute syn_encoding : string;\r
\r
- type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, DELAY, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);\r
- signal dissect_current_state, dissect_next_state : dissect_states;\r
- attribute syn_encoding of dissect_current_state: signal is "onehot";\r
+ type DISSECT_STATES is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, DELAY, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);\r
+ signal DISSECT_CS, DISSECT_NS : DISSECT_STATES;\r
+ attribute syn_encoding of DISSECT_CS: signal is "onehot";\r
\r
signal rx_fifo_q : std_logic_vector(17 downto 0);\r
signal rx_fifo_qq : std_logic_vector(17 downto 0);\r
signal mon_sent_frames : unsigned(31 downto 0);\r
signal mon_sent_bytes : unsigned(31 downto 0);\r
\r
+ signal rx_cnt : std_logic_vector(15 downto 0);\r
+ signal tx_cnt : std_logic_vector(15 downto 0);\r
+\r
+ -- TO BE REMOVED LATER.\r
+ signal delay_ctr : unsigned(13 downto 0);\r
+ signal delay_done : std_logic;\r
+\r
+ -- TEST\r
+ signal saved_dst_mac : std_logic_vector(47 downto 0);\r
+ signal store_mac_x : std_logic;\r
+ signal store_mac : std_logic;\r
+ \r
attribute syn_preserve : boolean;\r
attribute syn_keep : boolean;\r
attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;\r
attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;\r
\r
- signal rx_cnt : std_logic_vector(15 downto 0);\r
- signal tx_cnt : std_logic_vector(15 downto 0);\r
-\r
- signal delay_ctr : unsigned(13 downto 0);\r
- signal delay_done : std_logic;\r
-\r
begin\r
\r
-- DEBUG lines\r
\r
MAKE_RESET_OUT <= make_reset;\r
\r
+ -- TEST\r
+ PROC_STORE_MAC: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( DISSECT_CS = IDLE ) then\r
+ saved_dst_mac <= (others => '0');\r
+ elsif( store_mac = '1' ) then\r
+ saved_dst_mac <= PS_SRC_MAC_ADDRESS_IN;\r
+ end if;\r
+ end if;\r
+ end process PROC_STORE_MAC;\r
+ \r
+ -- stores incoming TRBnet requests\r
THE_RECEIVE_FIFO: entity work.fifo_2kx9x18_wcnt\r
port map(\r
Reset => RESET,\r
);\r
\r
--TODO: change to synchronous\r
- rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or\r
- (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or\r
- (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')\r
+ rx_fifo_rd <= '1' when ((DISSECT_CS = LOAD_TO_HUB) and (gsc_init_dataready = '1')) or\r
+ ((DISSECT_CS = WAIT_FOR_HUB) and (gsc_init_dataready = '1') and (GSC_INIT_READ_IN = '1')) or\r
+ ((DISSECT_CS = READ_FRAME) and (PS_DATA_IN(8) = '1'))\r
else '0'; -- preload first word\r
\r
PROC_RX_FIFO_WR_SYNC: process( CLK )\r
end if;\r
end process PROC_RX_FIFO_WR_SYNC;\r
\r
+ -- one travelling bit\r
PROC_SAVED_HDR_CTR: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if ( (PS_WR_EN_IN = '0') and (PS_ACTIVATE_IN = '0') and (dissect_current_state = IDLE) ) then\r
+ if ( (PS_WR_EN_IN = '0') and (PS_ACTIVATE_IN = '0') and (DISSECT_CS = IDLE) ) then\r
saved_hdr_ctr <= "0001";\r
elsif( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') and (saved_hdr_ctr /= "1000") ) then\r
saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';\r
if( PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then\r
if ( saved_hdr_ctr = "0001" ) then\r
saved_hdr_1 <= PS_DATA_IN(7 downto 0);\r
- saved_hdr_2 <= saved_hdr_2;\r
elsif( saved_hdr_ctr = "0010" ) then\r
saved_hdr_2 <= PS_DATA_IN(7 downto 0);\r
- saved_hdr_1 <= saved_hdr_1;\r
end if;\r
end if;\r
end if;\r
------ TODO: change it to synchronous\r
GSC_INIT_PACKET_NUM_OUT <= std_logic_vector(packet_num);\r
GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;\r
- gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or -- JM: TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen?\r
- (dissect_current_state = WAIT_FOR_HUB)\r
+ -- JM: TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen?\r
+ gsc_init_dataready <= '1' when ((DISSECT_CS = LOAD_TO_HUB) and (GSC_INIT_READ_IN = '1')) or\r
+ ((DISSECT_CS = WAIT_FOR_HUB))\r
else '0';\r
\r
PROC_PACKET_NUM: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( dissect_current_state = IDLE ) then\r
+ if( DISSECT_CS = IDLE ) then\r
packet_num <= "100";\r
- elsif( GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100" and dissect_current_state /= READ_FRAME ) then -- JM: BUG zählt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist\r
+ elsif( (GSC_INIT_READ_IN = '1') and (rx_fifo_rd = '1') and (packet_num = "100") and (DISSECT_CS /= READ_FRAME) ) then\r
+ -- JM: BUG zaehlt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist\r
packet_num <= "000";\r
- elsif( rx_fifo_rd = '1' and packet_num /= "100" ) then\r
+ elsif( (rx_fifo_rd = '1') and (packet_num /= "100") ) then\r
packet_num <= packet_num + "1";\r
end if;\r
end if;\r
PROC_TX_FIFO_WR_SYNC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if ( GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1' ) then\r
+ if ( (GSC_REPLY_DATAREADY_IN = '1') and (gsc_reply_read = '1') ) then\r
tx_fifo_wr <= '1';\r
elsif( saved_hdr_ctr = "0010" ) then\r
tx_fifo_wr <= '1';\r
end if;\r
\r
if( saved_hdr_ctr(2 downto 0) = "010" ) then\r
- tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";\r
+ tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02"; -- "reply" + random byte\r
else\r
tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);\r
tx_fifo_data(8) <= '0';\r
end if;\r
end process PROC_TX_FIFO_WR_SYNC;\r
\r
- tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0';\r
+ tx_fifo_rd <= '1' when (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') else '0';\r
\r
TX_FIFO_SYNC_PROC: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
tx_fifo_reset <= '1';\r
elsif( rising_edge(CLK) ) then\r
- if( too_much_data = '1' and dissect_current_state = CLEANUP ) then\r
+ if( (too_much_data = '1') and (DISSECT_CS = CLEANUP) ) then\r
tx_fifo_reset <= '1';\r
else\r
tx_fifo_reset <= '0';\r
GSC_REPLY_READ_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE ) then\r
+ if( (DISSECT_CS = WAIT_FOR_RESPONSE) or (DISSECT_CS = SAVE_RESPONSE) ) then\r
gsc_reply_read <= '1';\r
else\r
gsc_reply_read <= '0';\r
TX_DATA_CTR_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if (dissect_current_state = IDLE) then\r
+ if (DISSECT_CS = IDLE) then\r
tx_data_ctr <= (others => '0');\r
elsif( tx_fifo_wr = '1' ) then\r
tx_data_ctr <= tx_data_ctr + 2;\r
TOO_MUCH_DATA_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if ( dissect_current_state = IDLE ) then\r
+ if ( DISSECT_CS = IDLE ) then\r
too_much_data <= '0';\r
- elsif( (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = unsigned(CFG_MAX_REPLY_SIZE_IN(15 downto 0))) ) then\r
+ elsif( (DISSECT_CS = SAVE_RESPONSE) and (tx_data_ctr = unsigned(CFG_MAX_REPLY_SIZE_IN(15 downto 0))) ) then\r
too_much_data <= '1';\r
end if;\r
end if;\r
TX_LOADED_CTR_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( dissect_current_state = IDLE ) then\r
+ if( DISSECT_CS = IDLE ) then\r
tx_loaded_ctr <= x"0000";\r
- elsif( dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' ) then\r
- tx_loaded_ctr <= tx_loaded_ctr + x"1";\r
+ elsif( (DISSECT_CS = LOAD_FRAME) and (PS_SELECTED_IN = '1') and (TC_RD_EN_IN = '1') ) then\r
+ tx_loaded_ctr <= tx_loaded_ctr + 1;\r
end if;\r
end if;\r
end process TX_LOADED_CTR_PROC;\r
begin\r
if( rising_edge(CLK) ) then\r
if( too_much_data = '0' ) then\r
- if( dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP ) then\r
+ if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then\r
PS_RESPONSE_READY_OUT <= '1';\r
else\r
PS_RESPONSE_READY_OUT <= '0';\r
end if;\r
end if;\r
\r
- if( dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE ) then\r
+ if( (DISSECT_CS = IDLE) or (DISSECT_CS = WAIT_FOR_RESPONSE) ) then\r
PS_BUSY_OUT <= '0';\r
else\r
PS_BUSY_OUT <= '1';\r
end process PS_RESPONSE_SYNC;\r
\r
TC_FRAME_TYPE_OUT <= x"0008";\r
- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;\r
+-- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;\r
+ TC_DEST_MAC_OUT <= saved_dst_mac;\r
TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;\r
TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8);\r
TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);\r
TC_SRC_MAC_OUT <= MY_MAC_IN;\r
TC_SRC_IP_OUT <= MY_IP_IN;\r
- TC_SRC_UDP_OUT <= x"9065"; --x"a861";\r
+ TC_SRC_UDP_OUT <= x"9065"; --x"a861"; -- BUG?!? shouldn't we use the SRC UDP port?\r
TC_IP_PROTOCOL_OUT <= x"11";\r
TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0));\r
\r
DISSECT_MACHINE_PROC: process( CLK, RESET )\r
begin\r
if ( RESET = '1' ) then\r
- dissect_current_state <= IDLE;\r
+ DISSECT_CS <= IDLE;\r
+ store_mac <= '0';\r
elsif( rising_edge(CLK) ) then\r
- dissect_current_state <= dissect_next_state;\r
+ DISSECT_CS <= DISSECT_NS;\r
+ store_mac <= store_mac_x;\r
end if;\r
end process DISSECT_MACHINE_PROC;\r
\r
- DISSECT_MACHINE: process( dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN,\r
+ DISSECT_MACHINE: process( DISSECT_CS, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN,\r
PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr,\r
tx_data_ctr, rx_fifo_q, GSC_BUSY_IN, delay_done )\r
begin\r
state <= x"0";\r
+ store_mac_x <= '0';\r
\r
- case dissect_current_state is\r
+ case DISSECT_CS is\r
\r
when IDLE =>\r
state <= x"1";\r
if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then\r
- dissect_next_state <= READ_FRAME;\r
+ DISSECT_NS <= READ_FRAME;\r
+ store_mac_x <= '1';\r
else\r
- dissect_next_state <= IDLE;\r
+ DISSECT_NS <= IDLE;\r
end if;\r
\r
when READ_FRAME =>\r
state <= x"2";\r
if ( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '0') ) then\r
- dissect_next_state <= WAIT_FOR_HUB;\r
+ DISSECT_NS <= WAIT_FOR_HUB;\r
elsif( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '1') ) then\r
- dissect_next_state <= LOAD_TO_HUB;\r
+ DISSECT_NS <= LOAD_TO_HUB;\r
else\r
- dissect_next_state <= READ_FRAME;\r
+ DISSECT_NS <= READ_FRAME;\r
end if;\r
\r
when WAIT_FOR_HUB =>\r
state <= x"3";\r
if( GSC_INIT_READ_IN = '1' ) then\r
- dissect_next_state <= LOAD_TO_HUB;\r
+ DISSECT_NS <= LOAD_TO_HUB;\r
else\r
- dissect_next_state <= WAIT_FOR_HUB;\r
+ DISSECT_NS <= WAIT_FOR_HUB;\r
end if;\r
\r
when LOAD_TO_HUB =>\r
state <= x"4";\r
if( (rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1') ) then\r
if( reset_detected = '1' ) then\r
- dissect_next_state <= CLEANUP;\r
+ DISSECT_NS <= CLEANUP;\r
else\r
- dissect_next_state <= WAIT_FOR_RESPONSE;\r
+ DISSECT_NS <= WAIT_FOR_RESPONSE;\r
end if;\r
else\r
- dissect_next_state <= LOAD_TO_HUB;\r
+ DISSECT_NS <= LOAD_TO_HUB;\r
end if;\r
\r
when WAIT_FOR_RESPONSE =>\r
state <= x"5";\r
if( GSC_REPLY_DATAREADY_IN = '1' ) then\r
- dissect_next_state <= SAVE_RESPONSE;\r
+ DISSECT_NS <= SAVE_RESPONSE;\r
else\r
- dissect_next_state <= WAIT_FOR_RESPONSE;\r
+ DISSECT_NS <= WAIT_FOR_RESPONSE;\r
end if;\r
\r
when SAVE_RESPONSE =>\r
state <= x"6";\r
if( (GSC_REPLY_DATAREADY_IN = '0') and (GSC_BUSY_IN = '0') ) then\r
if( too_much_data = '0' ) then\r
--- dissect_next_state <= WAIT_FOR_LOAD;\r
- dissect_next_state <= DELAY;\r
+-- DISSECT_NS <= WAIT_FOR_LOAD;\r
+ DISSECT_NS <= DELAY;\r
else\r
- dissect_next_state <= CLEANUP;\r
+ DISSECT_NS <= CLEANUP;\r
end if;\r
else\r
- dissect_next_state <= SAVE_RESPONSE;\r
+ DISSECT_NS <= SAVE_RESPONSE;\r
end if;\r
\r
when DELAY =>\r
+ state <= x"a";\r
if( delay_done = '1' ) then\r
- dissect_next_state <= WAIT_FOR_LOAD;\r
+ DISSECT_NS <= WAIT_FOR_LOAD;\r
else\r
- dissect_next_state <= DELAY;\r
+ DISSECT_NS <= DELAY;\r
end if;\r
\r
when WAIT_FOR_LOAD =>\r
state <= x"7";\r
- if (PS_SELECTED_IN = '1') then\r
- dissect_next_state <= LOAD_FRAME;\r
+ if( PS_SELECTED_IN = '1' ) then\r
+ DISSECT_NS <= LOAD_FRAME;\r
else\r
- dissect_next_state <= WAIT_FOR_LOAD;\r
+ DISSECT_NS <= WAIT_FOR_LOAD;\r
end if;\r
\r
when LOAD_FRAME =>\r
state <= x"8";\r
- if (tx_loaded_ctr = tx_data_ctr) then\r
- dissect_next_state <= CLEANUP;\r
+ if( tx_loaded_ctr = tx_data_ctr ) then\r
+ DISSECT_NS <= CLEANUP;\r
else\r
- dissect_next_state <= LOAD_FRAME;\r
+ DISSECT_NS <= LOAD_FRAME;\r
end if;\r
\r
when CLEANUP =>\r
state <= x"9";\r
- dissect_next_state <= IDLE;\r
+ DISSECT_NS <= IDLE;\r
\r
- when others => dissect_next_state <= IDLE;\r
+ when others => DISSECT_NS <= IDLE;\r
\r
end case;\r
end process DISSECT_MACHINE;\r
\r
+ -- JUST FOR TESTING. TO BE REMOVED.\r
PROC_DELAY_CTR: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if( dissect_current_state /= DELAY ) then\r
+ if( DISSECT_CS /= DELAY ) then\r
delay_ctr <= (others => '0');\r
else\r
delay_ctr <= delay_ctr + 1;\r
end if;\r
end process PROC_DELAY_CTR;\r
\r
- delay_done <= std_logic(delay_ctr(13));\r
+-- delay_done <= std_logic(delay_ctr(13));\r
+ delay_done <= std_logic(delay_ctr(4));\r
\r
-- reset request packet detection\r
RESET_DETECTED_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if ( dissect_current_state = IDLE ) then\r
+ if ( DISSECT_CS = IDLE ) then\r
reset_detected <= '0';\r
- elsif( PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100" ) then\r
+ elsif( (PS_DATA_IN(7 downto 0) = x"80") and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') and (saved_hdr_ctr = "0100") ) then\r
reset_detected <= '1';\r
end if;\r
end if;\r
MAKE_RESET_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- if ( dissect_current_state = IDLE ) then\r
+ if ( DISSECT_CS = IDLE ) then\r
make_reset <= '0';\r
- elsif( dissect_current_state = CLEANUP and reset_detected = '1' ) then\r
+ elsif( (DISSECT_CS = CLEANUP) and (reset_detected = '1') ) then\r
make_reset <= '1';\r
end if;\r
end if;\r
if ( RESET = '1' ) then\r
mon_rec_frames <= (others => '0');\r
elsif( rising_edge(CLK) ) then\r
- if( dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1' ) then\r
+ if( (DISSECT_CS = READ_FRAME) and (PS_DATA_IN(8) = '1') ) then\r
mon_rec_frames <= mon_rec_frames + 1;\r
end if;\r
end if;\r
if ( RESET = '1' ) then\r
mon_sent_frames <= (others => '0');\r
elsif( rising_edge(CLK) ) then\r
- if( dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr ) then\r
+ if( (DISSECT_CS = LOAD_FRAME) and (tx_loaded_ctr = tx_data_ctr) ) then\r
mon_sent_frames <= mon_sent_frames + 1;\r
end if;\r
end if;\r
if ( RESET = '1' ) then\r
reply_ctr <= (others => '0');\r
elsif( rising_edge(CLK) ) then\r
- if( dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr ) then\r
+ if( (DISSECT_CS = LOAD_FRAME) and (tx_loaded_ctr = tx_data_ctr) ) then\r
reply_ctr <= reply_ctr + 1;\r
end if;\r
end if;\r
jspc29 / trbnet.git / commitdiff