new wasa spi mode

diff --git a/wasa/compile_padiwa_frankfurt.pl b/wasa/compile_padiwa_frankfurt.pl
index 084cf2d845f59e7f27840ff9aeab6686de56d73f..6b41d05441c90f65931c896d6073b092721113ed 100755 (executable)
--- a/wasa/compile_padiwa_frankfurt.pl
+++ b/wasa/compile_padiwa_frankfurt.pl
@@ -12,10 +12,11 @@ my $TOPNAME                      = "trb3_periph_padiwa";  #Name of top-level ent
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.0';
 my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+#my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
 ###################################################################################
 
-
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
 
 
 

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index bed5e96f28dae95aab2a0f03ce06a6fb3ff36195..1fc24afbd50eb0771b2c5ddf6152b2db2d00ca35 100644 (file)
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -13,6 +13,9 @@ use machxo2.all;
 \r
 \r
 entity panda_dirc_wasa is\r
+  generic(\r
+    SAME_ORDER : integer := 0\r
+    );\r
   port(\r
     CON        : out std_logic_vector(16 downto 1);\r
     INP        : in  std_logic_vector(16 downto 1);\r
@@ -161,7 +164,7 @@ type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
 signal ram   : ram_t;\r
 \r
 signal pwm_i : std_logic_vector(31 downto 0);\r
-\r
+signal tmp_con     : std_logic_vector(15 downto 0);\r
 signal spi_reg00_i : std_logic_vector(15 downto 0);\r
 signal spi_reg10_i : std_logic_vector(15 downto 0);\r
 signal spi_reg20_i : std_logic_vector(15 downto 0);\r
@@ -531,7 +534,16 @@ end process;
 ---------------------------------------------------------------------------\r
 \r
 inp_gated <= (INP xor inp_invert) and not input_enable;\r
-CON <= inp_gated or (inp_stretched and inp_stretch);\r
+tmp_con <= inp_gated or (inp_stretched and inp_stretch);\r
+\r
+gen_outputs_1 : if SAME_ORDER = 1 generate\r
+  CON <= tmp_con;\r
+end generate;\r
+gen_outputs_2 : if SAME_ORDER = 0 generate\r
+  CON <= tmp_con;\r
+end generate;\r
+\r
+\r
 \r
 SPARE_LINE(0) <= '0'; --clk_26;\r
 SPARE_LINE(1) <= '0'; --clk_i;\r
@@ -581,7 +593,9 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
 -- TEST_LINE(13)           <= ;\r
 -- TEST_LINE(14)           <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0';\r
 -- TEST_LINE(15)           <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';\r
--- \r
+\r
+\r
+TEST_LINE               <= spi_debug_i;\r
 \r
 \r
 LED_GREEN  <= not leds(0) when led_status(4) = '0' else not led_status(0);\r

diff --git a/wasa/source/spi_slave.vhd b/wasa/source/spi_slave.vhd
index 13b4a02fc7ff933742331676f1a05c1ad1b4f606..48292894f81e9ec7d709214c2ac7c35a36ad7094 100644 (file)
--- a/wasa/source/spi_slave.vhd
+++ b/wasa/source/spi_slave.vhd
@@ -150,8 +150,8 @@ DEBUG_OUT(1) <= spi_cs_reg;
 DEBUG_OUT(2) <= spi_in_reg;
 DEBUG_OUT(3) <= buf_SPI_OUT;
 DEBUG_OUT(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4));
--- DEBUG_OUT(8) <= 
-DEBUG_OUT(15 downto 8) <= input(31 downto 24);
+DEBUG_OUT(14 downto 8) <= input(30 downto 24);
+DEBUG_OUT(15) <= write_i(4);
 
 
 

diff --git a/wasa/trb3_periph_padiwa.p2t b/wasa/trb3_periph_padiwa.p2t
index 995161f9940ecb64b00d450faa7e7d4136f2748e..de1c3be1b7f5d147129c8c158d88d2384b0af495 100644 (file)
--- a/wasa/trb3_periph_padiwa.p2t
+++ b/wasa/trb3_periph_padiwa.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 11
+-t 10
 -c 1
 -e 2
 -m nodelist.txt

diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj
index cde14cdc0d155cf3bdf94a13dd5126a608dd8295..f2239b80ba13005e18c1e6743db1d6b78cb56b4d 100644 (file)
--- a/wasa/trb3_periph_padiwa.prj
+++ b/wasa/trb3_periph_padiwa.prj
@@ -23,8 +23,8 @@ set_option -retiming 0
 set_option -pipe 0
 #set_option -force_gsr 
 set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
 set_option -compiler_compatible true
 
 

diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd
index 6cf55620275c961828b6d92f95ece116e84f5593..2fd5fbeb45b0a416ababefffa01dd52e55f13cc5 100644 (file)
--- a/wasa/trb3_periph_padiwa.vhd
+++ b/wasa/trb3_periph_padiwa.vhd
@@ -683,7 +683,7 @@ begin
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      HIT_IN                => hit_in_i(63 downto 0),  -- Channel start signals
+      HIT_IN                => hit_in_i(3 downto 0),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --