my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+#my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de";
###################################################################################
-
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
\r
\r
entity panda_dirc_wasa is\r
+ generic(\r
+ SAME_ORDER : integer := 0\r
+ );\r
port(\r
CON : out std_logic_vector(16 downto 1);\r
INP : in std_logic_vector(16 downto 1);\r
signal ram : ram_t;\r
\r
signal pwm_i : std_logic_vector(31 downto 0);\r
-\r
+signal tmp_con : std_logic_vector(15 downto 0);\r
signal spi_reg00_i : std_logic_vector(15 downto 0);\r
signal spi_reg10_i : std_logic_vector(15 downto 0);\r
signal spi_reg20_i : std_logic_vector(15 downto 0);\r
---------------------------------------------------------------------------\r
\r
inp_gated <= (INP xor inp_invert) and not input_enable;\r
-CON <= inp_gated or (inp_stretched and inp_stretch);\r
+tmp_con <= inp_gated or (inp_stretched and inp_stretch);\r
+\r
+gen_outputs_1 : if SAME_ORDER = 1 generate\r
+ CON <= tmp_con;\r
+end generate;\r
+gen_outputs_2 : if SAME_ORDER = 0 generate\r
+ CON <= tmp_con;\r
+end generate;\r
+\r
+\r
\r
SPARE_LINE(0) <= '0'; --clk_26;\r
SPARE_LINE(1) <= '0'; --clk_i;\r
-- TEST_LINE(13) <= ;\r
-- TEST_LINE(14) <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0';\r
-- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';\r
--- \r
+\r
+\r
+TEST_LINE <= spi_debug_i;\r
\r
\r
LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0);\r
DEBUG_OUT(2) <= spi_in_reg;
DEBUG_OUT(3) <= buf_SPI_OUT;
DEBUG_OUT(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4));
--- DEBUG_OUT(8) <=
-DEBUG_OUT(15 downto 8) <= input(31 downto 24);
+DEBUG_OUT(14 downto 8) <= input(30 downto 24);
+DEBUG_OUT(15) <= write_i(4);
-n 1
-y
-s 12
--t 11
+-t 10
-c 1
-e 2
-m nodelist.txt
set_option -pipe 0
#set_option -force_gsr
set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
set_option -compiler_compatible true
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(63 downto 0), -- Channel start signals
+ HIT_IN => hit_in_i(3 downto 0), -- Channel start signals
TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
--