library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net_bridge_etrax_endpoint is
generic(
architecture trb_net_bridge_etrax_endpoint_arch of trb_net_bridge_etrax_endpoint is
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
- );
- end component;
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN : in STD_LOGIC;
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out STD_LOGIC;
-
- MED_DATAREADY_OUT : out STD_LOGIC;
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL : in STD_LOGIC_VECTOR (31 downto 0);
- STAT : out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
-
- component trb_net_bridge_etrax_apl is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);
- APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
- APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);
- APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
- APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);
- CPU_READ : in STD_LOGIC;
- CPU_WRITE : in STD_LOGIC;
- CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0);
- CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0);
- CPU_DATAREADY_OUT : out std_logic;
- CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0);
- STAT : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_YES;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT : out std_logic;
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN : in std_logic;
-
- MED_REPLY_DATAREADY_OUT : out std_logic;
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN : in std_logic;
-
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT : out std_logic;
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN : in std_logic;
-
- INT_INIT_DATAREADY_IN : in std_logic;
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT : out std_logic;
-
- INT_REPLY_DATAREADY_OUT : out std_logic;
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN : in std_logic;
-
- INT_REPLY_DATAREADY_IN : in std_logic;
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_GEN : out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_GEN : in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN : in std_logic;
- APL_READ_OUT : out std_logic;
- APL_SHORT_TRANSFER_IN : in std_logic;
- APL_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_SEND_IN : in std_logic;
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_DATAREADY_OUT : out std_logic;
- APL_READ_IN : in std_logic;
-
- -- APL Control port
- APL_RUN_OUT : out std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- APL_LENGTH_IN : in std_logic_vector (15 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- -- master_data_out and slave_data_in are only used in active API for termination
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
-
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
-
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
-
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
signal APL_STAT : std_logic_vector(31 downto 0);
signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0);
signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
signal m_DATAREADY_IN : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
- signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ signal m_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+ signal m_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
signal m_READ_OUT : std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
signal MPLEX_CTRL : std_logic_vector (31 downto 0);
MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
MED_REPLY_READ_IN => m_READ_IN(i*2+1),
MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
+ MED_DATA_IN => m_DATA_IN(i*c_DATA_WIDTH+15 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH),
MED_READ_OUT => m_READ_OUT(i),
MED_ERROR_IN => MED_ERROR_IN,
-- Internal direction port
RESET => RESET,
CLK_EN => CLK_EN,
MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN,
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN,
+ MED_DATA_IN => m_DATA_IN(i*16+15 downto i*16),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN(i*3+2 downto i*3),
MED_READ_OUT => m_READ_OUT(i),
MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48);
-STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(23 downto 16);
-STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(23 downto 16);
+STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(19 downto 16);
+STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(19 downto 16);
STAT_API1(11) <= apl_to_buf_REPLY_READ(3);
STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3);
- component trb_net16_med_16_IC is
- port(
- CLK : in std_logic;
- CLK_EN : in std_logic;
- RESET : in std_logic;
-
- --Internal Connection
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_IN : in std_logic;
-
- DATA_OUT : out std_logic_vector(15 downto 0);
- DATA_VALID_OUT : out std_logic;
- DATA_CTRL_OUT : out std_logic;
- DATA_CLK_OUT : out std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- DATA_VALID_IN : in std_logic;
- DATA_CTRL_IN : in std_logic;
- DATA_CLK_IN : in std_logic;
-
- STAT_OP : out std_logic_vector(15 downto 0);
- CTRL_OP : in std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(63 downto 0)
- );
- end component;
-
end component;
-
+ component trb_net_bridge_etrax_apl is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);
+ APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);
+ APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);
+ CPU_READ : in STD_LOGIC;
+ CPU_WRITE : in STD_LOGIC;
+ CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0);
+ CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0);
+ CPU_DATAREADY_OUT : out std_logic;
+ CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0);
+ STAT : out std_logic_vector (31 downto 0);
+ CTRL : in std_logic_vector (31 downto 0)
+ );
+ end component;
end package;
\ No newline at end of file