RESET : in std_logic;
DO_REBOOT : in std_logic;
PROGRAMN : out std_logic := '1'
- );
+ );
end entity;
architecture fpga_reboot_arch of fpga_reboot is
PROGRAMN <= not delayed_restart_fpga;
-end architecture;
\ No newline at end of file
+end architecture;
entity spi_flash_and_fpga_reload_record is
port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
- BUS_TX : out CTRLBUS_TX;
- BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+ BUS_RX : in CTRLBUS_RX;
DO_REBOOT_IN : in std_logic;
PROGRAMN : out std_logic;
SPI_SCK_OUT : out std_logic;
SPI_SDO_OUT : out std_logic;
SPI_SDI_IN : in std_logic
- );
+ );
end entity;
PORT_NUMBER => 2,
PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"),
PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
- )
+ )
port map(
CLK => CLK_IN,
RESET => RESET_IN,
BUS_UNKNOWN_ADDR_IN(1) => '0',
STAT_DEBUG => open
- );
+ );
THE_SPI_MASTER: spi_master
BRAM_WE_OUT => spi_bram_we,
-- Status lines
STAT => open
- );
+ );
-- data memory for SPI accesses
THE_SPI_MEMORY: spi_databus_memory
BRAM_WE_IN => spi_bram_we,
-- Status lines
STAT => open
- );
+ );
---------------------------------------------------------------------------
-- Reboot FPGA
RESET => RESET_IN,
DO_REBOOT => DO_REBOOT_IN,
PROGRAMN => PROGRAMN
- );
-
+ );
end architecture;