*** empty log message ***

diff --git a/testbenches/pseudo_random_stream_checker.vhd b/testbenches/pseudo_random_stream_checker.vhd
index 1a59362908aec2ead3019bb2ed1204cfec559401..9b35aa5e6af363e5a09c1cdb3927a2a403970363 100644 (file)
--- a/testbenches/pseudo_random_stream_checker.vhd
+++ b/testbenches/pseudo_random_stream_checker.vhd
@@ -21,7 +21,8 @@ entity pseudo_random_stream_checker is
     D_IN   : in  std_logic_vector(15 downto 0);
     D_EN   : in  std_logic;
     D_RST  : in  std_logic;
-    FAIL   : out std_logic
+    FAIL   : out std_logic;
+    MY_CRC_OUT: out std_logic_vector(15 downto 0)
     );
 end entity;
 
@@ -40,7 +41,7 @@ architecture arch of pseudo_random_stream_checker is
       );
   end component;
 
-  signal test_counter : unsigned(20 downto 0);
+  signal test_counter : unsigned(15 downto 0);
   signal CRC_reset    : std_logic;
   signal last_D_EN    : std_logic;
   signal last_D_RST   : std_logic;
@@ -60,7 +61,7 @@ begin
       );
 
   CRC_reset <= RESET or D_RST;
-
+  MY_CRC_OUT <= CRC_out;
 
   process(CLK)
     begin

diff --git a/testbenches/pseudo_random_stream_generator.vhd b/testbenches/pseudo_random_stream_generator.vhd
index 8c2ae0f5c5c19d3088ab5b068438e8ffc18abb8b..ee891767fa95287d4cc2a91aa2a667c592c44b3a 100644 (file)
--- a/testbenches/pseudo_random_stream_generator.vhd
+++ b/testbenches/pseudo_random_stream_generator.vhd
@@ -75,7 +75,7 @@ begin
   next_D_EN  <= last_CRC_enable;
   next_D_RST <= CRC_reset;
 
-  CRC_reset <= and_all(std_logic_vector(test_counter(20 downto 15)));
+  CRC_reset <= and_all(std_logic_vector(test_counter(20 downto 10)));
 
   process(CLK)
     begin

diff --git a/testbenches/testbench_all_channels_p2p.vhd b/testbenches/testbench_all_channels_p2p.vhd
index 904c0ad5a59f35418ccdf70ee4098ae4985c5c93..55a113dd8d8e63c945fee68cf3192dcd2e6f3416 100644 (file)
--- a/testbenches/testbench_all_channels_p2p.vhd
+++ b/testbenches/testbench_all_channels_p2p.vhd
@@ -329,7 +329,7 @@ begin
     generic map(
       TARGET_ADDRESS   => x"FFFF",
       PREFILL_LENGTH   => 3,
-      TRANSFER_LENGTH  => 10
+      TRANSFER_LENGTH  => 1
       )
     port map(
       CLK    => CLK,
@@ -341,7 +341,7 @@ begin
       APL_READ_IN         => APL_READ_OUT(0),
       APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(0),
       APL_DTYPE_OUT       => APL_DTYPE_IN(3 downto 0),
-      APL_SEND_OUT        => open,--APL_SEND_IN(0),
+      APL_SEND_OUT        => APL_SEND_IN(0),
       APL_DATA_IN         => APL_DATA_OUT(15 downto 0),
       APL_PACKET_NUM_IN   => APL_PACKET_NUM_OUT(2 downto 0),
       APL_TYP_IN          => APL_TYP_OUT(2 downto 0),

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index 52ca0bedc9510b3e00ec3063bf71c3a7b4cde533..4257a20f681b18465f3deb751873e413573fd869 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -31,7 +31,8 @@ entity trb_net16_addresses is
     API_READ_IN       : in  std_logic;
     ADDRESS_REJECTED  : out std_logic;
     API_SEND_OUT      : out std_logic;
-    ADDRESS_OUT       : out std_logic_vector(15 downto 0)
+    ADDRESS_OUT       : out std_logic_vector(15 downto 0);
+    STAT_DEBUG        : out std_logic_vector(15 downto 0)
     );
 end entity;
 
@@ -81,6 +82,7 @@ signal next_state, state : std_logic_vector(c_NUM_WIDTH-1 downto 0);
 
 type sending_state_t is (sending_idle, send_uid_1, send_uid_2, send_ack_address);
 signal sending_state : sending_state_t;
+signal sending_state_bits : std_logic_vector(1 downto 0);
 signal buf_ADDRESS_OUT : std_logic_vector(15 downto 0);
 
 begin
@@ -224,6 +226,11 @@ begin
       end case;
     end process;
 
+  sending_state_bits <= "00" when sending_state = send_uid_1 else
+                        "01" when sending_state = send_uid_2 else
+                        "10" when sending_state = send_ack_address else
+                        "11" ;--when sending_state = sending_idle;
+
 
   process(CLK)
     begin
@@ -273,4 +280,20 @@ API_SEND_OUT <= buf_API_SEND_OUT;
 API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
 ADDRESS_OUT <= buf_ADDRESS_OUT;
 
+
+
+
+
+STAT_DEBUG(2 downto 0)   <= ram_read_addr1(2 downto 0);
+STAT_DEBUG(6 downto 3)   <= ram_read_addr2;
+STAT_DEBUG(7)            <= API_DATAREADY_IN;
+STAT_DEBUG(9 downto 8)   <= state(1 downto 0);
+STAT_DEBUG(11 downto 10) <= sending_state_bits;
+STAT_DEBUG(15 downto 12) <= "0000"; --added by regio!
+
+--   STAT_ADDR_DEBUG(12) <= buf_API_DATAREADY_OUT;  --dataready out of Regio
+--   STAT_ADDR_DEBUG(13) <= ADR_REJECTED;
+--   STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
+--   STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;      --dataready out of addresses
+
 end architecture;
\ No newline at end of file

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index cc0380596c77818907f2fe9c671dc2f723148649..edc9beb414bc324cbf047d12ec4ce5c14109e4cd 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -124,7 +124,8 @@ entity trb_net16_endpoint_hades_full is
     MED_STAT_OP               : out std_logic_vector (15 downto 0);
     CTRL_MPLEX                : in  std_logic_vector (31 downto 0);
     IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0);
-    STAT_ONEWIRE              : out std_logic_vector (31 downto 0)
+    STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
+    STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0)
     );
 end entity;
 
@@ -228,7 +229,8 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
       EXT_REG_DATA_OUT    : out std_logic_vector(31 downto 0);
       EXT_REG_WRITE_IN    : in  std_logic;
       EXT_REG_ADDR_IN     : in  std_logic_vector(7 downto 0);
-      STAT : out std_logic_vector(31 downto 0)
+      STAT                : out std_logic_vector(31 downto 0);
+      STAT_ADDR_DEBUG     : out std_logic_vector(15 downto 0)
       );
   end component;
 
@@ -889,7 +891,8 @@ begin
               EXT_REG_DATA_OUT       => REGIO_EXT_REG_DATA_OUT,
               EXT_REG_WRITE_IN       => REGIO_EXT_REG_WRITE_IN,
               EXT_REG_ADDR_IN        => REGIO_EXT_REG_ADDR_IN,
-              STAT                   => REGIO_REGIO_STAT
+              STAT                   => REGIO_REGIO_STAT,
+              STAT_ADDR_DEBUG        => STAT_ADDR_DEBUG
               );
           gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = 0 generate
             buf_IDRAM_DATA_IN <= REGIO_IDRAM_DATA_IN;

diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd
index 6897d61a31fc53a091422705c816f5d783518164..3490c1a76f2ee93c7108e9c743b6676542f2cfc2 100644 (file)
--- a/trb_net16_obuf_nodata.vhd
+++ b/trb_net16_obuf_nodata.vhd
@@ -59,7 +59,7 @@ begin
           buf_MED_PACKET_NUM_OUT <= c_H0;
           transfer_counter := c_H0;
         elsif CLK_EN = '1' then
-          reg_SEND_ACK_IN_2 <= (reg_SEND_ACK_IN_2 or SEND_ACK_IN) and reg_SEND_ACK_IN;
+
 
 
           if MED_READ_IN = '1' and reg_SEND_ACK_IN = '1' then
@@ -91,15 +91,20 @@ begin
             buf_MED_DATA_OUT(2 downto 0) <= TYPE_ACK;
           end if;
           buf_MED_PACKET_NUM_OUT <= transfer_counter;
-          reg_SEND_ACK_IN  <= reg_SEND_ACK_IN or SEND_ACK_IN or reg_SEND_ACK_IN_2;
-          if transfer_counter = c_F3 and SEND_ACK_IN = '0' and reg_SEND_ACK_IN_2 = '0' then
-            reg_SEND_ACK_IN <= '0';
-          end if;
 
+          if transfer_counter = c_F3 then
+            reg_SEND_ACK_IN   <= reg_SEND_ACK_IN_2 or SEND_ACK_IN;
+            reg_SEND_ACK_IN_2 <= reg_SEND_ACK_IN_2 and SEND_ACK_IN;
+          else
+            reg_SEND_ACK_IN   <= reg_SEND_ACK_IN or SEND_ACK_IN or reg_SEND_ACK_IN_2;
+            reg_SEND_ACK_IN_2 <= (reg_SEND_ACK_IN_2 or SEND_ACK_IN) and reg_SEND_ACK_IN;
+          end if;
         end if;
       end if;
     end process;
 
+--     send_ACK     <= SEND_ACK_IN or reg_SEND_ACK_IN or reg_SEND_ACK_IN_2;
+--     next_SEND_ACK_IN_2 <= (reg_SEND_ACK_IN_2 or SEND_ACK_IN) and reg_SEND_ACK_IN;
 
 
   STAT_BUFFER <= (others => '0');

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 8c4219deeb811115b8ba39cfa2c23d72fdce743f..a82fac2e72b3435c26bd3e4224ae49588f790be2 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -82,7 +82,8 @@ entity trb_net16_regIO is
     EXT_REG_DATA_OUT    : out std_logic_vector(31 downto 0);
     EXT_REG_WRITE_IN    : in  std_logic;
     EXT_REG_ADDR_IN     : in  std_logic_vector(7 downto 0);
-    STAT : out std_logic_vector(31 downto 0)
+    STAT                : out std_logic_vector(31 downto 0);
+    STAT_ADDR_DEBUG     : out std_logic_vector(15 downto 0)
     );
 end entity;
 
@@ -123,7 +124,8 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
       API_READ_IN       : in  std_logic;
       ADDRESS_REJECTED  : out std_logic;
       API_SEND_OUT      : out std_logic;
-      ADDRESS_OUT       : out std_logic_vector(15 downto 0)
+      ADDRESS_OUT       : out std_logic_vector(15 downto 0);
+      STAT_DEBUG        : out std_logic_vector(15 downto 0)
       );
   end component;
 
@@ -209,6 +211,11 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
   signal combined_API_READ_OUT   : std_logic;
   signal dat_data_counter      : std_logic_vector(15 downto 0);
   signal next_dat_data_counter : std_logic_vector(15 downto 0);
+  signal combined_API_SEND_OUT : std_logic;
+  signal combined_API_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal combined_API_DATAREADY_OUT : std_logic;
+  signal combined_API_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_STAT_ADDR_DEBUG   : std_logic_vector(15 downto 0);
 
 
 begin
@@ -244,9 +251,15 @@ begin
       RAM_ADDR_IN       => IDRAM_ADDR_IN,
       RAM_WR_IN         => IDRAM_WR_IN,
       ADDRESS_REJECTED  => ADR_REJECTED,
-      ADDRESS_OUT       => MY_ADDRESS_OUT
+      ADDRESS_OUT       => MY_ADDRESS_OUT,
+      STAT_DEBUG        => buf_STAT_ADDR_DEBUG
       );
 
+  STAT_ADDR_DEBUG(11 downto 0) <= buf_STAT_ADDR_DEBUG(11 downto 0);
+  STAT_ADDR_DEBUG(12) <= buf_API_DATAREADY_OUT;
+  STAT_ADDR_DEBUG(13) <= ADR_REJECTED;
+  STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
+  STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;
 
   buf_DAT_ADDR_OUT <= address;
   buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
@@ -330,18 +343,19 @@ begin
 
         when ADDRESS_RECV =>
           ADR_DATAREADY_IN <= API_DATAREADY_IN;
-          ADR_READ_IN <= '0';
+          ADR_READ_IN <= API_READ_IN;
           if ADR_REJECTED = '1' then
             next_state <= SEND_REPLY_SHORT_TRANSFER;
-          elsif ADR_DATAREADY_OUT = '1' then
+          elsif ADR_DATAREADY_OUT = '1' and ADR_SEND_OUT = '1' then
             next_state <= ADDRESS_ACK;
           end if;
 
         when ADDRESS_ACK =>
           ADR_READ_IN <= API_READ_IN;
-          next_API_SEND_OUT <= ADR_SEND_OUT;
-          next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
-          next_API_DATA_OUT <= ADR_DATA_OUT;
+          ADR_DATAREADY_IN <= API_DATAREADY_IN;
+--           next_API_SEND_OUT <= ADR_SEND_OUT;
+--           next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
+--           next_API_DATA_OUT <= ADR_DATA_OUT;
           if ADR_SEND_OUT = '0' then
             next_state <= SEND_REPLY_DATA_finish;
           end if;
@@ -699,13 +713,18 @@ begin
   process(CLK)
     begin
       if rising_edge(CLK) then
-        buf_API_DATAREADY_OUT <= next_API_DATAREADY_OUT;
-        if current_state = ADDRESS_ACK then
-          buf_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
+        if RESET = '1' then
+          buf_API_DATA_OUT <= (others => '0');
+          buf_API_DATAREADY_OUT <= '0';
         else
-          buf_API_PACKET_NUM_OUT <= next_packet_counter;
+          buf_API_DATAREADY_OUT <= next_API_DATAREADY_OUT;
+          if current_state = ADDRESS_ACK then
+            buf_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
+          else
+            buf_API_PACKET_NUM_OUT <= next_packet_counter;
+          end if;
+          buf_API_DATA_OUT <= next_API_DATA_OUT;
         end if;
-        buf_API_DATA_OUT <= next_API_DATA_OUT;
       end if;
     end process;
 
@@ -807,13 +826,22 @@ begin
     end process;
 
 
-  --combine read_out of regio and addresses
-  process(current_state, ADR_READ_OUT, buf_API_READ_OUT)
+  --combine signals from regio and addresses
+  process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT,
+          ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT)
     begin
-      if current_state = ADDRESS_RECV then
+      if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then
         combined_API_READ_OUT <= ADR_READ_OUT;
+        combined_API_SEND_OUT <= ADR_SEND_OUT;
+        combined_API_DATA_OUT <= ADR_DATA_OUT;
+        combined_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
+        combined_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
       else
         combined_API_READ_OUT <= buf_API_READ_OUT;
+        combined_API_SEND_OUT <= buf_API_SEND_OUT;
+        combined_API_DATA_OUT <= buf_API_DATA_OUT;
+        combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT;
+        combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
       end if;
     end process;
 
@@ -843,11 +871,11 @@ begin
   buf_API_ERROR_PATTERN_OUT(4) <= dont_understand;
   buf_API_ERROR_PATTERN_OUT(3 downto 0) <= (others => '0');
 
-  API_READ_OUT       <= combined_API_READ_OUT;
-  API_SEND_OUT       <= buf_API_SEND_OUT;
-  API_DATAREADY_OUT      <= buf_API_DATAREADY_OUT;
-  API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
-  API_DATA_OUT       <= buf_API_DATA_OUT;
+  API_READ_OUT           <= combined_API_READ_OUT;
+  API_SEND_OUT           <= combined_API_SEND_OUT;
+  API_DATAREADY_OUT      <= combined_API_DATAREADY_OUT;
+  API_PACKET_NUM_OUT     <= combined_API_PACKET_NUM_OUT;
+  API_DATA_OUT           <= combined_API_DATA_OUT;
   API_SHORT_TRANSFER_OUT <= buf_API_SHORT_TRANSFER_OUT;
   API_DTYPE_OUT          <= saved_operation;
   API_ERROR_PATTERN_OUT  <= buf_API_ERROR_PATTERN_OUT;

diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
index 57f059a6163c718c86e632259f9bfe6ec8055f90..9ac43f6b86776236a5d463f2d406e9286e66f5ea 100644 (file)
--- a/trb_net_onewire.vhd
+++ b/trb_net_onewire.vhd
@@ -10,7 +10,7 @@ use work.trb_net_std.all;
 entity trb_net_onewire is
   generic(
     USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
-    PARASITIC_MODE : integer range 0 to 1 := c_YES;
+    PARASITIC_MODE : integer range 0 to 1 := c_NO;
     CLK_PERIOD : integer := 10  --clk period in ns
     );
   port(