\label{fig:tdc_tdl_slice}
\end{figure}
-In our design each LUT is programmed as a 1-bit full adder and a N~delay element chain is created as a N~bit adder (Figure~\ref{fig:tdc_adder}). All bits of one of the operands are set as '1' and the other operand as '0' except the first bit. The start (hit) signal is assigned to the first bit. As soon as the hit signal arrives to the TDC, starting from the first full adder, the result bits change to '0' and a carry signal is sent to the adjacent full adder. When the stop signal is sent, the outputs of the full adders are latched and the number of zeros defines the location of the propagating carry signal. In our design, the stop signal is defined as the next rising edge of the system clock after the start signal. As the maximum time interval to be measured by the fine time counter is one clock cycle, the total propagation time of the carry signal, along the delay line, has to be longer than a clock period. Manual placement of the delay elements and the corresponding registers are done in order to achieve a uniform delay along the line.
\ No newline at end of file
+In our design each LUT is programmed as a 1-bit full adder and a N~delay element chain is created as a N~bit adder (Figure~\ref{fig:tdc_adder}). All bits of one of the operands are set as '1' and the other operand as '0' except the first bit. The start (hit) signal is assigned to the first bit. As soon as the hit signal arrives to the TDC, starting from the first full adder, the result bits change to '0' and a carry signal is sent to the adjacent full adder. When the stop signal is sent, the outputs of the full adders are latched and the number of zeros defines the location of the propagating carry signal. In our design, the stop signal is defined as the next rising edge of the system clock after the start signal. As the maximum time interval to be measured by the fine time counter is one clock cycle, the total propagation time of the carry signal, along the delay line, has to be longer than a clock period. Manual placement of the delay elements and the corresponding registers are done in order to achieve a uniform delay along the line.
+
+\subsection{Calibration} \label{sec:calibration}
+The propagation delay of a delay cell depends on temperature and the consistency of the power supply. This dependency effects the resolution of the TDC. In order to overcome this problem, the output data of the TDC has to be calibrated.
+
+For an FPGA TDC, digital calibration has to be applied to the raw data. The digital calibration method used in this study was bin-by-bin calibration\cite{tdc_bin_calibration}. In this method a DNL histogram is created for a given number of hits. The number of hits used to generate the DNL histogram varied between 50000 and 500000 and the bin width of each bin was calculated. Assuming the time intervals are completely random and not correlated with the clock signal, the hits should be equally distributed over the time interval of the fine interpolator, which is the clock period. Then the bin width can be calculated from,
+\begin{equation}
+ BW=n\times\frac{T_o}{N}
+\end{equation}
+where $n$ is the actual number of hits of the bin and $N$ is the total number of hits. Using this calculation and the DNL histogram, which is already calculated, a \textit{Look-Up Table} (LUT)\footnote{A lookup table is used to display information, which is recorded previously, corresponding to an individual input.} is created to store the time values of each bin. The corresponding time value for each bin is the middle point of the bin width values. The time value of the first bin is the half of the bin width of the first bin. For the second bin, it is the summation of the bin width value of the first bin and half of the bin width value of the second bin, and so on. After creating the LUT this is used for subsequent measurements. An example of calibrated and uncalibrated time values are shown in \autoref{fig:calibration}. As may be seen from the graph, the quantisation levels of the calibrated data are distributed along the time more evenly than the uncalibrated data quantisation steps. As these quantisation steps effect the non-linearities of the TDC, calibration has lowered the non-linearity values.
+
+\begin{figure}[htp]
+ \centering
+ \includegraphics[width=0.8\textwidth]{figures/Calibration_2.pdf}
+ \caption[An example of a LUT created by the bin-by-bin calibration method]{An example of a LUT created by the bin-by-bin calibration method (Adapted from \cite{tdc_Wu_waveunion})}
+ \label{fig:calibration}
+\end{figure}
+
+This calibration method is correct for a given temperature and supply voltage values, and the calibration LUT has to be updated regularly during the offline analysis.
\ No newline at end of file
--- /dev/null
+@article{tdc_bin_calibration,
+ author = "R Szplet and J Kalisz and R Pelka",
+ title = "Nonlinearity correction of the integrated time-to-digital converter with direct coding",
+ journal = "IEEE Transactions on Instrumentation and Measurement",
+ volume = "46",
+ pages = "449--453",
+ month = "April",
+ year = "1997"
+}
+
+@article{tdc_Wu_waveunion,
+ author = "Jinyuan Wu and Zonghang Shi",
+ title = "The 10-ps Wave Union TDC: Improving FPGA TDC Resolution beyond Its Cell Delay",
+ year = "2008",
+ journal = "Nuclear Science Symposium Conference Record, 2008 IEEE",
+ month = "19-25 October",
+ pages = "3440--3446"
+}
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jspc29 / daqdocu.git / commitdiff