signal led_counter : std_logic_vector(16 downto 0);
signal rx_led, tx_led : std_logic_vector(3 downto 0);
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
- attribute syn_keep of led_counter : signal is true;
- attribute syn_keep of reset_i : signal is true;
- attribute syn_preserve of reset_i : signal is true;
+
signal reset_word_cnt : std_logic_vector(19 downto 0);
signal make_trbnet_reset : std_logic_vector(3 downto 0);
signal send_reset_words : std_logic_vector(3 downto 0);
+ signal send_resync : std_logic_vector(3 downto 0);
signal tx_correct : std_logic_vector(7 downto 0);
signal first_idle : std_logic_vector(3 downto 0);
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+ attribute syn_keep of led_counter : signal is true;
+ attribute syn_keep of reset_i : signal is true;
+ attribute syn_preserve of reset_i : signal is true;
+ attribute syn_keep of send_resync : signal is true;
+ attribute syn_preserve of send_resync : signal is true;
+
begin
--------------------------------------------------------------------------
THE_SFP_STATUS_SYNC: signal_sync
generic map(
DEPTH => 3,
- WIDTH => 2
+ WIDTH => 3
)
port map(
RESET => reset_i(i),
D_IN(0) => SD_PRSNT_N_IN(i),
D_IN(1) => SD_LOS_IN(i),
+ D_IN(2) => CTRL_OP(i*16+15),
CLK0 => SYSCLK,
CLK1 => SYSCLK,
D_OUT(0) => sfp_prsnt_n(i),
- D_OUT(1) => sfp_los(i)
+ D_OUT(1) => sfp_los(i),
+ D_OUT(2) => send_resync(i)
);
-- Transfering the komma delimiter in the *training* phase
LOCATE COMP "TAD_7" SITE "T9";
LOCATE COMP "TAD_8" SITE "R10";
DEFINE PORT GROUP "tad_grp" "TAD*" ;
- IOBUF GROUP "tad_grp" IO_TYPE=LVTTL33 PULLMODE=UP ;
+ IOBUF GROUP "tad_grp" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
LOCATE COMP "CMS" SITE "R2";
LOCATE COMP "GDE" SITE "F16";
# LOCATE COMP "INITN" SITE "H11";
LOCATE COMP "MODD" SITE "P3";
+ IOBUF PORT "MODD" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
# LOCATE COMP "PROGRAMN" SITE "N12";
LOCATE COMP "RDYI" SITE "P16";
LOCATE COMP "RES" SITE "P4";
+ IOBUF PORT "RES" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
LOCATE COMP "TACK" SITE "P14";
# LOCATE COMP "TADS_0" SITE "N9";
# LOCATE COMP "TADS_1" SITE "P10";
# LOCATE COMP "TENB" SITE "T11";
# LOCATE COMP "TENR" SITE "T13";
LOCATE COMP "TOK" SITE "P2";
+ IOBUF PORT "TOK" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
# LOCATE COMP "TOR" SITE "R14";
LOCATE COMP "TRDYO" SITE "P15";
# LOCATE COMP "TREN" SITE "T12";
LOCATE COMP "TRSV" SITE "T4";
LOCATE COMP "WRM" SITE "R15";
+ IOBUF PORT "WRM" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
# LOCATE COMP "ADI_0" SITE "L9";
# LOCATE COMP "ADI_1" SITE "M9";
-#################################################################
+################################################################
#Logic Analyzer Connection (Jan)
#################################################################
# LOCATE COMP "LB_0" SITE "L9";
STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48);
-STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(19 downto 16);
-STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(19 downto 16);
+STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(23 downto 16);
+STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(23 downto 16);
STAT_API1(11) <= apl_to_buf_REPLY_READ(3);
STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3);
REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
--following ports only used when using internal data port
signal buf_IDRAM_WR_IN : std_logic;
signal reset_no_link : std_logic;
- signal buf_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ signal buf_COMMON_STAT_REG_STROBE : std_logic_vector((std_COMSTATREG)-1 downto 0);
+ signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0);
signal buf_STAT_REG_STROBE : std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
signal buf_CTRL_REG_STROBE : std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
signal int_trigger_num : std_logic_vector(15 downto 0);
signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
+ signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;
signal buf_LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
signal temperature : std_logic_vector(11 downto 0);
proc_internal_trigger_number : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_no_link = '1' then
int_trigger_num <= (others => '1');
- else
- if buf_COMMON_CTRL_REG_STROBE(1) = '1' then
- int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
- elsif TRIGGER_MONITOR_IN = '1' then
- int_trigger_num <= int_trigger_num + 1;
- end if;
+ elsif TRIGGER_MONITOR_IN = '1' then
+ int_trigger_num <= int_trigger_num + 1;
+ elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then
+ int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
end if;
end if;
end process;
proc_check_trigger_number : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
trigger_number_match <= '1';
- else
- if LVL1_TRG_RECEIVED_OUT_rising = '1' then
- if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then
- trigger_number_match <= '1';
- else
- trigger_number_match <= '0';
- end if;
+ elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then
+ if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then
+ trigger_number_match <= '1';
+ else
+ trigger_number_match <= '0';
end if;
end if;
end if;
if rising_edge(CLK) then
last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
+ LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT;
- if RESET = '1' or LVL1_TRG_RELEASE_IN = '1' then
+ if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
got_timing_trigger <= '0';
elsif TRIGGER_MONITOR_IN = '1' then
got_timing_trigger <= '1';
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_REGS : out std_logic_vector (16*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
signal HC_READ_IN : std_logic;
signal HC_RUN_OUT : std_logic;
signal HC_SEQNR_OUT : std_logic_vector (7 downto 0);
- signal HC_STAT_REGS : std_logic_vector (2**3*32-1 downto 0);
+ signal HC_STAT_REGS : std_logic_vector (2**4*32-1 downto 0);
+ signal STAT_REG_STROBE : std_logic_vector (2**4-1 downto 0);
signal HC_CTRL_REGS : std_logic_vector (2**3*32-1 downto 0);
signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal buf_HC_STAT_REGS : std_logic_vector (2**3*32-1 downto 0);
+ signal buf_HC_STAT_REGS : std_logic_vector (2**4*32-1 downto 0);
signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
signal DAT_UNKNOWN_ADDR_IN : std_logic := '0';
signal DAT_TIMEOUT_OUT : std_logic;
+ signal STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0);
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_preserve of m_DATA_IN : signal is true;
STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16),
STAT_locked => HUB_locked(i),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
+ STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
);
STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0),
STAT_locked => HUB_locked(i),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
+ STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
STAT_FSM => stat_ipu_fsm,
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
---------------------------------------------------------------------
hub_control : trb_net16_regIO
generic map(
- NUM_STAT_REGS => 3,
+ NUM_STAT_REGS => 4,
NUM_CTRL_REGS => 3,
INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
REGISTERS_OUT => HC_CTRL_REGS,
COMMON_STAT_REG_IN => HC_COMMON_STAT_REGS,
COMMON_CTRL_REG_OUT => HC_COMMON_CTRL_REGS,
+ COMMON_STAT_REG_STROBE => open,
+ COMMON_CTRL_REG_STROBE => open,
+ STAT_REG_STROBE => STAT_REG_STROBE,
+ CTRL_REG_STROBE => open,
--Port to write Unique ID
IDRAM_DATA_IN => IDRAM_DATA_IN,
IDRAM_DATA_OUT => open,
buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked;
buf_HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED;
buf_HC_STAT_REGS(5*32+15 downto 5*32) <= stat_ipu_fsm;
- buf_HC_STAT_REGS(8*32-1 downto 5*32+16) <= (others => '0'); --unused regs
+ buf_HC_STAT_REGS(8*32-1 downto 5*32+16) <= (others => '0'); --unused regs
+ buf_HC_STAT_REGS(16*32-1 downto 12*32) <= (others => '0'); --unused regs
+
+ PROC_TIMEOUT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or STAT_REG_STROBE(8) = '1' then
+ buf_HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0');
+ else
+ buf_HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or buf_HC_STAT_REGS(8*32+31 downto 8*32);
+ end if;
+ if RESET = '1' or STAT_REG_STROBE(9) = '1' then
+ buf_HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0');
+ else
+ buf_HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or buf_HC_STAT_REGS(9*32+31 downto 9*32);
+ end if;
+ if RESET = '1' or STAT_REG_STROBE(10) = '1' then
+ buf_HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0');
+ else
+ buf_HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or buf_HC_STAT_REGS(10*32+31 downto 10*32);
+ end if;
+ if RESET = '1' or STAT_REG_STROBE(11) = '1' then
+ buf_HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0');
+ else
+ buf_HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or buf_HC_STAT_REGS(11*32+31 downto 11*32);
+ end if;
+ end if;
+ end process;
+
PROC_LED : process(CLK)
begin
STAT_DEBUG : out std_logic_vector (31 downto 0);
STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
STAT : out std_logic_vector (15 downto 0);
STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0)
);
STAT_DEBUG : out std_logic_vector (31 downto 0);
STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
timeout_found <= or_all(connection_timed_out);
- if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then
+ if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then
connection_timed_out(i) <= '1';
--Debugging
----------------------------------
+
+ STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= connection_timed_out;
+ STAT_TIMEOUT(31 downto POINT_NUMBER) <= (others => '0');
+
+
STAT_DEBUG(0) <= got_trm(0);
STAT_DEBUG(1) <= got_trm(1);
STAT_DEBUG(2) <= REPLY_POOL_DATAREADY;
STAT : out std_logic_vector (15 downto 0);
STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
+ STAT_TIMEOUT : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
);
----------------------------------
--Debugging
----------------------------------
+
+ STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= connection_timed_out;
+ STAT_TIMEOUT(31 downto POINT_NUMBER) <= (others => '0');
+
STAT(0) <= got_trm(0);
STAT(1) <= got_trm(1);
STAT(2) <= REPLY_POOL_DATAREADY;
CLK => CLK,
RESET => reset_i_mux_io,
CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN(2),
- MED_DATA_IN => MED_DATA_IN(47 downto 32),
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(8 downto 6),
- MED_READ_OUT => MED_READ_OUT(2),
- MED_DATAREADY_OUT => MED_DATAREADY_OUT(2),
- MED_DATA_OUT => MED_DATA_OUT(47 downto 32),
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(8 downto 6),
- MED_READ_IN => MED_READ_IN(2),
+ MED_DATAREADY_IN => MED_DATAREADY_IN(mii),
+ MED_DATA_IN => MED_DATA_IN(mii*3+15 downto mii*16),
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN(mii*3+2 downto mii*3),
+ MED_READ_OUT => MED_READ_OUT(mii),
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT(mii),
+ MED_DATA_OUT => MED_DATA_OUT(mii*3+15 downto mii*16),
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(mii*3+2 downto mii*3),
+ MED_READ_IN => MED_READ_IN(mii),
INT_DATAREADY_OUT => io_dataready_in,
INT_DATA_OUT => io_data_in,
INT_PACKET_NUM_OUT => io_packet_num_in,
INT_READ_OUT <= buf_INT_READ_OUT;
buf_INT_READ_OUT <= not int_dataready_in_i or reg_INT_READ_OUT;
+
SYNC_INT_DATA_INPUTS : process(CLK)
begin
if rising_edge(CLK) then
end process;
-- gen_sbuf : if SECURE_MODE = 1 generate
- SBUF:trb_net16_sbuf
+ THE_SBUF : trb_net16_sbuf
generic map (
VERSION => SBUF_VERSION
)
MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
comb_read <= '1';
- process(CLK)
+ process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
max_DATA_COUNT_minus_one <= (others => '0');
end generate;
- GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, int_data_in_i,
- CURRENT_DATA_COUNT, CRC, saved_packet_type,buffer_number, CTRL_BUFFER)
+ GENERATE_WORDS : process (transfer_counter)
+-- , SEND_BUFFER_SIZE_IN, int_data_in_i,
+-- CURRENT_DATA_COUNT, CRC, saved_packet_type,buffer_number, CTRL_BUFFER)
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
- gen_crc : if USE_CHECKSUM = 1 generate
+ GEN_CRC : if USE_CHECKSUM = 1 generate
CRC_gen : trb_net_CRC
port map(
CLK => CLK,
CRC_OUT => CRC,
CRC_match => crc_match
);
- end generate;
- gen_no_crc : if USE_CHECKSUM = 0 generate
+ end generate GEN_CRC;
+
+ GEN_NO_CRC : if USE_CHECKSUM = 0 generate
CRC <= (others => '0');
end generate;
TRANSMITTED_BUFFERS <= (others => '0');
end generate;
- gen2 : if USE_ACKNOWLEDGE = 1 generate
+ GEN2 : if USE_ACKNOWLEDGE = 1 generate
REG_DATA_COUNT : process(CLK)
begin
if rising_edge(CLK) then
end if;
end if;
end if;
- end process;
+ end process reg_TRANSMITTED_BUFFERS;
end generate;
STAT_DEBUG(0) <= comb_dataready;
STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0);
STAT_DEBUG(20) <= '1';
STAT_DEBUG(31 downto 21) <= (others => '0');
-end architecture;
\ No newline at end of file
+end architecture;
REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
--strobes for r/w operations on regio registers
- COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);
STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
--Internal Data Port
signal local_time_i : std_logic_vector(7 downto 0) := (others => '0');
signal us_tick_i : std_logic := '0';
signal global_time_write, next_global_time_write : std_logic;
- signal next_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- signal next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
- signal next_next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ signal next_COMMON_STAT_REG_STROBE : std_logic_vector((std_COMSTATREG)-1 downto 0);
+ signal next_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0);
+ signal next_next_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0);
signal next_STAT_REG_STROBE : std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
signal next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
signal next_next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
--- can only be used in combination with term_ibuf -> no check for packet type!
-
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
begin
- g1: if USE_TRG_PORT = 1 generate
+ g1: if USE_TRG_PORT = c_YES generate
TRG_TYPE_OUT <= reg_TRG_TYPE_OUT;
TRG_CODE_OUT <= reg_TRG_CODE_OUT;
TRG_NUMBER_OUT <= reg_TRG_NUMBER_OUT;
TRG_INFORMATION_OUT <= reg_TRG_INFORMATION_OUT;
TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT;
INT_READ_OUT <= '1'; --not send_trm and not reg_APL_GOT_TRM;
- end generate;
- g1n: if USE_TRG_PORT = 0 generate
+ end generate;
+
+ g1n: if USE_TRG_PORT = c_NO generate
TRG_TYPE_OUT <= (others => '0');
TRG_CODE_OUT <= (others => '0');
TRG_NUMBER_OUT <= (others => '0');
TRG_INFORMATION_OUT <= (others => '0');
TRG_RECEIVED_OUT <= '0';
INT_READ_OUT <= '1'; --not send_trm;
- end generate;
+ end generate;
process(RESET, transfer_counter, INT_READ_IN, saved_packet_type, buf_TRG_ERROR_PATTERN_IN,
reg_TRG_INFORMATION_OUT, reg_TRG_RECEIVED_OUT, INT_PACKET_NUM_IN, INT_DATA_IN,
buf_INT_DATA_OUT, TRG_RELEASE_IN, send_trm, buf_INT_DATAREADY_OUT)
begin
- next_seqnr <= (others => '0');
if USE_TRG_PORT = 1 then
next_TRG_TYPE_OUT <= reg_TRG_TYPE_OUT;
next_TRG_CODE_OUT <= reg_TRG_CODE_OUT;
next_TRG_CODE_OUT <= reg_TRG_CODE_OUT;
next_TRG_INFORMATION_OUT <= reg_TRG_INFORMATION_OUT;
next_TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT;
- next_seqnr <= (others => '0');
- if saved_packet_type = TYPE_TRM then
+ next_seqnr <= seqnr;
+ if saved_packet_type = TYPE_TRM and INT_DATAREADY_IN = '1' then
if INT_PACKET_NUM_IN = c_F1 then
next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 8);
next_TRG_CODE_OUT <= INT_DATA_IN(7 downto 0);
elsif INT_PACKET_NUM_IN = c_F2 then
- next_TRG_NUMBER_OUT(15 downto 0) <= INT_DATA_IN(15 downto 0);
+ next_TRG_NUMBER_OUT <= INT_DATA_IN(15 downto 0);
elsif INT_PACKET_NUM_IN = c_F3 then
next_TRG_TYPE_OUT <= INT_DATA_IN(3 downto 0);
next_seqnr <= INT_DATA_IN(11 downto 4);
next_TRG_RECEIVED_OUT <= '1';
end if;
end if;
- end if;
+ end if;
next_send_trm <= '0';
next_INT_DATAREADY_OUT <= '0';
next_INT_DATA_OUT <= buf_INT_DATA_OUT;
- if (reg_TRG_RECEIVED_OUT = '1' and (TRG_RELEASE_IN = '1' or USE_TRG_PORT = 0)) or send_trm = '1' then
+ if (reg_TRG_RECEIVED_OUT = '1' and (TRG_RELEASE_IN = '1' or USE_TRG_PORT = c_NO)) or send_trm = '1' then
--next_transfer_counter is used for transmission!
if transfer_counter = c_F3_next and INT_READ_IN = '1' then
next_send_trm <= '0';
if rising_edge(CLK) then
if RESET = '1' then
buf_TRG_ERROR_PATTERN_IN <= (others => '0');
- elsif CLK_EN = '1' and TRG_RELEASE_IN = '1' then
+ elsif TRG_RELEASE_IN = '1' then
buf_TRG_ERROR_PATTERN_IN <= TRG_ERROR_PATTERN_IN;
end if;
end if;
if rising_edge(CLK) then
if RESET = '1' then
transfer_counter <= c_H0;
- elsif CLK_EN = '1' and buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
+ elsif buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
if transfer_counter = c_max_word_number then
transfer_counter <= (others => '0');
else
if RESET = '1' then
buf_INT_DATA_OUT <= "0000000000000" & TYPE_TRM;
buf_INT_DATAREADY_OUT <= '0';
- elsif CLK_EN = '1' then
+ else
buf_INT_DATA_OUT <= next_INT_DATA_OUT;
buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT;
end if;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or (INT_PACKET_NUM_IN = c_F3 and INT_DATAREADY_IN = '1') then --or
+ if RESET = '1' then --or
saved_packet_type <= "111";
- elsif CLK_EN = '1' and INT_PACKET_NUM_IN = c_H0 then
+ elsif INT_PACKET_NUM_IN = c_H0 then
saved_packet_type <= INT_DATA_IN(2 downto 0);
end if;
end if;
REG_send_trm: process(CLK)
begin
- if rising_edge(CLK) then
- if RESET = '1' then
- send_trm <= '0';
- reg_TRG_RECEIVED_OUT <= '0';
- reg_TRG_NUMBER_OUT <= (others => '0');
- elsif CLK_EN = '1' then
- send_trm <= next_send_trm;
- reg_TRG_RECEIVED_OUT <= next_TRG_RECEIVED_OUT;
- reg_TRG_NUMBER_OUT <= next_TRG_NUMBER_OUT;
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ send_trm <= '0';
+ reg_TRG_RECEIVED_OUT <= '0';
+ reg_TRG_NUMBER_OUT <= (others => '0');
+ else
+ send_trm <= next_send_trm;
+ reg_TRG_RECEIVED_OUT <= next_TRG_RECEIVED_OUT;
+ reg_TRG_NUMBER_OUT <= next_TRG_NUMBER_OUT;
+ end if;
end if;
- end if;
- end process;
+ end process;
g2: if USE_TRG_PORT = 1 generate
CLK_REG: process(CLK)
reg_TRG_TYPE_OUT <= (others => '0');
reg_TRG_CODE_OUT <= (others => '0');
reg_TRG_INFORMATION_OUT <= (others => '0');
- elsif CLK_EN = '1' then
+ else
reg_TRG_TYPE_OUT <= next_TRG_TYPE_OUT;
reg_TRG_CODE_OUT <= next_TRG_CODE_OUT;
reg_TRG_INFORMATION_OUT <= next_TRG_INFORMATION_OUT;
REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);
STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
--following ports only used when using internal data port
component trb_net16_regIO is
generic (
- NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers
NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
--standard values for output registers
INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
--Custom Register in / out
REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);
STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
--Internal Data Port
constant std_USE_REPLY_CHANNEL: integer := c_YES;
constant std_FIFO_DEPTH : integer := c_FIFO_BRAM;
constant std_DATA_COUNT_WIDTH : integer := 7; --max 7
- constant std_TERM_SECURE_MODE : integer := c_NO;
+ constant std_TERM_SECURE_MODE : integer := c_YES;
constant std_MUX_SECURE_MODE : integer := c_NO;
constant std_FORCE_REPLY : integer := c_YES;
constant cfg_USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
jspc29 / trbnet.git / commitdiff