<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass/gth_xcku_2gbps4_120mhz_txprogdiv240_txbufbypass.xci">
+ <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz_txprogdiv240/gth_xcku_2gbps4_120mhz_txprogdiv240.xci">
+ <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_bit_sync.v">
+ <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v">
+ <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gtwizard_ultrascale_v1_7_reset_inv_sync.v">
+ <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/ip/vio_0/vio_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/ip/clk_wiz_1/clk_wiz_1.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/src/tx_phase_aligner/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_top.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/src/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PPRDIR/../src/hub/trb_net16_cri_hub_slwcntrl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd">
+ <File Path="$PPRDIR/src/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/src/hub_test.vhd">
+ <File Path="$PPRDIR/src/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/vitis_workspace/init/Release/init.elf">
- <FileInfo>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="ScopedToRef" Val="design_1"/>
- <Attr Name="ScopedToCell" Val="microblaze_0"/>
- <Attr Name="IsVisible" Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/ip/clk_wiz_0/clk_wiz_0.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/ip/clk_wiz_1/clk_wiz_1.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../trbnet/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci">
+ <File Path="$PPRDIR/../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../trbnet/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci">
+ <File Path="$PPRDIR/src/hub_test.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/ip/vio_0/vio_0.xci">
+ <File Path="$PPRDIR/vitis_workspace/init/Release/init.elf">
<FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
+ <Attr Name="ScopedToRef" Val="design_1"/>
+ <Attr Name="ScopedToCell" Val="microblaze_0"/>
+ <Attr Name="IsVisible" Val="1"/>
</FileInfo>
</File>
<Config>
<Attr Name="ScopedToRef" Val="trb_net_reset_handler"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/constrs/debug_tx_phase_aligner.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="ScopedToRef" Val="tx_phase_aligner"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
library unisim;
use unisim.vcomponents.all;
+library xpm;
+use xpm.vcomponents.all;
+
library work;
use work.config.all;
use work.trb_net_std.all;
use work.version.all;
entity hub_test is
- generic (
- BYPASS_TXBUF : integer range 0 to 1 := 1
- );
port (
CLK_200_P : in std_logic;
CLK_200_N : in std_logic;
);
end component;
- component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx is
- generic (
- P_BUFFER_BYPASS_MODE : integer;
- P_TOTAL_NUMBER_OF_CHANNELS : integer;
- P_MASTER_CHANNEL_POINTER : integer
- );
- port (
- gtwiz_buffbypass_tx_clk_in : in std_logic;
- gtwiz_buffbypass_tx_reset_in : in std_logic;
- gtwiz_buffbypass_tx_start_user_in : in std_logic;
- gtwiz_buffbypass_tx_resetdone_in : in std_logic;
- gtwiz_buffbypass_tx_done_out : out std_logic;
- gtwiz_buffbypass_tx_error_out : out std_logic;
- txphaligndone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphinitdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlysresetdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txsyncout_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txsyncdone_in : in std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphdlyreset_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphalign_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphalignen_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphdlypd_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphinit_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphovrden_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlysreset_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlybypass_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlyen_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlyovrden_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txphdlytstclk_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlyhold_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txdlyupdown_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txsyncmode_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txsyncallin_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0);
- txsyncin_out : out std_logic_vector(P_TOTAL_NUMBER_OF_CHANNELS - 1 downto 0)
- );
- end component gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx;
-
signal clk_200_ibuf : std_logic;
signal baseclk_100 : std_logic;
signal mb_ext_resets_n : std_logic_vector(7 downto 0);
signal mgtrefclk_uplink_bufg : std_logic;
signal mgtrefclk_uplink_bufg_half : std_logic;
- signal downlink_usrclk : std_logic;
- signal downlink_usrclk_double : std_logic;
- signal downlink_usrclk_active : std_logic;
- signal not_downlink_usrclk_active : std_logic;
-
signal initial_clear_timer : unsigned(27 downto 0) := (others => '0');
signal initial_clear_n : std_logic := '0';
+ signal tx_aligned : std_logic_vector(INTERFACE_NUM - 2 downto 0);
+ constant DOWNLINK_ONES : std_logic_vector(INTERFACE_NUM - 2 downto 0)
+ := (others => '1');
+
signal reset_from_vio : std_logic;
signal reset_from_net : std_logic;
+ signal clear_in : std_logic;
+
signal send_reset_in : std_logic;
signal send_reset_detect : std_logic;
signal med2int_i : med2int_array_t(0 to 10);
signal int2med_i : int2med_array_t(0 to 10);
- signal txoutclk : std_logic_vector(0 to INTERFACE_NUM - 2);
- signal txprgdivresetdone : std_logic_vector(0 to INTERFACE_NUM - 2);
-
- signal txresetdone : std_logic_vector(0 to INTERFACE_NUM - 2);
-
- signal txdlybypass : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlyen : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlyhold : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlyovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlysreset : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlyupdown : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphalign : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphalignen : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphdlypd : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphdlyreset : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphdlytstclk : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphinit : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphovrden : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txsyncallin : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txsyncin : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txsyncmode : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txdlysresetdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphaligndone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txphinitdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txsyncdone : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal txsyncout : std_logic_vector(INTERFACE_NUM - 2 downto 0);
- signal buffbypass_tx_start_user : std_logic := '0';
- signal buffbypass_tx_done : std_logic;
- signal buffbypass_tx_error : std_logic;
-
signal ctrlbus_rx_i : CTRLBUS_RX;
signal bussci1_rx : CTRLBUS_RX;
signal bussci2_rx : CTRLBUS_RX;
);
not_sysclk_locked <= not sysclk_locked;
- downlink_usrclk_active <= txprgdivresetdone(0);
- not_downlink_usrclk_active <= not downlink_usrclk_active;
-
- THE_DOWNLINK_USRCLK_DOUBLE : BUFG_GT
- port map (
- O => downlink_usrclk_double,
- CE => '1',
- CEMASK => '0',
- CLR => not_downlink_usrclk_active,
- CLRMASK => '0',
- DIV => "000",
- I => txoutclk(0)
- );
-
- THE_DOWNLINK_USRCLK : BUFG_GT
- port map (
- O => downlink_usrclk,
- CE => '1',
- CEMASK => '0',
- CLR => not_downlink_usrclk_active,
- CLRMASK => '0',
- DIV => "001",
- I => txoutclk(0)
- );
-
THE_MGTREFCLK0_232 : IBUFDS_GTE3
generic map (
REFCLK_EN_TX_PATH => '0',
trb_reset <= reset_from_net or (send_reset_detect and not send_reset_in);
+ clear_in <= '1' when reset_from_vio = '1' or tx_aligned /= DOWNLINK_ONES
+ else '0';
THE_RESET_HANDLER : entity work.trb_net_reset_handler
generic map (
RESET_DELAY => x"FEEE"
)
port map (
- CLEAR_IN => reset_from_vio,
+ CLEAR_IN => clear_in,
CLEAR_N_IN => initial_clear_n,
CLK_IN => sysclk_120,
SYSCLK_IN => sysclk_120,
IS_SYNC_SLAVE => c_YES,
LINE_RATE_KBPS => 2000000,
REFCLK_FREQ_HZ => 200000000,
- USE_TXPROGDIV => 0,
- BYPASS_TXBUF => 0
+ SOFT_RESET_TX => 1
)
port map (
SYSCLK => sysclk_120,
CLK_100 => baseclk_100,
+ RESET_ALL => '0',
GTREFCLK => mgtrefclk_uplink,
GTREFCLK_BUFG => mgtrefclk_uplink_bufg,
RXOUTCLK => open,
generate_downlinks:
for linknum in 0 to INTERFACE_NUM - 2 generate
+ signal drpaddr : std_logic_vector(8 downto 0);
+ signal drpdi : std_logic_vector(15 downto 0);
+ signal drpen : std_logic;
+ signal drpwe : std_logic;
+ signal drpdo : std_logic_vector(15 downto 0);
+ signal drprdy : std_logic;
+
+ signal txpippmen : std_logic;
+ signal txpippmovrden : std_logic;
+ signal txpippmpd : std_logic;
+ signal txpippmsel : std_logic;
+ signal txpippmstepsize : std_logic_vector(4 downto 0);
+
+ signal txbufstatus : std_logic_vector(1 downto 0);
+
+ signal txresetdone : std_logic;
+ signal not_txresetdone : std_logic;
+ signal reset_tx_phase_aligner : std_logic;
begin
THE_DOWNLINK : entity work.med_xcku_sfp_sync
generic map (
IS_SYNC_SLAVE => c_NO,
LINE_RATE_KBPS => 2400000,
REFCLK_FREQ_HZ => 120000000,
- USE_TXPROGDIV => 1,
- BYPASS_TXBUF => BYPASS_TXBUF
+ SOFT_RESET_TX => 0
)
port map (
SYSCLK => sysclk_120,
CLK_100 => baseclk_100,
+ RESET_ALL => not_sysclk_locked,
GTREFCLK => mgtrefclk_downlink,
GTREFCLK_BUFG => mgtrefclk_downlink_bufg,
RXOUTCLK => open,
- TXOUTCLK => txoutclk(linknum),
- RXUSRCLK => downlink_usrclk,
- RXUSRCLK_DOUBLE => downlink_usrclk_double,
- TXUSRCLK => downlink_usrclk,
- TXUSRCLK_DOUBLE => downlink_usrclk_double,
- RXUSRCLK_ACTIVE => downlink_usrclk_active,
- TXUSRCLK_ACTIVE => downlink_usrclk_active,
+ TXOUTCLK => open,
+ RXUSRCLK => sysclk_120,
+ RXUSRCLK_DOUBLE => sysclk_240,
+ TXUSRCLK => sysclk_120,
+ TXUSRCLK_DOUBLE => sysclk_240,
+ RXUSRCLK_ACTIVE => sysclk_locked,
+ TXUSRCLK_ACTIVE => sysclk_locked,
RXPMARESETDONE => open,
TXPMARESETDONE => open,
RXRESETDONE => open,
- TXRESETDONE => txresetdone(linknum),
+ TXRESETDONE => txresetdone,
RESET => reset,
CLEAR => clear,
RXN => RXN(linknum),
SD_TXDIS_OUT => mpod_d_txdis(linknum + 3),
STAT_DEBUG => open,
CTRL_DEBUG => (others => '0'),
- TXPRGDIVRESETDONE => txprgdivresetdone(linknum),
- TXDLYBYPASS => txdlybypass(linknum),
- TXDLYEN => txdlyen(linknum),
- TXDLYHOLD => txdlyhold(linknum),
- TXDLYOVRDEN => txdlyovrden(linknum),
- TXDLYSRESET => txdlysreset(linknum),
- TXDLYUPDOWN => txdlyupdown(linknum),
- TXPHALIGN => txphalign(linknum),
- TXPHALIGNEN => txphalignen(linknum),
- TXPHDLYPD => txphdlypd(linknum),
- TXPHDLYRESET => txphdlyreset(linknum),
- TXPHDLYTSTCLK => txphdlytstclk(linknum),
- TXPHINIT => txphinit(linknum),
- TXPHOVRDEN => txphovrden(linknum),
- TXSYNCALLIN => txsyncallin(linknum),
- TXSYNCIN => txsyncin(linknum),
- TXSYNCMODE => txsyncmode(linknum),
- TXDLYSRESETDONE => txdlysresetdone(linknum),
- TXPHALIGNDONE => txphaligndone(linknum),
- TXPHINITDONE => txphinitdone(linknum),
- TXSYNCDONE => txsyncdone(linknum),
- TXSYNCOUT => txsyncout(linknum)
+ DRPADDR => drpaddr,
+ DRPCLK => baseclk_100,
+ DRPDI => drpdi,
+ DRPEN => drpen,
+ DRPWE => drpwe,
+ DRPDO => drpdo,
+ DRPRDY => drprdy,
+ TXPIPPMEN => txpippmen,
+ TXPIPPMOVRDEN => txpippmovrden,
+ TXPIPPMPD => txpippmpd,
+ TXPIPPMSEL => txpippmsel,
+ TXPIPPMSTEPSIZE => txpippmstepsize,
+ TXBUFSTATUS => txbufstatus
);
- end generate generate_downlinks;
- generate_bypass_txbuf:
- if BYPASS_TXBUF = 1 generate
- begin
- buffbypass_tx_i : gtwizard_ultrascale_v1_7_8_gtwiz_buffbypass_tx
+ not_txresetdone <= not txresetdone;
+
+ xpm_cdc_async_rst_tx_phase_aligner : xpm_cdc_async_rst
+ generic map (
+ DEST_SYNC_FF => 4,
+ INIT_SYNC_FF => 0,
+ RST_ACTIVE_HIGH => 1
+ )
+ port map (
+ dest_arst => reset_tx_phase_aligner,
+ dest_clk => baseclk_100,
+ src_arst => not_txresetdone
+ );
+
+ tx_phase_aligner_i : entity work.tx_phase_aligner
generic map (
- P_BUFFER_BYPASS_MODE => 0,
- P_TOTAL_NUMBER_OF_CHANNELS => INTERFACE_NUM - 1,
- P_MASTER_CHANNEL_POINTER => 0
+ g_DRP_NPORT_CTRL => true,
+ g_DRP_ADDR_TXPI_PPM_CFG => "010011010"
)
port map (
- gtwiz_buffbypass_tx_clk_in => sysclk_120,
- gtwiz_buffbypass_tx_reset_in => not_sysclk_locked,
- gtwiz_buffbypass_tx_start_user_in => buffbypass_tx_start_user,
- gtwiz_buffbypass_tx_resetdone_in => txresetdone(0), -- TODO: OR of all channels?
- gtwiz_buffbypass_tx_done_out => buffbypass_tx_done,
- gtwiz_buffbypass_tx_error_out => buffbypass_tx_error,
- txphaligndone_in => txphaligndone,
- txphinitdone_in => txphinitdone,
- txdlysresetdone_in => txdlysresetdone,
- txsyncout_in => txsyncout,
- txsyncdone_in => txsyncdone,
- txphdlyreset_out => txphdlyreset,
- txphalign_out => txphalign,
- txphalignen_out => txphalignen,
- txphdlypd_out => txphdlypd,
- txphinit_out => txphinit,
- txphovrden_out => txphovrden,
- txdlysreset_out => txdlysreset,
- txdlybypass_out => txdlybypass,
- txdlyen_out => txdlyen,
- txdlyovrden_out => txdlyovrden,
- txphdlytstclk_out => txphdlytstclk,
- txdlyhold_out => txdlyhold,
- txdlyupdown_out => txdlyupdown,
- txsyncmode_out => txsyncmode,
- txsyncallin_out => txsyncallin,
- txsyncin_out => txsyncin
+ clk_sys_i => baseclk_100,
+ reset_i => reset_tx_phase_aligner,
+ tx_aligned_o => tx_aligned(linknum),
+ tx_pi_phase_calib_i => "0000000", -- (FINE_ALIGNMENT)
+ tx_ui_align_calib_i => '0', -- (FINE_ALIGNMENT)
+ tx_fifo_fill_pd_max_i => x"00040000",
+ tx_fine_realign_i => '0',
+ ps_strobe_i => '0',
+ ps_inc_ndec_i => '0',
+ ps_phase_step_i => "0000",
+ ps_done_o => open,
+ tx_pi_phase_o => open,
+ tx_fifo_fill_pd_o => open,
+ clk_txusr_i => sysclk_120,
+ tx_fifo_fill_level_i => txbufstatus(0),
+ txpippmen_o => txpippmen,
+ txpippmovrden_o => txpippmovrden,
+ txpippmsel_o => txpippmsel,
+ txpippmpd_o => txpippmpd,
+ txpippmstepsize_o => txpippmstepsize,
+ drpaddr_o => drpaddr,
+ drpen_o => drpen,
+ drpdi_o => drpdi,
+ drprdy_i => drprdy,
+ drpdo_i => drpdo,
+ drpwe_o => drpwe
);
- end generate generate_bypass_txbuf;
+ end generate generate_downlinks;
-- Create a 100 ns test pulse for debugging of microslice timing
process (sysclk_240) is
jspc29 / cri.git / commitdiff